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Wed, 10 Sep 2025 00:12:50 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 10 Sep 2025 09:12:37 +0200 Subject: [PATCH v2 01/15] gpio: loongson1: allow building the module with COMPILE_TEST enabled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-gpio-mmio-gpio-conv-part4-v2-1-f3d1a4c57124@linaro.org> References: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> In-Reply-To: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Keguang Zhang , Alban Bedel , Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Matthias Brugger , AngeloGioacchino Del Regno , Paul Walmsley , Samuel Holland , Yixun Lan , Andy Shevchenko Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Increase build coverage by allowing the module to be built with COMPILE_TEST=3Dy. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 31f8bab4b09df1640c892f4d839860edaa2ad6a3..09cb144f076661e0a2069016175= d0692257fb156 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -885,7 +885,7 @@ config GPIO_ZYNQMP_MODEPIN =20 config GPIO_LOONGSON1 tristate "Loongson1 GPIO support" - depends on MACH_LOONGSON32 + depends on MACH_LOONGSON32 || COMPILE_TEST select GPIO_GENERIC help Say Y or M here to support GPIO on Loongson1 SoCs. --=20 2.48.1 From nobody Thu Oct 2 22:39:58 2025 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F6F5308F3E for ; Wed, 10 Sep 2025 07:12:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-loongson1.c | 40 +++++++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/drivers/gpio/gpio-loongson1.c b/drivers/gpio/gpio-loongson1.c index 6ca3b969db4df231517d021a7b4b5e3ddcf626f7..9750a7a175081781624a49a7949= 26b3f1e45b4d2 100644 --- a/drivers/gpio/gpio-loongson1.c +++ b/drivers/gpio/gpio-loongson1.c @@ -5,10 +5,11 @@ * Copyright (C) 2015-2023 Keguang Zhang */ =20 +#include #include #include +#include #include -#include =20 /* Loongson 1 GPIO Register Definitions */ #define GPIO_CFG 0x0 @@ -17,19 +18,18 @@ #define GPIO_OUTPUT 0x30 =20 struct ls1x_gpio_chip { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *reg_base; }; =20 static int ls1x_gpio_request(struct gpio_chip *gc, unsigned int offset) { struct ls1x_gpio_chip *ls1x_gc =3D gpiochip_get_data(gc); - unsigned long flags; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&ls1x_gc->chip); + __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) | BIT(offset), ls1x_gc->reg_base + GPIO_CFG); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); =20 return 0; } @@ -37,16 +37,16 @@ static int ls1x_gpio_request(struct gpio_chip *gc, unsi= gned int offset) static void ls1x_gpio_free(struct gpio_chip *gc, unsigned int offset) { struct ls1x_gpio_chip *ls1x_gc =3D gpiochip_get_data(gc); - unsigned long flags; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&ls1x_gc->chip); + __raw_writel(__raw_readl(ls1x_gc->reg_base + GPIO_CFG) & ~BIT(offset), ls1x_gc->reg_base + GPIO_CFG); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 static int ls1x_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct ls1x_gpio_chip *ls1x_gc; int ret; @@ -59,29 +59,35 @@ static int ls1x_gpio_probe(struct platform_device *pdev) if (IS_ERR(ls1x_gc->reg_base)) return PTR_ERR(ls1x_gc->reg_base); =20 - ret =3D bgpio_init(&ls1x_gc->gc, dev, 4, ls1x_gc->reg_base + GPIO_DATA, - ls1x_gc->reg_base + GPIO_OUTPUT, NULL, - NULL, ls1x_gc->reg_base + GPIO_DIR, 0); + config =3D (struct gpio_generic_chip_config) { + .dev =3D dev, + .sz =3D 4, + .dat =3D ls1x_gc->reg_base + GPIO_DATA, + .set =3D ls1x_gc->reg_base + GPIO_OUTPUT, + .dirin =3D ls1x_gc->reg_base + GPIO_DIR, + }; + + ret =3D gpio_generic_chip_init(&ls1x_gc->chip, &config); if (ret) goto err; =20 - ls1x_gc->gc.owner =3D THIS_MODULE; - ls1x_gc->gc.request =3D ls1x_gpio_request; - ls1x_gc->gc.free =3D ls1x_gpio_free; + ls1x_gc->chip.gc.owner =3D THIS_MODULE; + ls1x_gc->chip.gc.request =3D ls1x_gpio_request; + ls1x_gc->chip.gc.free =3D ls1x_gpio_free; /* * Clear ngpio to let gpiolib get the correct number * by reading ngpios property */ - ls1x_gc->gc.ngpio =3D 0; + ls1x_gc->chip.gc.ngpio =3D 0; =20 - ret =3D devm_gpiochip_add_data(dev, &ls1x_gc->gc, ls1x_gc); + ret =3D devm_gpiochip_add_data(dev, &ls1x_gc->chip.gc, ls1x_gc); if (ret) goto err; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-hlwd.c | 105 ++++++++++++++++++++++++-------------------= ---- 1 file changed, 54 insertions(+), 51 deletions(-) diff --git a/drivers/gpio/gpio-hlwd.c b/drivers/gpio/gpio-hlwd.c index 0580f6712bea9a4d510bd332645982adbc5c6a32..a395f87436ac4df386ce2ee345f= c0a7cc34c843d 100644 --- a/drivers/gpio/gpio-hlwd.c +++ b/drivers/gpio/gpio-hlwd.c @@ -6,6 +6,7 @@ // Nintendo Wii (Hollywood) GPIO driver =20 #include +#include #include #include #include @@ -48,7 +49,7 @@ #define HW_GPIO_OWNER 0x3c =20 struct hlwd_gpio { - struct gpio_chip gpioc; + struct gpio_generic_chip gpioc; struct device *dev; void __iomem *regs; int irq; @@ -61,45 +62,44 @@ static void hlwd_gpio_irqhandler(struct irq_desc *desc) struct hlwd_gpio *hlwd =3D gpiochip_get_data(irq_desc_get_handler_data(desc)); struct irq_chip *chip =3D irq_desc_get_chip(desc); - unsigned long flags; unsigned long pending; int hwirq; u32 emulated_pending; =20 - raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); - pending =3D ioread32be(hlwd->regs + HW_GPIOB_INTFLAG); - pending &=3D ioread32be(hlwd->regs + HW_GPIOB_INTMASK); + scoped_guard(gpio_generic_lock_irqsave, &hlwd->gpioc) { + pending =3D ioread32be(hlwd->regs + HW_GPIOB_INTFLAG); + pending &=3D ioread32be(hlwd->regs + HW_GPIOB_INTMASK); =20 - /* Treat interrupts due to edge trigger emulation separately */ - emulated_pending =3D hlwd->edge_emulation & pending; - pending &=3D ~emulated_pending; - if (emulated_pending) { - u32 level, rising, falling; + /* Treat interrupts due to edge trigger emulation separately */ + emulated_pending =3D hlwd->edge_emulation & pending; + pending &=3D ~emulated_pending; + if (emulated_pending) { + u32 level, rising, falling; =20 - level =3D ioread32be(hlwd->regs + HW_GPIOB_INTLVL); - rising =3D level & emulated_pending; - falling =3D ~level & emulated_pending; + level =3D ioread32be(hlwd->regs + HW_GPIOB_INTLVL); + rising =3D level & emulated_pending; + falling =3D ~level & emulated_pending; =20 - /* Invert the levels */ - iowrite32be(level ^ emulated_pending, - hlwd->regs + HW_GPIOB_INTLVL); + /* Invert the levels */ + iowrite32be(level ^ emulated_pending, + hlwd->regs + HW_GPIOB_INTLVL); =20 - /* Ack all emulated-edge interrupts */ - iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG); + /* Ack all emulated-edge interrupts */ + iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG); =20 - /* Signal interrupts only on the correct edge */ - rising &=3D hlwd->rising_edge; - falling &=3D hlwd->falling_edge; + /* Signal interrupts only on the correct edge */ + rising &=3D hlwd->rising_edge; + falling &=3D hlwd->falling_edge; =20 - /* Mark emulated interrupts as pending */ - pending |=3D rising | falling; + /* Mark emulated interrupts as pending */ + pending |=3D rising | falling; + } } - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); =20 chained_irq_enter(chip, desc); =20 for_each_set_bit(hwirq, &pending, 32) - generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq); + generic_handle_domain_irq(hlwd->gpioc.gc.irq.domain, hwirq); =20 chained_irq_exit(chip, desc); } @@ -116,30 +116,29 @@ static void hlwd_gpio_irq_mask(struct irq_data *data) { struct hlwd_gpio *hlwd =3D gpiochip_get_data(irq_data_get_irq_chip_data(data)); - unsigned long flags; u32 mask; =20 - raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); - mask =3D ioread32be(hlwd->regs + HW_GPIOB_INTMASK); - mask &=3D ~BIT(data->hwirq); - iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); - gpiochip_disable_irq(&hlwd->gpioc, irqd_to_hwirq(data)); + scoped_guard(gpio_generic_lock_irqsave, &hlwd->gpioc) { + mask =3D ioread32be(hlwd->regs + HW_GPIOB_INTMASK); + mask &=3D ~BIT(data->hwirq); + iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); + } + gpiochip_disable_irq(&hlwd->gpioc.gc, irqd_to_hwirq(data)); } =20 static void hlwd_gpio_irq_unmask(struct irq_data *data) { struct hlwd_gpio *hlwd =3D gpiochip_get_data(irq_data_get_irq_chip_data(data)); - unsigned long flags; u32 mask; =20 - gpiochip_enable_irq(&hlwd->gpioc, irqd_to_hwirq(data)); - raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); + gpiochip_enable_irq(&hlwd->gpioc.gc, irqd_to_hwirq(data)); + + guard(gpio_generic_lock_irqsave)(&hlwd->gpioc); + mask =3D ioread32be(hlwd->regs + HW_GPIOB_INTMASK); mask |=3D BIT(data->hwirq); iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); } =20 static void hlwd_gpio_irq_enable(struct irq_data *data) @@ -173,10 +172,9 @@ static int hlwd_gpio_irq_set_type(struct irq_data *dat= a, unsigned int flow_type) { struct hlwd_gpio *hlwd =3D gpiochip_get_data(irq_data_get_irq_chip_data(data)); - unsigned long flags; u32 level; =20 - raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&hlwd->gpioc); =20 hlwd->edge_emulation &=3D ~BIT(data->hwirq); =20 @@ -197,11 +195,9 @@ static int hlwd_gpio_irq_set_type(struct irq_data *dat= a, unsigned int flow_type) hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type); break; default: - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); return -EINVAL; } =20 - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); return 0; } =20 @@ -225,6 +221,7 @@ static const struct irq_chip hlwd_gpio_irq_chip =3D { =20 static int hlwd_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct hlwd_gpio *hlwd; u32 ngpios; int res; @@ -244,25 +241,31 @@ static int hlwd_gpio_probe(struct platform_device *pd= ev) * systems where the AHBPROT memory firewall hasn't been configured to * permit PPC access to HW_GPIO_*. * - * Note that this has to happen before bgpio_init reads the - * HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the wrong - * values. + * Note that this has to happen before gpio_generic_chip_init() reads + * the HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the + * wrong values. */ iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER); =20 - res =3D bgpio_init(&hlwd->gpioc, &pdev->dev, 4, - hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT, - NULL, hlwd->regs + HW_GPIOB_DIR, NULL, - BGPIOF_BIG_ENDIAN_BYTE_ORDER); + config =3D (struct gpio_generic_chip_config) { + .dev =3D &pdev->dev, + .sz =3D 4, + .dat =3D hlwd->regs + HW_GPIOB_IN, + .set =3D hlwd->regs + HW_GPIOB_OUT, + .dirout =3D hlwd->regs + HW_GPIOB_DIR, + .flags =3D BGPIOF_BIG_ENDIAN_BYTE_ORDER, + }; + + res =3D gpio_generic_chip_init(&hlwd->gpioc, &config); if (res < 0) { - dev_warn(&pdev->dev, "bgpio_init failed: %d\n", res); + dev_warn(&pdev->dev, "failed to initialize generic GPIO chip: %d\n", res= ); return res; } =20 res =3D of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios); if (res) ngpios =3D 32; - hlwd->gpioc.ngpio =3D ngpios; + hlwd->gpioc.gc.ngpio =3D ngpios; =20 /* Mask and ack all interrupts */ iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK); @@ -282,7 +285,7 @@ static int hlwd_gpio_probe(struct platform_device *pdev) return hlwd->irq; } =20 - girq =3D &hlwd->gpioc.irq; + girq =3D &hlwd->gpioc.gc.irq; gpio_irq_chip_set_chip(girq, &hlwd_gpio_irq_chip); girq->parent_handler =3D hlwd_gpio_irqhandler; girq->num_parents =3D 1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ath79.c | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/gpio/gpio-ath79.c b/drivers/gpio/gpio-ath79.c index de4cc12e5e0399abcef61a89c8c91a1b203d20fb..8879f23f1871ed323513082f4d2= ebb2c40544cde 100644 --- a/drivers/gpio/gpio-ath79.c +++ b/drivers/gpio/gpio-ath79.c @@ -10,6 +10,7 @@ =20 #include #include +#include #include #include #include @@ -28,7 +29,7 @@ #define AR71XX_GPIO_REG_INT_MASK 0x24 =20 struct ath79_gpio_ctrl { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *base; raw_spinlock_t lock; unsigned long both_edges; @@ -37,8 +38,9 @@ struct ath79_gpio_ctrl { static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *dat= a) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(data); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); =20 - return container_of(gc, struct ath79_gpio_ctrl, gc); + return container_of(gen_gc, struct ath79_gpio_ctrl, chip); } =20 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) @@ -72,7 +74,7 @@ static void ath79_gpio_irq_unmask(struct irq_data *data) u32 mask =3D BIT(irqd_to_hwirq(data)); unsigned long flags; =20 - gpiochip_enable_irq(&ctrl->gc, irqd_to_hwirq(data)); + gpiochip_enable_irq(&ctrl->chip.gc, irqd_to_hwirq(data)); raw_spin_lock_irqsave(&ctrl->lock, flags); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); raw_spin_unlock_irqrestore(&ctrl->lock, flags); @@ -87,7 +89,7 @@ static void ath79_gpio_irq_mask(struct irq_data *data) raw_spin_lock_irqsave(&ctrl->lock, flags); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); raw_spin_unlock_irqrestore(&ctrl->lock, flags); - gpiochip_disable_irq(&ctrl->gc, irqd_to_hwirq(data)); + gpiochip_disable_irq(&ctrl->chip.gc, irqd_to_hwirq(data)); } =20 static void ath79_gpio_irq_enable(struct irq_data *data) @@ -187,8 +189,9 @@ static void ath79_gpio_irq_handler(struct irq_desc *des= c) { struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); struct irq_chip *irqchip =3D irq_desc_get_chip(desc); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct ath79_gpio_ctrl *ctrl =3D - container_of(gc, struct ath79_gpio_ctrl, gc); + container_of(gen_gc, struct ath79_gpio_ctrl, chip); unsigned long flags, pending; u32 both_edges, state; int irq; @@ -224,6 +227,7 @@ MODULE_DEVICE_TABLE(of, ath79_gpio_of_match); =20 static int ath79_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct ath79_gpio_ctrl *ctrl; struct gpio_irq_chip *girq; @@ -253,21 +257,26 @@ static int ath79_gpio_probe(struct platform_device *p= dev) return PTR_ERR(ctrl->base); =20 raw_spin_lock_init(&ctrl->lock); - err =3D bgpio_init(&ctrl->gc, dev, 4, - ctrl->base + AR71XX_GPIO_REG_IN, - ctrl->base + AR71XX_GPIO_REG_SET, - ctrl->base + AR71XX_GPIO_REG_CLEAR, - oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE, - oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL, - 0); + + config =3D (struct gpio_generic_chip_config) { + .dev =3D dev, + .sz =3D 4, + .dat =3D ctrl->base + AR71XX_GPIO_REG_IN, + .set =3D ctrl->base + AR71XX_GPIO_REG_SET, + .clr =3D ctrl->base + AR71XX_GPIO_REG_CLEAR, + .dirout =3D oe_inverted ? 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski This driver uses its own raw spinlock in interrupt routines while the generic GPIO chip callbacks use a separate one. This is, of course, racy so use the fact that the lock in generic GPIO chip is also a raw spinlock and convert the interrupt handling functions in this module to using the provided generic GPIO chip locking API. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ath79.c | 51 ++++++++++++++++++-------------------------= ---- 1 file changed, 19 insertions(+), 32 deletions(-) diff --git a/drivers/gpio/gpio-ath79.c b/drivers/gpio/gpio-ath79.c index 8879f23f1871ed323513082f4d2ebb2c40544cde..2ad9f6ac66362fba8cdab152a2b= 2c782dddf427c 100644 --- a/drivers/gpio/gpio-ath79.c +++ b/drivers/gpio/gpio-ath79.c @@ -31,7 +31,6 @@ struct ath79_gpio_ctrl { struct gpio_generic_chip chip; void __iomem *base; - raw_spinlock_t lock; unsigned long both_edges; }; =20 @@ -72,23 +71,22 @@ static void ath79_gpio_irq_unmask(struct irq_data *data) { struct ath79_gpio_ctrl *ctrl =3D irq_data_to_ath79_gpio(data); u32 mask =3D BIT(irqd_to_hwirq(data)); - unsigned long flags; =20 gpiochip_enable_irq(&ctrl->chip.gc, irqd_to_hwirq(data)); - raw_spin_lock_irqsave(&ctrl->lock, flags); + + guard(gpio_generic_lock_irqsave)(&ctrl->chip); + ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); - raw_spin_unlock_irqrestore(&ctrl->lock, flags); } =20 static void ath79_gpio_irq_mask(struct irq_data *data) { struct ath79_gpio_ctrl *ctrl =3D irq_data_to_ath79_gpio(data); u32 mask =3D BIT(irqd_to_hwirq(data)); - unsigned long flags; =20 - raw_spin_lock_irqsave(&ctrl->lock, flags); - ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); - raw_spin_unlock_irqrestore(&ctrl->lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) + ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); + gpiochip_disable_irq(&ctrl->chip.gc, irqd_to_hwirq(data)); } =20 @@ -96,24 +94,20 @@ static void ath79_gpio_irq_enable(struct irq_data *data) { struct ath79_gpio_ctrl *ctrl =3D irq_data_to_ath79_gpio(data); u32 mask =3D BIT(irqd_to_hwirq(data)); - unsigned long flags; =20 - raw_spin_lock_irqsave(&ctrl->lock, flags); + guard(gpio_generic_lock_irqsave)(&ctrl->chip); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); - raw_spin_unlock_irqrestore(&ctrl->lock, flags); } =20 static void ath79_gpio_irq_disable(struct irq_data *data) { struct ath79_gpio_ctrl *ctrl =3D irq_data_to_ath79_gpio(data); u32 mask =3D BIT(irqd_to_hwirq(data)); - unsigned long flags; =20 - raw_spin_lock_irqsave(&ctrl->lock, flags); + guard(gpio_generic_lock_irqsave)(&ctrl->chip); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); - raw_spin_unlock_irqrestore(&ctrl->lock, flags); } =20 static int ath79_gpio_irq_set_type(struct irq_data *data, @@ -122,7 +116,6 @@ static int ath79_gpio_irq_set_type(struct irq_data *dat= a, struct ath79_gpio_ctrl *ctrl =3D irq_data_to_ath79_gpio(data); u32 mask =3D BIT(irqd_to_hwirq(data)); u32 type =3D 0, polarity =3D 0; - unsigned long flags; bool disabled; =20 switch (flow_type) { @@ -144,7 +137,7 @@ static int ath79_gpio_irq_set_type(struct irq_data *dat= a, return -EINVAL; } =20 - raw_spin_lock_irqsave(&ctrl->lock, flags); + guard(gpio_generic_lock_irqsave)(&ctrl->chip); =20 if (flow_type =3D=3D IRQ_TYPE_EDGE_BOTH) { ctrl->both_edges |=3D mask; @@ -169,8 +162,6 @@ static int ath79_gpio_irq_set_type(struct irq_data *dat= a, ath79_gpio_update_bits( ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); =20 - raw_spin_unlock_irqrestore(&ctrl->lock, flags); - return 0; } =20 @@ -192,26 +183,24 @@ static void ath79_gpio_irq_handler(struct irq_desc *d= esc) struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct ath79_gpio_ctrl *ctrl =3D container_of(gen_gc, struct ath79_gpio_ctrl, chip); - unsigned long flags, pending; + unsigned long pending; u32 both_edges, state; int irq; =20 chained_irq_enter(irqchip, desc); =20 - raw_spin_lock_irqsave(&ctrl->lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) { + pending =3D ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); =20 - pending =3D ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); - - /* Update the polarity of the both edges irqs */ - both_edges =3D ctrl->both_edges & pending; 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Wed, 10 Sep 2025 00:13:03 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:3936:709a:82c4:3e38]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45df81d20d2sm16357035e9.8.2025.09.10.00.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 00:13:02 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 10 Sep 2025 09:12:42 +0200 Subject: [PATCH v2 06/15] gpio: xgene-sb: use generic GPIO chip register read and write APIs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-gpio-mmio-gpio-conv-part4-v2-6-f3d1a4c57124@linaro.org> References: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> In-Reply-To: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Keguang Zhang , Alban Bedel , Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Matthias Brugger , AngeloGioacchino Del Regno , Paul Walmsley , Samuel Holland , Yixun Lan , Andy Shevchenko Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski The conversion to using the modernized generic GPIO chip API was incomplete without also converting the direct calls to write/read_reg() callbacks. Use the provided wrappers from linux/gpio/generic.h. Fixes: 38d98a822c14 ("gpio: xgene-sb: use new generic GPIO chip API") Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-xgene-sb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-xgene-sb.c b/drivers/gpio/gpio-xgene-sb.c index c559a89aadf7a77bd9cce7e5a7d4a2b241307812..62545e358b6c4b1cab25e1135cb= 24ccc3e955078 100644 --- a/drivers/gpio/gpio-xgene-sb.c +++ b/drivers/gpio/gpio-xgene-sb.c @@ -63,14 +63,15 @@ struct xgene_gpio_sb { static void xgene_gpio_set_bit(struct gpio_chip *gc, void __iomem *reg, u32 gpio, int val) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); u32 data; =20 - data =3D gc->read_reg(reg); + data =3D gpio_generic_read_reg(chip, reg); if (val) data |=3D GPIO_MASK(gpio); else data &=3D ~GPIO_MASK(gpio); - gc->write_reg(reg, data); + gpio_generic_write_reg(chip, reg, data); } =20 static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int typ= e) --=20 2.48.1 From nobody Thu Oct 2 22:39:58 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E8F130C616 for ; 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Wed, 10 Sep 2025 00:13:05 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:3936:709a:82c4:3e38]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45df81d20d2sm16357035e9.8.2025.09.10.00.13.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 00:13:04 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 10 Sep 2025 09:12:43 +0200 Subject: [PATCH v2 07/15] gpio: brcmstb: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-gpio-mmio-gpio-conv-part4-v2-7-f3d1a4c57124@linaro.org> References: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> In-Reply-To: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Keguang Zhang , Alban Bedel , Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Matthias Brugger , AngeloGioacchino Del Regno , Paul Walmsley , Samuel Holland , Yixun Lan , Andy Shevchenko Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Acked-by: Doug Berger Reviewed-by: Florian Fainelli Reviewed-by: Linus Walleij Tested-by: Florian Fainelli --- drivers/gpio/gpio-brcmstb.c | 112 ++++++++++++++++++++++++----------------= ---- 1 file changed, 60 insertions(+), 52 deletions(-) diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c index e29a9589b3ccbd17d10f6671088dca3e76537927..be3ff916e134a674d3e1d334a7d= 431b7ad767a33 100644 --- a/drivers/gpio/gpio-brcmstb.c +++ b/drivers/gpio/gpio-brcmstb.c @@ -3,6 +3,7 @@ =20 #include #include +#include #include #include #include @@ -37,7 +38,7 @@ enum gio_reg_index { struct brcmstb_gpio_bank { struct list_head node; int id; - struct gpio_chip gc; + struct gpio_generic_chip chip; struct brcmstb_gpio_priv *parent_priv; u32 width; u32 wake_active; @@ -72,19 +73,18 @@ __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank= *bank) { void __iomem *reg_base =3D bank->parent_priv->reg_base; =20 - return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) & - bank->gc.read_reg(reg_base + GIO_MASK(bank->id)); + return gpio_generic_read_reg(&bank->chip, reg_base + GIO_STAT(bank->id)) & + gpio_generic_read_reg(&bank->chip, reg_base + GIO_MASK(bank->id)); } =20 static unsigned long brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) { unsigned long status; - unsigned long flags; =20 - raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&bank->chip); + status =3D __brcmstb_gpio_get_active_irqs(bank); - raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); =20 return status; } @@ -92,26 +92,26 @@ brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *= bank) static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq, struct brcmstb_gpio_bank *bank) { - return hwirq - bank->gc.offset; + return hwirq - bank->chip.gc.offset; } =20 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, unsigned int hwirq, bool enable) { - struct gpio_chip *gc =3D &bank->gc; struct brcmstb_gpio_priv *priv =3D bank->parent_priv; u32 mask =3D BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); u32 imask; - unsigned long flags; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); - imask =3D gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); + guard(gpio_generic_lock_irqsave)(&bank->chip); + + imask =3D gpio_generic_read_reg(&bank->chip, + priv->reg_base + GIO_MASK(bank->id)); if (enable) imask |=3D mask; else imask &=3D ~mask; - gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + gpio_generic_write_reg(&bank->chip, + priv->reg_base + GIO_MASK(bank->id), imask); } =20 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) @@ -150,7 +150,8 @@ static void brcmstb_gpio_irq_ack(struct irq_data *d) struct brcmstb_gpio_priv *priv =3D bank->parent_priv; u32 mask =3D BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); =20 - gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask); + gpio_generic_write_reg(&bank->chip, + priv->reg_base + GIO_STAT(bank->id), mask); } =20 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type) @@ -162,7 +163,6 @@ static int brcmstb_gpio_irq_set_type(struct irq_data *d= , unsigned int type) u32 edge_insensitive, iedge_insensitive; u32 edge_config, iedge_config; u32 level, ilevel; - unsigned long flags; =20 switch (type) { case IRQ_TYPE_LEVEL_LOW: @@ -194,23 +194,25 @@ static int brcmstb_gpio_irq_set_type(struct irq_data = *d, unsigned int type) return -EINVAL; } =20 - raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&bank->chip); =20 - iedge_config =3D bank->gc.read_reg(priv->reg_base + - GIO_EC(bank->id)) & ~mask; - iedge_insensitive =3D bank->gc.read_reg(priv->reg_base + - GIO_EI(bank->id)) & ~mask; - ilevel =3D bank->gc.read_reg(priv->reg_base + - GIO_LEVEL(bank->id)) & ~mask; + iedge_config =3D gpio_generic_read_reg(&bank->chip, + priv->reg_base + GIO_EC(bank->id)) & ~mask; + iedge_insensitive =3D gpio_generic_read_reg(&bank->chip, + priv->reg_base + GIO_EI(bank->id)) & ~mask; + ilevel =3D gpio_generic_read_reg(&bank->chip, + priv->reg_base + GIO_LEVEL(bank->id)) & ~mask; =20 - bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id), - iedge_config | edge_config); - bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id), - iedge_insensitive | edge_insensitive); - bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), - ilevel | level); + gpio_generic_write_reg(&bank->chip, + priv->reg_base + GIO_EC(bank->id), + iedge_config | edge_config); + gpio_generic_write_reg(&bank->chip, + priv->reg_base + GIO_EI(bank->id), + iedge_insensitive | edge_insensitive); + gpio_generic_write_reg(&bank->chip, + priv->reg_base + GIO_LEVEL(bank->id), + ilevel | level); =20 - raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); return 0; } =20 @@ -263,7 +265,7 @@ static void brcmstb_gpio_irq_bank_handler(struct brcmst= b_gpio_bank *bank) { struct brcmstb_gpio_priv *priv =3D bank->parent_priv; struct irq_domain *domain =3D priv->irq_domain; - int hwbase =3D bank->gc.offset; + int hwbase =3D bank->chip.gc.offset; unsigned long status; =20 while ((status =3D brcmstb_gpio_get_active_irqs(bank))) { @@ -303,7 +305,7 @@ static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_= bank( =20 /* banks are in descending order */ list_for_each_entry_reverse(bank, &priv->bank_list, node) { - i +=3D bank->gc.ngpio; + i +=3D bank->chip.gc.ngpio; if (hwirq < i) return bank; } @@ -332,7 +334,7 @@ static int brcmstb_gpio_irq_map(struct irq_domain *d, u= nsigned int irq, =20 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n", irq, (int)hwirq, bank->id); - ret =3D irq_set_chip_data(irq, &bank->gc); + ret =3D irq_set_chip_data(irq, &bank->chip.gc); if (ret < 0) return ret; irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class, @@ -394,7 +396,7 @@ static void brcmstb_gpio_remove(struct platform_device = *pdev) * more important to actually perform all of the steps. */ list_for_each_entry(bank, &priv->bank_list, node) - gpiochip_remove(&bank->gc); + gpiochip_remove(&bank->chip.gc); } =20 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc, @@ -412,7 +414,7 @@ static int brcmstb_gpio_of_xlate(struct gpio_chip *gc, if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) return -EINVAL; =20 - offset =3D gpiospec->args[0] - bank->gc.offset; + offset =3D gpiospec->args[0] - bank->chip.gc.offset; if (offset >=3D gc->ngpio || offset < 0) return -EINVAL; =20 @@ -493,19 +495,17 @@ static int brcmstb_gpio_irq_setup(struct platform_dev= ice *pdev, static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv, struct brcmstb_gpio_bank *bank) { - struct gpio_chip *gc =3D &bank->gc; unsigned int i; =20 for (i =3D 0; i < GIO_REG_STAT; i++) - bank->saved_regs[i] =3D gc->read_reg(priv->reg_base + - GIO_BANK_OFF(bank->id, i)); + bank->saved_regs[i] =3D gpio_generic_read_reg(&bank->chip, + priv->reg_base + GIO_BANK_OFF(bank->id, i)); } =20 static void brcmstb_gpio_quiesce(struct device *dev, bool save) { struct brcmstb_gpio_priv *priv =3D dev_get_drvdata(dev); struct brcmstb_gpio_bank *bank; - struct gpio_chip *gc; u32 imask; =20 /* disable non-wake interrupt */ @@ -513,8 +513,6 @@ static void brcmstb_gpio_quiesce(struct device *dev, bo= ol save) disable_irq(priv->parent_irq); =20 list_for_each_entry(bank, &priv->bank_list, node) { - gc =3D &bank->gc; - if (save) brcmstb_gpio_bank_save(priv, bank); =20 @@ -523,8 +521,9 @@ static void brcmstb_gpio_quiesce(struct device *dev, bo= ol save) imask =3D bank->wake_active; else imask =3D 0; - gc->write_reg(priv->reg_base + GIO_MASK(bank->id), - imask); + gpio_generic_write_reg(&bank->chip, + priv->reg_base + GIO_MASK(bank->id), + imask); } } =20 @@ -538,12 +537,12 @@ static void brcmstb_gpio_shutdown(struct platform_dev= ice *pdev) static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv, struct brcmstb_gpio_bank *bank) { - struct gpio_chip *gc =3D &bank->gc; unsigned int i; =20 for (i =3D 0; i < GIO_REG_STAT; i++) - gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i), - bank->saved_regs[i]); + gpio_generic_write_reg(&bank->chip, + priv->reg_base + GIO_BANK_OFF(bank->id, i), + bank->saved_regs[i]); } =20 static int brcmstb_gpio_suspend(struct device *dev) @@ -585,6 +584,7 @@ static const struct dev_pm_ops brcmstb_gpio_pm_ops =3D { =20 static int brcmstb_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; void __iomem *reg_base; @@ -665,17 +665,24 @@ static int brcmstb_gpio_probe(struct platform_device = *pdev) bank->width =3D bank_width; } =20 + gc =3D &bank->chip.gc; + /* * Regs are 4 bytes wide, have data reg, no set/clear regs, * and direction bits have 0 =3D output and 1 =3D input */ - gc =3D &bank->gc; - err =3D bgpio_init(gc, dev, 4, - reg_base + GIO_DATA(bank->id), - NULL, NULL, NULL, - reg_base + GIO_IODIR(bank->id), flags); + + config =3D (struct gpio_generic_chip_config) { + .dev =3D dev, + .sz =3D 4, + .dat =3D reg_base + GIO_DATA(bank->id), + .dirin =3D reg_base + GIO_IODIR(bank->id), + .flags =3D flags, + }; + + err =3D gpio_generic_chip_init(&bank->chip, &config); if (err) { - dev_err(dev, "bgpio_init() failed\n"); + dev_err(dev, "failed to initialize generic GPIO chip\n"); goto fail; } =20 @@ -700,7 +707,8 @@ static int brcmstb_gpio_probe(struct platform_device *p= dev) * be retained from S5 cold boot */ need_wakeup_event |=3D !!__brcmstb_gpio_get_active_irqs(bank); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mt7621.c | 51 +++++++++++++++++++++++++++++-------------= ---- 1 file changed, 32 insertions(+), 19 deletions(-) diff --git a/drivers/gpio/gpio-mt7621.c b/drivers/gpio/gpio-mt7621.c index 93facbebb80efadbdd3fb4500e0db14936287f1a..e56812a1721151c8f3b32b5093a= ee5c74bb798bc 100644 --- a/drivers/gpio/gpio-mt7621.c +++ b/drivers/gpio/gpio-mt7621.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include #include #include @@ -30,7 +31,7 @@ =20 struct mtk_gc { struct irq_chip irq_chip; - struct gpio_chip chip; + struct gpio_generic_chip chip; spinlock_t lock; int bank; u32 rising; @@ -59,27 +60,29 @@ struct mtk { static inline struct mtk_gc * to_mediatek_gpio(struct gpio_chip *chip) { - return container_of(chip, struct mtk_gc, chip); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(chip); + + return container_of(gen_gc, struct mtk_gc, chip); } =20 static inline void mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val) { - struct gpio_chip *gc =3D &rg->chip; + struct gpio_chip *gc =3D &rg->chip.gc; struct mtk *mtk =3D gpiochip_get_data(gc); =20 offset =3D (rg->bank * GPIO_BANK_STRIDE) + offset; - gc->write_reg(mtk->base + offset, val); + gpio_generic_write_reg(&rg->chip, mtk->base + offset, val); } =20 static inline u32 mtk_gpio_r32(struct mtk_gc *rg, u32 offset) { - struct gpio_chip *gc =3D &rg->chip; + struct gpio_chip *gc =3D &rg->chip.gc; struct mtk *mtk =3D gpiochip_get_data(gc); =20 offset =3D (rg->bank * GPIO_BANK_STRIDE) + offset; - return gc->read_reg(mtk->base + offset); + return gpio_generic_read_reg(&rg->chip, mtk->base + offset); } =20 static irqreturn_t @@ -220,6 +223,7 @@ static const struct irq_chip mt7621_irq_chip =3D { static int mediatek_gpio_bank_probe(struct device *dev, int bank) { + struct gpio_generic_chip_config config; struct mtk *mtk =3D dev_get_drvdata(dev); struct mtk_gc *rg; void __iomem *dat, *set, *ctrl, *diro; @@ -236,21 +240,30 @@ mediatek_gpio_bank_probe(struct device *dev, int bank) ctrl =3D mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE); diro =3D mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE); =20 - ret =3D bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL, - BGPIOF_NO_SET_ON_INPUT); + config =3D (struct gpio_generic_chip_config) { + .dev =3D dev, + .sz =3D 4, + .dat =3D dat, + .set =3D set, + .clr =3D ctrl, + .dirout =3D diro, + .flags =3D BGPIOF_NO_SET_ON_INPUT, + }; + + ret =3D gpio_generic_chip_init(&rg->chip, &config); if (ret) { - dev_err(dev, "bgpio_init() failed\n"); + dev_err(dev, "failed to initialize generic GPIO chip\n"); return ret; } =20 - rg->chip.of_gpio_n_cells =3D 2; - rg->chip.of_xlate =3D mediatek_gpio_xlate; - rg->chip.label =3D devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d", + rg->chip.gc.of_gpio_n_cells =3D 2; + rg->chip.gc.of_xlate =3D mediatek_gpio_xlate; + rg->chip.gc.label =3D devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d", dev_name(dev), bank); - if (!rg->chip.label) + if (!rg->chip.gc.label) return -ENOMEM; =20 - rg->chip.offset =3D bank * MTK_BANK_WIDTH; + rg->chip.gc.offset =3D bank * MTK_BANK_WIDTH; =20 if (mtk->gpio_irq) { struct gpio_irq_chip *girq; @@ -261,7 +274,7 @@ mediatek_gpio_bank_probe(struct device *dev, int bank) */ ret =3D devm_request_irq(dev, mtk->gpio_irq, mediatek_gpio_irq_handler, IRQF_SHARED, - rg->chip.label, &rg->chip); + rg->chip.gc.label, &rg->chip.gc); =20 if (ret) { dev_err(dev, "Error requesting IRQ %d: %d\n", @@ -269,7 +282,7 @@ mediatek_gpio_bank_probe(struct device *dev, int bank) return ret; } =20 - girq =3D &rg->chip.irq; + girq =3D &rg->chip.gc.irq; gpio_irq_chip_set_chip(girq, &mt7621_irq_chip); /* This will let us handle the parent IRQ in the driver */ girq->parent_handler =3D NULL; @@ -279,17 +292,17 @@ mediatek_gpio_bank_probe(struct device *dev, int bank) girq->handler =3D handle_simple_irq; } =20 - ret =3D devm_gpiochip_add_data(dev, &rg->chip, mtk); + ret =3D devm_gpiochip_add_data(dev, &rg->chip.gc, mtk); if (ret < 0) { dev_err(dev, "Could not register gpio %d, ret=3D%d\n", - rg->chip.ngpio, ret); + rg->chip.gc.ngpio, ret); return ret; } =20 /* set polarity to low for all gpios */ mtk_gpio_w32(rg, GPIO_REG_POL, 0); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski This driver uses its own spinlock in interrupt routines while the generic GPIO chip callbacks use a separate one. This is, of course, racy so use the fact that the lock in generic GPIO chip is also a spinlock and convert the interrupt handling functions in this module to using the provided generic GPIO chip locking API. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mt7621.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/drivers/gpio/gpio-mt7621.c b/drivers/gpio/gpio-mt7621.c index e56812a1721151c8f3b32b5093aee5c74bb798bc..e7bb9b2cd6cf32baa71b4185ea2= 74075a7bc2d8f 100644 --- a/drivers/gpio/gpio-mt7621.c +++ b/drivers/gpio/gpio-mt7621.c @@ -11,7 +11,6 @@ #include #include #include -#include =20 #define MTK_BANK_CNT 3 #define MTK_BANK_WIDTH 32 @@ -32,7 +31,6 @@ struct mtk_gc { struct irq_chip irq_chip; struct gpio_generic_chip chip; - spinlock_t lock; int bank; u32 rising; u32 falling; @@ -111,12 +109,12 @@ mediatek_gpio_irq_unmask(struct irq_data *d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct mtk_gc *rg =3D to_mediatek_gpio(gc); int pin =3D d->hwirq; - unsigned long flags; u32 rise, fall, high, low; =20 gpiochip_enable_irq(gc, d->hwirq); =20 - spin_lock_irqsave(&rg->lock, flags); + guard(gpio_generic_lock_irqsave)(&rg->chip); + rise =3D mtk_gpio_r32(rg, GPIO_REG_REDGE); fall =3D mtk_gpio_r32(rg, GPIO_REG_FEDGE); high =3D mtk_gpio_r32(rg, GPIO_REG_HLVL); @@ -125,7 +123,6 @@ mediatek_gpio_irq_unmask(struct irq_data *d) mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling)); mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel)); mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel)); - spin_unlock_irqrestore(&rg->lock, flags); } =20 static void @@ -134,19 +131,18 @@ mediatek_gpio_irq_mask(struct irq_data *d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct mtk_gc *rg =3D to_mediatek_gpio(gc); int pin =3D d->hwirq; - unsigned long flags; u32 rise, fall, high, low; =20 - spin_lock_irqsave(&rg->lock, flags); - rise =3D mtk_gpio_r32(rg, GPIO_REG_REDGE); - fall =3D mtk_gpio_r32(rg, GPIO_REG_FEDGE); - high =3D mtk_gpio_r32(rg, GPIO_REG_HLVL); - low =3D mtk_gpio_r32(rg, GPIO_REG_LLVL); - mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin)); - mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin)); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-menz127.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/gpio-menz127.c b/drivers/gpio/gpio-menz127.c index ebe5da4933bce730c70f83c1c0f86fc4a4cc9906..da2bf9381cc43cd489f6a859363= 6bbbc95ab5660 100644 --- a/drivers/gpio/gpio-menz127.c +++ b/drivers/gpio/gpio-menz127.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 #define MEN_Z127_CTRL 0x00 #define MEN_Z127_PSR 0x04 @@ -30,7 +31,7 @@ (db <=3D MEN_Z127_DB_MAX_US)) =20 struct men_z127_gpio { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *reg_base; struct resource *mem; }; @@ -64,7 +65,7 @@ static int men_z127_debounce(struct gpio_chip *gc, unsign= ed gpio, debounce /=3D 50; } =20 - raw_spin_lock(&gc->bgpio_lock); + guard(gpio_generic_lock)(&priv->chip); =20 db_en =3D readl(priv->reg_base + MEN_Z127_DBER); =20 @@ -79,8 +80,6 @@ static int men_z127_debounce(struct gpio_chip *gc, unsign= ed gpio, writel(db_en, priv->reg_base + MEN_Z127_DBER); writel(db_cnt, priv->reg_base + GPIO_TO_DBCNT_REG(gpio)); =20 - raw_spin_unlock(&gc->bgpio_lock); - return 0; } =20 @@ -91,7 +90,8 @@ static int men_z127_set_single_ended(struct gpio_chip *gc, struct men_z127_gpio *priv =3D gpiochip_get_data(gc); u32 od_en; =20 - raw_spin_lock(&gc->bgpio_lock); + guard(gpio_generic_lock)(&priv->chip); + od_en =3D readl(priv->reg_base + MEN_Z127_ODER); =20 if (param =3D=3D PIN_CONFIG_DRIVE_OPEN_DRAIN) @@ -101,7 +101,6 @@ static int men_z127_set_single_ended(struct gpio_chip *= gc, od_en &=3D ~BIT(offset); =20 writel(od_en, priv->reg_base + MEN_Z127_ODER); - raw_spin_unlock(&gc->bgpio_lock); =20 return 0; } @@ -137,6 +136,7 @@ static void men_z127_release_mem(void *data) static int men_z127_probe(struct mcb_device *mdev, const struct mcb_device_id *id) { + struct gpio_generic_chip_config config; struct men_z127_gpio *men_z127_gpio; struct device *dev =3D &mdev->dev; int ret; @@ -163,18 +163,21 @@ static int men_z127_probe(struct mcb_device *mdev, =20 mcb_set_drvdata(mdev, men_z127_gpio); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Reviewed-by: Samuel Holland --- drivers/gpio/gpio-sifive.c | 73 ++++++++++++++++++++++++------------------= ---- 1 file changed, 38 insertions(+), 35 deletions(-) diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c index 98ef975c44d9a6c9238605cfd1d5820fd70a66ca..2ced87ffd3bbf219c11857391eb= 4ea808adc0527 100644 --- a/drivers/gpio/gpio-sifive.c +++ b/drivers/gpio/gpio-sifive.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -32,7 +33,7 @@ =20 struct sifive_gpio { void __iomem *base; - struct gpio_chip gc; + struct gpio_generic_chip gen_gc; struct regmap *regs; unsigned long irq_state; unsigned int trigger[SIFIVE_GPIO_MAX]; @@ -41,10 +42,10 @@ struct sifive_gpio { =20 static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offs= et) { - unsigned long flags; unsigned int trigger; =20 - raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); + trigger =3D (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0; regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset), (trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0); @@ -54,7 +55,6 @@ static void sifive_gpio_set_ie(struct sifive_gpio *chip, = unsigned int offset) (trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0); regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset), (trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0); - raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags); } =20 static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigg= er) @@ -72,13 +72,12 @@ static int sifive_gpio_irq_set_type(struct irq_data *d,= unsigned int trigger) } =20 static void sifive_gpio_irq_enable(struct irq_data *d) -{ + { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct sifive_gpio *chip =3D gpiochip_get_data(gc); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); int offset =3D hwirq % SIFIVE_GPIO_MAX; u32 bit =3D BIT(offset); - unsigned long flags; =20 gpiochip_enable_irq(gc, hwirq); irq_chip_enable_parent(d); @@ -86,13 +85,13 @@ static void sifive_gpio_irq_enable(struct irq_data *d) /* Switch to input */ gc->direction_input(gc, offset); =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); - /* Clear any sticky pending interrupts */ - regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); - regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); - regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); - regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) { + /* Clear any sticky pending interrupts */ + regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); + regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); + regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); + regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); + } =20 /* Enable interrupts */ assign_bit(offset, &chip->irq_state, 1); @@ -118,15 +117,14 @@ static void sifive_gpio_irq_eoi(struct irq_data *d) struct sifive_gpio *chip =3D gpiochip_get_data(gc); int offset =3D irqd_to_hwirq(d) % SIFIVE_GPIO_MAX; u32 bit =3D BIT(offset); - unsigned long flags; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); - /* Clear all pending interrupts */ - regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); - regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); - regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); - regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) { + /* Clear all pending interrupts */ + regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); + regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); + regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); + regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); + } =20 irq_chip_eoi_parent(d); } @@ -179,6 +177,7 @@ static const struct regmap_config sifive_gpio_regmap_co= nfig =3D { =20 static int sifive_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct irq_domain *parent; struct gpio_irq_chip *girq; @@ -217,13 +216,17 @@ static int sifive_gpio_probe(struct platform_device *= pdev) */ parent =3D irq_get_irq_data(chip->irq_number[0])->domain; =20 - ret =3D bgpio_init(&chip->gc, dev, 4, - chip->base + SIFIVE_GPIO_INPUT_VAL, - chip->base + SIFIVE_GPIO_OUTPUT_VAL, - NULL, - chip->base + SIFIVE_GPIO_OUTPUT_EN, - chip->base + SIFIVE_GPIO_INPUT_EN, - BGPIOF_READ_OUTPUT_REG_SET); + config =3D (struct gpio_generic_chip_config) { + .dev =3D dev, + .sz =3D 4, + .dat =3D chip->base + SIFIVE_GPIO_INPUT_VAL, + .set =3D chip->base + SIFIVE_GPIO_OUTPUT_VAL, + .dirout =3D chip->base + SIFIVE_GPIO_OUTPUT_EN, + .dirin =3D chip->base + SIFIVE_GPIO_INPUT_EN, + .flags =3D BGPIOF_READ_OUTPUT_REG_SET, + }; + + ret =3D gpio_generic_chip_init(&chip->gen_gc, &config); if (ret) { dev_err(dev, "unable to init generic GPIO\n"); return ret; @@ -236,12 +239,12 @@ static int sifive_gpio_probe(struct platform_device *= pdev) regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0); chip->irq_state =3D 0; =20 - chip->gc.base =3D -1; - chip->gc.ngpio =3D ngpio; - chip->gc.label =3D dev_name(dev); - chip->gc.parent =3D dev; - chip->gc.owner =3D THIS_MODULE; - girq =3D &chip->gc.irq; + chip->gen_gc.gc.base =3D -1; + chip->gen_gc.gc.ngpio =3D ngpio; + chip->gen_gc.gc.label =3D dev_name(dev); + chip->gen_gc.gc.parent =3D dev; + chip->gen_gc.gc.owner =3D THIS_MODULE; + girq =3D &chip->gen_gc.gc.irq; gpio_irq_chip_set_chip(girq, &sifive_gpio_irqchip); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Reviewed-by: Yixun Lan Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-spacemit-k1.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k= 1.c index 3cc75c701ec40194e602b80d3f96f23204ce3b4d..a0af23f732819be9329af1cb628= 87dc6eb100ac9 100644 --- a/drivers/gpio/gpio-spacemit-k1.c +++ b/drivers/gpio/gpio-spacemit-k1.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include #include #include @@ -38,7 +39,7 @@ struct spacemit_gpio; =20 struct spacemit_gpio_bank { - struct gpio_chip gc; + struct gpio_generic_chip chip; struct spacemit_gpio *sg; void __iomem *base; u32 irq_mask; @@ -72,7 +73,7 @@ static irqreturn_t spacemit_gpio_irq_handler(int irq, voi= d *dev_id) return IRQ_NONE; =20 for_each_set_bit(n, &pending, BITS_PER_LONG) - handle_nested_irq(irq_find_mapping(gb->gc.irq.domain, n)); + handle_nested_irq(irq_find_mapping(gb->chip.gc.irq.domain, n)); =20 return IRQ_HANDLED; } @@ -143,7 +144,7 @@ static void spacemit_gpio_irq_print_chip(struct irq_dat= a *data, struct seq_file { struct spacemit_gpio_bank *gb =3D irq_data_get_irq_chip_data(data); =20 - seq_printf(p, "%s-%d", dev_name(gb->gc.parent), spacemit_gpio_bank_index(= gb)); + seq_printf(p, "%s-%d", dev_name(gb->chip.gc.parent), spacemit_gpio_bank_i= ndex(gb)); } =20 static struct irq_chip spacemit_gpio_chip =3D { @@ -165,7 +166,7 @@ static bool spacemit_of_node_instance_match(struct gpio= _chip *gc, unsigned int i if (i >=3D SPACEMIT_NR_BANKS) return false; =20 - return (gc =3D=3D &sg->sgb[i].gc); + return (gc =3D=3D &sg->sgb[i].chip.gc); } =20 static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, @@ -173,7 +174,8 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio = *sg, int index, int irq) { struct spacemit_gpio_bank *gb =3D &sg->sgb[index]; - struct gpio_chip *gc =3D &gb->gc; + struct gpio_generic_chip_config config; + struct gpio_chip *gc =3D &gb->chip.gc; struct device *dev =3D sg->dev; struct gpio_irq_chip *girq; void __iomem *dat, *set, *clr, *dirin, *dirout; @@ -187,9 +189,19 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio= *sg, dirin =3D gb->base + SPACEMIT_GCDR; dirout =3D gb->base + SPACEMIT_GSDR; =20 + config =3D (struct gpio_generic_chip_config) { + .dev =3D dev, + .sz =3D 4, + .dat =3D dat, + .set =3D set, + .clr =3D clr, + .dirout =3D dirout, + .dirin =3D dirin, + .flags =3D BGPIOF_UNREADABLE_REG_SET | BGPIOF_UNREADABLE_REG_DIR, + }; + /* This registers 32 GPIO lines per bank */ - ret =3D bgpio_init(gc, dev, 4, dat, set, clr, dirout, dirin, - BGPIOF_UNREADABLE_REG_SET | BGPIOF_UNREADABLE_REG_DIR); + ret =3D gpio_generic_chip_init(&gb->chip, &config); if (ret) return dev_err_probe(dev, ret, "failed to init gpio chip\n"); =20 @@ -221,7 +233,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio = *sg, ret =3D devm_request_threaded_irq(dev, irq, NULL, spacemit_gpio_irq_handler, IRQF_ONESHOT | IRQF_SHARED, - gb->gc.label, gb); + gb->chip.gc.label, gb); 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Wed, 10 Sep 2025 00:13:20 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 10 Sep 2025 09:12:49 +0200 Subject: [PATCH v2 13/15] gpio: sodaville: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-gpio-mmio-gpio-conv-part4-v2-13-f3d1a4c57124@linaro.org> References: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> In-Reply-To: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Keguang Zhang , Alban Bedel , Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Matthias Brugger , AngeloGioacchino Del Regno , Paul Walmsley , Samuel Holland , Yixun Lan , Andy Shevchenko Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij --- drivers/gpio/gpio-sodaville.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/gpio-sodaville.c b/drivers/gpio/gpio-sodaville.c index abd13c79ace09db228e975f93c92e727d3864ef8..37c1338377295fa2995bac98f1a= e2db892209602 100644 --- a/drivers/gpio/gpio-sodaville.c +++ b/drivers/gpio/gpio-sodaville.c @@ -9,6 +9,7 @@ =20 #include #include +#include #include #include #include @@ -39,7 +40,7 @@ struct sdv_gpio_chip_data { void __iomem *gpio_pub_base; struct irq_domain *id; struct irq_chip_generic *gc; - struct gpio_chip chip; + struct gpio_generic_chip gen_gc; }; =20 static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type) @@ -180,6 +181,7 @@ static int sdv_register_irqsupport(struct sdv_gpio_chip= _data *sd, static int sdv_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *pci_id) { + struct gpio_generic_chip_config config; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-mmio.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c index 79e1be149c94842cb6fa6b657343b11e78701220..b4f0ab0daaeb11bd88723f8b1c1= 5bd09225f1d97 100644 --- a/drivers/gpio/gpio-mmio.c +++ b/drivers/gpio/gpio-mmio.c @@ -57,6 +57,7 @@ o ` ~~~~\___/~~~~ ` control= ler in FPGA is ,.` #include =20 #include +#include =20 #include "gpiolib.h" =20 @@ -737,6 +738,8 @@ MODULE_DEVICE_TABLE(of, bgpio_of_match); =20 static int bgpio_pdev_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; + struct gpio_generic_chip *gen_gc; struct device *dev =3D &pdev->dev; struct resource *r; void __iomem *dat; @@ -748,7 +751,6 @@ static int bgpio_pdev_probe(struct platform_device *pde= v) unsigned long flags =3D 0; unsigned int base; int err; - struct gpio_chip *gc; const char *label; =20 r =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); @@ -777,8 +779,8 @@ static int bgpio_pdev_probe(struct platform_device *pde= v) if (IS_ERR(dirin)) return PTR_ERR(dirin); =20 - gc =3D devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); - if (!gc) + gen_gc =3D devm_kzalloc(&pdev->dev, sizeof(*gen_gc), GFP_KERNEL); + if (!gen_gc) return -ENOMEM; =20 if (device_is_big_endian(dev)) @@ -787,13 +789,24 @@ static int bgpio_pdev_probe(struct platform_device *p= dev) if (device_property_read_bool(dev, "no-output")) flags |=3D BGPIOF_NO_OUTPUT; =20 - err =3D bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); + config =3D (struct gpio_generic_chip_config) { + .dev =3D dev, + .sz =3D sz, + .dat =3D dat, + .set =3D set, + .clr =3D clr, + .dirout =3D dirout, + .dirin =3D dirin, + .flags =3D flags, + }; + + err =3D gpio_generic_chip_init(gen_gc, &config); if (err) return err; =20 err =3D device_property_read_string(dev, "label", &label); if (!err) - gc->label =3D label; + gen_gc->gc.label =3D label; =20 /* * This property *must not* be used in device-tree sources, it's only @@ -801,11 +814,11 @@ static int bgpio_pdev_probe(struct platform_device *p= dev) */ err =3D device_property_read_u32(dev, "gpio-mmio,base", &base); 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski With all users of bgpio_init() converted to using the modernized generic GPIO chip API, we can now move the gpio-mmio-specific fields out of struct gpio_chip and into the dedicated struct gpio_generic_chip. To that end: adjust the gpio-mmio driver to the new layout, update the docs, etc. The changes in gpio-mlxbf2.c and gpio-mpc8xxx.c are here and not in their respective conversion commits because the former passes the address of the generic chip's lock to the __releases() annotation and we cannot really hide it while gpio-mpc8xxx.c accesses the shadow registers in a driver-specific workaround and there's no reason to make them available in a public API. Also: drop the relevant task from TODO as it's now done. Signed-off-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/TODO | 5 - drivers/gpio/gpio-mlxbf2.c | 2 +- drivers/gpio/gpio-mmio.c | 321 ++++++++++++++++++++++-----------------= ---- drivers/gpio/gpio-mpc8xxx.c | 5 +- include/linux/gpio/driver.h | 44 ------ include/linux/gpio/generic.h | 67 ++++++--- 6 files changed, 211 insertions(+), 233 deletions(-) diff --git a/drivers/gpio/TODO b/drivers/gpio/TODO index b797499e627ee9fdb1ee9c564b8278241f720850..8ed74e05903a972e99e0789319e= d19ebd8545a1a 100644 --- a/drivers/gpio/TODO +++ b/drivers/gpio/TODO @@ -131,11 +131,6 @@ Work items: helpers (x86 inb()/outb()) and convert port-mapped I/O drivers to use this with dry-coding and sending to maintainers to test =20 -- Move the MMIO GPIO specific fields out of struct gpio_chip into a - dedicated structure. Currently every GPIO chip has them if gpio-mmio is - enabled in Kconfig even if it itself doesn't register with the helper - library. - --------------------------------------------------------------------------= ----- =20 Generic regmap GPIO diff --git a/drivers/gpio/gpio-mlxbf2.c b/drivers/gpio/gpio-mlxbf2.c index f99f66cd189ca71c9d188dff0a0b42ef2223abb3..9520d26b20a5851ac8b5de239b8= f5980dabc2820 100644 --- a/drivers/gpio/gpio-mlxbf2.c +++ b/drivers/gpio/gpio-mlxbf2.c @@ -156,7 +156,7 @@ static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_= context *gs) * Release the YU arm_gpio_lock after changing the direction mode. */ static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs) - __releases(&gs->chip.gc.bgpio_lock) + __releases(&gs->chip.lock) __releases(yu_arm_gpio_lock_param.lock) { writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io); diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c index b4f0ab0daaeb11bd88723f8b1c15bd09225f1d97..a3df14d672a92ac771014315458= cb50933b6c539 100644 --- a/drivers/gpio/gpio-mmio.c +++ b/drivers/gpio/gpio-mmio.c @@ -125,20 +125,23 @@ static unsigned long bgpio_read32be(void __iomem *reg) =20 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int li= ne) { - if (gc->be_bits) - return BIT(gc->bgpio_bits - 1 - line); + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + + if (chip->be_bits) + return BIT(chip->bits - 1 - line); return BIT(line); } =20 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); unsigned long pinmask =3D bgpio_line2mask(gc, gpio); - bool dir =3D !!(gc->bgpio_dir & pinmask); + bool dir =3D !!(chip->sdir & pinmask); =20 if (dir) - return !!(gc->read_reg(gc->reg_set) & pinmask); - else - return !!(gc->read_reg(gc->reg_dat) & pinmask); + return !!(chip->read_reg(chip->reg_set) & pinmask); + + return !!(chip->read_reg(chip->reg_dat) & pinmask); } =20 /* @@ -148,26 +151,28 @@ static int bgpio_get_set(struct gpio_chip *gc, unsign= ed int gpio) static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mas= k, unsigned long *bits) { - unsigned long get_mask =3D 0; - unsigned long set_mask =3D 0; + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + unsigned long get_mask =3D 0, set_mask =3D 0; =20 /* Make sure we first clear any bits that are zero when we read the regis= ter */ *bits &=3D ~*mask; =20 - set_mask =3D *mask & gc->bgpio_dir; - get_mask =3D *mask & ~gc->bgpio_dir; + set_mask =3D *mask & chip->sdir; + get_mask =3D *mask & ~chip->sdir; =20 if (set_mask) - *bits |=3D gc->read_reg(gc->reg_set) & set_mask; + *bits |=3D chip->read_reg(chip->reg_set) & set_mask; if (get_mask) - *bits |=3D gc->read_reg(gc->reg_dat) & get_mask; + *bits |=3D chip->read_reg(chip->reg_dat) & get_mask; =20 return 0; } =20 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) { - return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio)); + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + + return !!(chip->read_reg(chip->reg_dat) & bgpio_line2mask(gc, gpio)); } =20 /* @@ -176,9 +181,11 @@ static int bgpio_get(struct gpio_chip *gc, unsigned in= t gpio) static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + /* Make sure we first clear any bits that are zero when we read the regis= ter */ *bits &=3D ~*mask; - *bits |=3D gc->read_reg(gc->reg_dat) & *mask; + *bits |=3D chip->read_reg(chip->reg_dat) & *mask; return 0; } =20 @@ -188,6 +195,7 @@ static int bgpio_get_multiple(struct gpio_chip *gc, uns= igned long *mask, static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); unsigned long readmask =3D 0; unsigned long val; int bit; @@ -200,7 +208,7 @@ static int bgpio_get_multiple_be(struct gpio_chip *gc, = unsigned long *mask, readmask |=3D bgpio_line2mask(gc, bit); =20 /* Read the register */ - val =3D gc->read_reg(gc->reg_dat) & readmask; + val =3D chip->read_reg(chip->reg_dat) & readmask; =20 /* * Mirror the result into the "bits" result, this will give line 0 @@ -219,19 +227,20 @@ static int bgpio_set_none(struct gpio_chip *gc, unsig= ned int gpio, int val) =20 static int bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); unsigned long mask =3D bgpio_line2mask(gc, gpio); unsigned long flags; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + raw_spin_lock_irqsave(&chip->lock, flags); =20 if (val) - gc->bgpio_data |=3D mask; + chip->sdata |=3D mask; else - gc->bgpio_data &=3D ~mask; + chip->sdata &=3D ~mask; =20 - gc->write_reg(gc->reg_dat, gc->bgpio_data); + chip->write_reg(chip->reg_dat, chip->sdata); =20 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + raw_spin_unlock_irqrestore(&chip->lock, flags); =20 return 0; } @@ -239,31 +248,32 @@ static int bgpio_set(struct gpio_chip *gc, unsigned i= nt gpio, int val) static int bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, int val) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); unsigned long mask =3D bgpio_line2mask(gc, gpio); =20 if (val) - gc->write_reg(gc->reg_set, mask); + chip->write_reg(chip->reg_set, mask); else - gc->write_reg(gc->reg_clr, mask); + chip->write_reg(chip->reg_clr, mask); =20 return 0; } =20 static int bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) { - unsigned long mask =3D bgpio_line2mask(gc, gpio); - unsigned long flags; + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + unsigned long mask =3D bgpio_line2mask(gc, gpio), flags; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + raw_spin_lock_irqsave(&chip->lock, flags); =20 if (val) - gc->bgpio_data |=3D mask; + chip->sdata |=3D mask; else - gc->bgpio_data &=3D ~mask; + chip->sdata &=3D ~mask; =20 - gc->write_reg(gc->reg_set, gc->bgpio_data); + chip->write_reg(chip->reg_set, chip->sdata); =20 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + raw_spin_unlock_irqrestore(&chip->lock, flags); =20 return 0; } @@ -273,12 +283,13 @@ static void bgpio_multiple_get_masks(struct gpio_chip= *gc, unsigned long *set_mask, unsigned long *clear_mask) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); int i; =20 *set_mask =3D 0; *clear_mask =3D 0; =20 - for_each_set_bit(i, mask, gc->bgpio_bits) { + for_each_set_bit(i, mask, chip->bits) { if (test_bit(i, bits)) *set_mask |=3D bgpio_line2mask(gc, i); else @@ -291,25 +302,27 @@ static void bgpio_set_multiple_single_reg(struct gpio= _chip *gc, unsigned long *bits, void __iomem *reg) { - unsigned long flags; - unsigned long set_mask, clear_mask; + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + unsigned long flags, set_mask, clear_mask; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + raw_spin_lock_irqsave(&chip->lock, flags); =20 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); =20 - gc->bgpio_data |=3D set_mask; - gc->bgpio_data &=3D ~clear_mask; + chip->sdata |=3D set_mask; + chip->sdata &=3D ~clear_mask; =20 - gc->write_reg(reg, gc->bgpio_data); + chip->write_reg(reg, chip->sdata); =20 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + raw_spin_unlock_irqrestore(&chip->lock, flags); } =20 static int bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { - bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + + bgpio_set_multiple_single_reg(gc, mask, bits, chip->reg_dat); =20 return 0; } @@ -317,7 +330,9 @@ static int bgpio_set_multiple(struct gpio_chip *gc, uns= igned long *mask, static int bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mas= k, unsigned long *bits) { - bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + + bgpio_set_multiple_single_reg(gc, mask, bits, chip->reg_set); =20 return 0; } @@ -326,21 +341,24 @@ static int bgpio_set_multiple_with_clear(struct gpio_= chip *gc, unsigned long *mask, unsigned long *bits) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); unsigned long set_mask, clear_mask; =20 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); =20 if (set_mask) - gc->write_reg(gc->reg_set, set_mask); + chip->write_reg(chip->reg_set, set_mask); if (clear_mask) - gc->write_reg(gc->reg_clr, clear_mask); + chip->write_reg(chip->reg_clr, clear_mask); =20 return 0; } =20 static int bgpio_dir_return(struct gpio_chip *gc, unsigned int gpio, bool = dir_out) { - if (!gc->bgpio_pinctrl) + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + + if (!chip->pinctrl) return 0; =20 if (dir_out) @@ -375,39 +393,42 @@ static int bgpio_simple_dir_out(struct gpio_chip *gc,= unsigned int gpio, =20 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); unsigned long flags; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + raw_spin_lock_irqsave(&chip->lock, flags); =20 - gc->bgpio_dir &=3D ~bgpio_line2mask(gc, gpio); + chip->sdir &=3D ~bgpio_line2mask(gc, gpio); =20 - if (gc->reg_dir_in) - gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); - if (gc->reg_dir_out) - gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); + if (chip->reg_dir_in) + chip->write_reg(chip->reg_dir_in, ~chip->sdir); + if (chip->reg_dir_out) + chip->write_reg(chip->reg_dir_out, chip->sdir); =20 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + raw_spin_unlock_irqrestore(&chip->lock, flags); =20 return bgpio_dir_return(gc, gpio, false); } =20 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + /* Return 0 if output, 1 if input */ - if (gc->bgpio_dir_unreadable) { - if (gc->bgpio_dir & bgpio_line2mask(gc, gpio)) + if (chip->dir_unreadable) { + if (chip->sdir & bgpio_line2mask(gc, gpio)) return GPIO_LINE_DIRECTION_OUT; return GPIO_LINE_DIRECTION_IN; } =20 - if (gc->reg_dir_out) { - if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio)) + if (chip->reg_dir_out) { + if (chip->read_reg(chip->reg_dir_out) & bgpio_line2mask(gc, gpio)) return GPIO_LINE_DIRECTION_OUT; return GPIO_LINE_DIRECTION_IN; } =20 - if (gc->reg_dir_in) - if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio))) + if (chip->reg_dir_in) + if (!(chip->read_reg(chip->reg_dir_in) & bgpio_line2mask(gc, gpio))) return GPIO_LINE_DIRECTION_OUT; =20 return GPIO_LINE_DIRECTION_IN; @@ -415,18 +436,19 @@ static int bgpio_get_dir(struct gpio_chip *gc, unsign= ed int gpio) =20 static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) { + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); unsigned long flags; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + raw_spin_lock_irqsave(&chip->lock, flags); =20 - gc->bgpio_dir |=3D bgpio_line2mask(gc, gpio); + chip->sdir |=3D bgpio_line2mask(gc, gpio); =20 - if (gc->reg_dir_in) - gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); - if (gc->reg_dir_out) - gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); + if (chip->reg_dir_in) + chip->write_reg(chip->reg_dir_in, ~chip->sdir); + if (chip->reg_dir_out) + chip->write_reg(chip->reg_dir_out, chip->sdir); =20 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + raw_spin_unlock_irqrestore(&chip->lock, flags); } =20 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, @@ -446,31 +468,30 @@ static int bgpio_dir_out_val_first(struct gpio_chip *= gc, unsigned int gpio, } =20 static int bgpio_setup_accessors(struct device *dev, - struct gpio_chip *gc, + struct gpio_generic_chip *chip, bool byte_be) { - - switch (gc->bgpio_bits) { + switch (chip->bits) { case 8: - gc->read_reg =3D bgpio_read8; - gc->write_reg =3D bgpio_write8; + chip->read_reg =3D bgpio_read8; + chip->write_reg =3D bgpio_write8; break; case 16: if (byte_be) { - gc->read_reg =3D bgpio_read16be; - gc->write_reg =3D bgpio_write16be; + chip->read_reg =3D bgpio_read16be; + chip->write_reg =3D bgpio_write16be; } else { - gc->read_reg =3D bgpio_read16; - gc->write_reg =3D bgpio_write16; + chip->read_reg =3D bgpio_read16; + chip->write_reg =3D bgpio_write16; } break; case 32: if (byte_be) { - gc->read_reg =3D bgpio_read32be; - gc->write_reg =3D bgpio_write32be; + chip->read_reg =3D bgpio_read32be; + chip->write_reg =3D bgpio_write32be; } else { - gc->read_reg =3D bgpio_read32; - gc->write_reg =3D bgpio_write32; + chip->read_reg =3D bgpio_read32; + chip->write_reg =3D bgpio_write32; } break; #if BITS_PER_LONG >=3D 64 @@ -480,13 +501,13 @@ static int bgpio_setup_accessors(struct device *dev, "64 bit big endian byte order unsupported\n"); return -EINVAL; } else { - gc->read_reg =3D bgpio_read64; - gc->write_reg =3D bgpio_write64; + chip->read_reg =3D bgpio_read64; + chip->write_reg =3D bgpio_write64; } break; #endif /* BITS_PER_LONG >=3D 64 */ default: - dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits); + dev_err(dev, "unsupported data width %u bits\n", chip->bits); return -EINVAL; } =20 @@ -515,27 +536,25 @@ static int bgpio_setup_accessors(struct device *dev, * - an input direction register (named "dirin") where a 1 bit indicates * the GPIO is an input. */ -static int bgpio_setup_io(struct gpio_chip *gc, - void __iomem *dat, - void __iomem *set, - void __iomem *clr, - unsigned long flags) +static int bgpio_setup_io(struct gpio_generic_chip *chip, + const struct gpio_generic_chip_config *cfg) { + struct gpio_chip *gc =3D &chip->gc; =20 - gc->reg_dat =3D dat; - if (!gc->reg_dat) + chip->reg_dat =3D cfg->dat; + if (!chip->reg_dat) return -EINVAL; =20 - if (set && clr) { - gc->reg_set =3D set; - gc->reg_clr =3D clr; + if (cfg->set && cfg->clr) { + chip->reg_set =3D cfg->set; + chip->reg_clr =3D cfg->clr; gc->set =3D bgpio_set_with_clear; gc->set_multiple =3D bgpio_set_multiple_with_clear; - } else if (set && !clr) { - gc->reg_set =3D set; + } else if (cfg->set && !cfg->clr) { + chip->reg_set =3D cfg->set; gc->set =3D bgpio_set_set; gc->set_multiple =3D bgpio_set_multiple_set; - } else if (flags & BGPIOF_NO_OUTPUT) { + } else if (cfg->flags & BGPIOF_NO_OUTPUT) { gc->set =3D bgpio_set_none; gc->set_multiple =3D NULL; } else { @@ -543,10 +562,10 @@ static int bgpio_setup_io(struct gpio_chip *gc, gc->set_multiple =3D bgpio_set_multiple; } =20 - if (!(flags & BGPIOF_UNREADABLE_REG_SET) && - (flags & BGPIOF_READ_OUTPUT_REG_SET)) { + if (!(cfg->flags & BGPIOF_UNREADABLE_REG_SET) && + (cfg->flags & BGPIOF_READ_OUTPUT_REG_SET)) { gc->get =3D bgpio_get_set; - if (!gc->be_bits) + if (!chip->be_bits) gc->get_multiple =3D bgpio_get_set_multiple; /* * We deliberately avoid assigning the ->get_multiple() call @@ -557,7 +576,7 @@ static int bgpio_setup_io(struct gpio_chip *gc, */ } else { gc->get =3D bgpio_get; - if (gc->be_bits) + if (chip->be_bits) gc->get_multiple =3D bgpio_get_multiple_be; else gc->get_multiple =3D bgpio_get_multiple; @@ -566,27 +585,27 @@ static int bgpio_setup_io(struct gpio_chip *gc, return 0; } =20 -static int bgpio_setup_direction(struct gpio_chip *gc, - void __iomem *dirout, - void __iomem *dirin, - unsigned long flags) +static int bgpio_setup_direction(struct gpio_generic_chip *chip, + const struct gpio_generic_chip_config *cfg) { - if (dirout || dirin) { - gc->reg_dir_out =3D dirout; - gc->reg_dir_in =3D dirin; - if (flags & BGPIOF_NO_SET_ON_INPUT) + struct gpio_chip *gc =3D &chip->gc; + + if (cfg->dirout || cfg->dirin) { + chip->reg_dir_out =3D cfg->dirout; + chip->reg_dir_in =3D cfg->dirin; + if (cfg->flags & BGPIOF_NO_SET_ON_INPUT) gc->direction_output =3D bgpio_dir_out_dir_first; else gc->direction_output =3D bgpio_dir_out_val_first; gc->direction_input =3D bgpio_dir_in; gc->get_direction =3D bgpio_get_dir; } else { - if (flags & BGPIOF_NO_OUTPUT) + if (cfg->flags & BGPIOF_NO_OUTPUT) gc->direction_output =3D bgpio_dir_out_err; else gc->direction_output =3D bgpio_simple_dir_out; =20 - if (flags & BGPIOF_NO_INPUT) + if (cfg->flags & BGPIOF_NO_INPUT) gc->direction_input =3D bgpio_dir_in_err; else gc->direction_input =3D bgpio_simple_dir_in; @@ -595,117 +614,101 @@ static int bgpio_setup_direction(struct gpio_chip *= gc, return 0; } =20 -static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) +static int bgpio_request(struct gpio_chip *gc, unsigned int gpio_pin) { - if (gpio_pin >=3D chip->ngpio) + struct gpio_generic_chip *chip =3D to_gpio_generic_chip(gc); + + if (gpio_pin >=3D gc->ngpio) return -EINVAL; =20 - if (chip->bgpio_pinctrl) - return gpiochip_generic_request(chip, gpio_pin); + if (chip->pinctrl) + return gpiochip_generic_request(gc, gpio_pin); =20 return 0; } =20 /** - * bgpio_init() - Initialize generic GPIO accessor functions - * @gc: the GPIO chip to set up - * @dev: the parent device of the new GPIO chip (compulsory) - * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or= 4 - * @dat: MMIO address for the register to READ the value of the GPIO lines= , it - * is expected that a 1 in the corresponding bit in this register means the - * line is asserted - * @set: MMIO address for the register to SET the value of the GPIO lines,= it is - * expected that we write the line with 1 in this register to drive the GP= IO line - * high. - * @clr: MMIO address for the register to CLEAR the value of the GPIO line= s, it is - * expected that we write the line with 1 in this register to drive the GP= IO line - * low. It is allowed to leave this address as NULL, in that case the SET = register - * will be assumed to also clear the GPIO lines, by actively writing the l= ine - * with 0. - * @dirout: MMIO address for the register to set the line as OUTPUT. It is= assumed - * that setting a line to 1 in this register will turn that line into an - * output line. Conversely, setting the line to 0 will turn that line into - * an input. - * @dirin: MMIO address for the register to set this line as INPUT. It is = assumed - * that setting a line to 1 in this register will turn that line into an - * input line. Conversely, setting the line to 0 will turn that line into - * an output. - * @flags: Different flags that will affect the behaviour of the device, s= uch as - * endianness etc. + * gpio_generic_chip_init() - Initialize a generic GPIO chip. + * @chip: Generic GPIO chip to set up. + * @cfg: Generic GPIO chip configuration. + * + * Returns 0 on success, negative error number on failure. */ -int bgpio_init(struct gpio_chip *gc, struct device *dev, - unsigned long sz, void __iomem *dat, void __iomem *set, - void __iomem *clr, void __iomem *dirout, void __iomem *dirin, - unsigned long flags) +int gpio_generic_chip_init(struct gpio_generic_chip *chip, + const struct gpio_generic_chip_config *cfg) { + struct gpio_chip *gc =3D &chip->gc; + unsigned long flags =3D cfg->flags; + struct device *dev =3D cfg->dev; int ret; =20 - if (!is_power_of_2(sz)) + if (!is_power_of_2(cfg->sz)) return -EINVAL; =20 - gc->bgpio_bits =3D sz * 8; - if (gc->bgpio_bits > BITS_PER_LONG) + chip->bits =3D cfg->sz * 8; + if (chip->bits > BITS_PER_LONG) return -EINVAL; =20 - raw_spin_lock_init(&gc->bgpio_lock); + raw_spin_lock_init(&chip->lock); gc->parent =3D dev; gc->label =3D dev_name(dev); gc->base =3D -1; gc->request =3D bgpio_request; - gc->be_bits =3D !!(flags & BGPIOF_BIG_ENDIAN); + chip->be_bits =3D !!(flags & BGPIOF_BIG_ENDIAN); =20 ret =3D gpiochip_get_ngpios(gc, dev); if (ret) - gc->ngpio =3D gc->bgpio_bits; + gc->ngpio =3D chip->bits; =20 - ret =3D bgpio_setup_io(gc, dat, set, clr, flags); + ret =3D bgpio_setup_io(chip, cfg); if (ret) return ret; =20 - ret =3D bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORD= ER); + ret =3D bgpio_setup_accessors(dev, chip, + flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); if (ret) return ret; =20 - ret =3D bgpio_setup_direction(gc, dirout, dirin, flags); + ret =3D bgpio_setup_direction(chip, cfg); if (ret) return ret; =20 if (flags & BGPIOF_PINCTRL_BACKEND) { - gc->bgpio_pinctrl =3D true; + chip->pinctrl =3D true; /* Currently this callback is only used for pincontrol */ gc->free =3D gpiochip_generic_free; } =20 - gc->bgpio_data =3D gc->read_reg(gc->reg_dat); + chip->sdata =3D chip->read_reg(chip->reg_dat); if (gc->set =3D=3D bgpio_set_set && !(flags & BGPIOF_UNREADABLE_REG_SET)) - gc->bgpio_data =3D gc->read_reg(gc->reg_set); + chip->sdata =3D chip->read_reg(chip->reg_set); =20 if (flags & BGPIOF_UNREADABLE_REG_DIR) - gc->bgpio_dir_unreadable =3D true; + chip->dir_unreadable =3D true; =20 /* * Inspect hardware to find initial direction setting. */ - if ((gc->reg_dir_out || gc->reg_dir_in) && + if ((chip->reg_dir_out || chip->reg_dir_in) && !(flags & BGPIOF_UNREADABLE_REG_DIR)) { - if (gc->reg_dir_out) - gc->bgpio_dir =3D gc->read_reg(gc->reg_dir_out); - else if (gc->reg_dir_in) - gc->bgpio_dir =3D ~gc->read_reg(gc->reg_dir_in); + if (chip->reg_dir_out) + chip->sdir =3D chip->read_reg(chip->reg_dir_out); + else if (chip->reg_dir_in) + chip->sdir =3D ~chip->read_reg(chip->reg_dir_in); /* * If we have two direction registers, synchronise * input setting to output setting, the library * can not handle a line being input and output at * the same time. */ - if (gc->reg_dir_out && gc->reg_dir_in) - gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); + if (chip->reg_dir_out && chip->reg_dir_in) + chip->write_reg(chip->reg_dir_in, ~chip->sdir); } =20 return ret; } -EXPORT_SYMBOL_GPL(bgpio_init); +EXPORT_SYMBOL_GPL(gpio_generic_chip_init); =20 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) =20 diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c index 38643fb813c562957076aab48d804f8048cee5e4..2bb6100840ea27fb63ce7cdc3e1= eb3e43526eb4d 100644 --- a/drivers/gpio/gpio-mpc8xxx.c +++ b/drivers/gpio/gpio-mpc8xxx.c @@ -71,7 +71,7 @@ static int mpc8572_gpio_get(struct gpio_chip *gc, unsigne= d int gpio) mpc8xxx_gc->regs + GPIO_DIR); val =3D gpio_generic_read_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; - out_shadow =3D gc->bgpio_data & out_mask; + out_shadow =3D mpc8xxx_gc->chip.sdata & out_mask; =20 return !!((val | out_shadow) & mpc_pin2mask(gpio)); } @@ -399,7 +399,8 @@ static int mpc8xxx_probe(struct platform_device *pdev) gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); /* Also, latch state of GPIOs configured as output by bootloader. */ - gc->bgpio_data =3D gpio_generic_read_reg(&mpc8xxx_gc->chip, + mpc8xxx_gc->chip.sdata =3D + gpio_generic_read_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_DAT) & gpio_generic_read_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_DIR); diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 9fcd4a988081f74d25dc88535705ba9265e56fd2..9b14fd20f13eee7d465e065e7de= d2c92e2bbc78e 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -388,28 +388,6 @@ struct gpio_irq_chip { * implies that if the chip supports IRQs, these IRQs need to be threaded * as the chip access may sleep when e.g. reading out the IRQ status * registers. - * @read_reg: reader function for generic GPIO - * @write_reg: writer function for generic GPIO - * @be_bits: if the generic GPIO has big endian bit order (bit 31 is repre= senting - * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by t= he - * generic GPIO core. It is for internal housekeeping only. - * @reg_dat: data (in) register for generic GPIO - * @reg_set: output set register (out=3Dhigh) for generic GPIO - * @reg_clr: output clear register (out=3Dlow) for generic GPIO - * @reg_dir_out: direction out setting register for generic GPIO - * @reg_dir_in: direction in setting register for generic GPIO - * @bgpio_dir_unreadable: indicates that the direction register(s) cannot - * be read and we need to rely on out internal state tracking. - * @bgpio_pinctrl: the generic GPIO uses a pin control backend. - * @bgpio_bits: number of register bits used for a generic GPIO i.e. - * * 8 - * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep - * shadowed and real data registers writes together. - * @bgpio_data: shadowed data register for generic GPIO to clear/set bits - * safely. - * @bgpio_dir: shadowed direction register for generic GPIO to clear/set - * direction safely. A "1" in this word means the line is set as - * output. * * A gpio_chip can help platforms abstract various sources of GPIOs so * they can all be accessed through a common programming interface. @@ -475,23 +453,6 @@ struct gpio_chip { const char *const *names; bool can_sleep; =20 -#if IS_ENABLED(CONFIG_GPIO_GENERIC) - unsigned long (*read_reg)(void __iomem *reg); - void (*write_reg)(void __iomem *reg, unsigned long data); - bool be_bits; - void __iomem *reg_dat; - void __iomem *reg_set; - void __iomem *reg_clr; - void __iomem *reg_dir_out; - void __iomem *reg_dir_in; - bool bgpio_dir_unreadable; - bool bgpio_pinctrl; - int bgpio_bits; - raw_spinlock_t bgpio_lock; - unsigned long bgpio_data; - unsigned long bgpio_dir; -#endif /* CONFIG_GPIO_GENERIC */ - #ifdef CONFIG_GPIOLIB_IRQCHIP /* * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib @@ -723,11 +684,6 @@ int gpiochip_populate_parent_fwspec_fourcell(struct gp= io_chip *gc, =20 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ =20 -int bgpio_init(struct gpio_chip *gc, struct device *dev, - unsigned long sz, void __iomem *dat, void __iomem *set, - void __iomem *clr, void __iomem *dirout, void __iomem *dirin, - unsigned long flags); - #define BGPIOF_BIG_ENDIAN BIT(0) #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ diff --git a/include/linux/gpio/generic.h b/include/linux/gpio/generic.h index 4c0626b53ec90388a034bc7797eefa53e7ea064e..162430d96660e96b995eb4a2e64= 183503fc618e3 100644 --- a/include/linux/gpio/generic.h +++ b/include/linux/gpio/generic.h @@ -50,9 +50,44 @@ struct gpio_generic_chip_config { * struct gpio_generic_chip - Generic GPIO chip implementation. * @gc: The underlying struct gpio_chip object, implementing low-level GPIO * chip routines. + * @read_reg: reader function for generic GPIO + * @write_reg: writer function for generic GPIO + * @be_bits: if the generic GPIO has big endian bit order (bit 31 is + * representing line 0, bit 30 is line 1 ... bit 0 is line 31) t= his + * is set to true by the generic GPIO core. It is for internal + * housekeeping only. + * @reg_dat: data (in) register for generic GPIO + * @reg_set: output set register (out=3Dhigh) for generic GPIO + * @reg_clr: output clear register (out=3Dlow) for generic GPIO + * @reg_dir_out: direction out setting register for generic GPIO + * @reg_dir_in: direction in setting register for generic GPIO + * @dir_unreadable: indicates that the direction register(s) cannot be rea= d and + * we need to rely on out internal state tracking. + * @pinctrl: the generic GPIO uses a pin control backend. + * @bits: number of register bits used for a generic GPIO + * i.e. * 8 + * @lock: used to lock chip->sdata. Also, this is needed to keep + * shadowed and real data registers writes together. + * @sdata: shadowed data register for generic GPIO to clear/set bits safel= y. + * @sdir: shadowed direction register for generic GPIO to clear/set direct= ion + * safely. A "1" in this word means the line is set as output. */ struct gpio_generic_chip { struct gpio_chip gc; + unsigned long (*read_reg)(void __iomem *reg); + void (*write_reg)(void __iomem *reg, unsigned long data); + bool be_bits; + void __iomem *reg_dat; + void __iomem *reg_set; + void __iomem *reg_clr; + void __iomem *reg_dir_out; + void __iomem *reg_dir_in; + bool dir_unreadable; + bool pinctrl; + int bits; + raw_spinlock_t lock; + unsigned long sdata; + unsigned long sdir; }; =20 static inline struct gpio_generic_chip * @@ -61,20 +96,8 @@ to_gpio_generic_chip(struct gpio_chip *gc) return container_of(gc, struct gpio_generic_chip, gc); } =20 -/** - * gpio_generic_chip_init() - Initialize a generic GPIO chip. - * @chip: Generic GPIO chip to set up. - * @cfg: Generic GPIO chip configuration. - * - * Returns 0 on success, negative error number on failure. - */ -static inline int -gpio_generic_chip_init(struct gpio_generic_chip *chip, - const struct gpio_generic_chip_config *cfg) -{ - return bgpio_init(&chip->gc, cfg->dev, cfg->sz, cfg->dat, cfg->set, - cfg->clr, cfg->dirout, cfg->dirin, cfg->flags); -} +int gpio_generic_chip_init(struct gpio_generic_chip *chip, + const struct gpio_generic_chip_config *cfg); =20 /** * gpio_generic_chip_set() - Set the GPIO line value of the generic GPIO c= hip. @@ -110,10 +133,10 @@ gpio_generic_chip_set(struct gpio_generic_chip *chip,= unsigned int offset, static inline unsigned long gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg) { - if (WARN_ON(!chip->gc.read_reg)) + if (WARN_ON(!chip->read_reg)) return 0; =20 - return chip->gc.read_reg(reg); + return chip->read_reg(reg); } =20 /** @@ -125,23 +148,23 @@ gpio_generic_read_reg(struct gpio_generic_chip *chip,= void __iomem *reg) static inline void gpio_generic_write_reg(struct gpio_generic_chip *chip, void __iomem *reg, unsigned long val) { - if (WARN_ON(!chip->gc.write_reg)) + if (WARN_ON(!chip->write_reg)) return; =20 - chip->gc.write_reg(reg, val); + chip->write_reg(reg, val); } =20 #define gpio_generic_chip_lock(gen_gc) \ - raw_spin_lock(&(gen_gc)->gc.bgpio_lock) + raw_spin_lock(&(gen_gc)->lock) =20 #define gpio_generic_chip_unlock(gen_gc) \ - raw_spin_unlock(&(gen_gc)->gc.bgpio_lock) + raw_spin_unlock(&(gen_gc)->lock) =20 #define gpio_generic_chip_lock_irqsave(gen_gc, flags) \ - raw_spin_lock_irqsave(&(gen_gc)->gc.bgpio_lock, flags) + raw_spin_lock_irqsave(&(gen_gc)->lock, flags) =20 #define gpio_generic_chip_unlock_irqrestore(gen_gc, flags) \ - raw_spin_unlock_irqrestore(&(gen_gc)->gc.bgpio_lock, flags) + raw_spin_unlock_irqrestore(&(gen_gc)->lock, flags) =20 DEFINE_LOCK_GUARD_1(gpio_generic_lock, struct gpio_generic_chip, --=20 2.48.1