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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL6PEPF0001AB76.mail.protection.outlook.com (10.167.242.169) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9115.13 via Frontend Transport; Tue, 9 Sep 2025 18:58:17 +0000 Received: from titanite-d354host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 9 Sep 2025 11:58:15 -0700 From: Avadhut Naik To: CC: , , , Subject: [PATCH v3 2/5] EDAC/amd64: Remove NUM_CONTROLLERS macro Date: Tue, 9 Sep 2025 18:53:11 +0000 Message-ID: <20250909185748.1621098-3-avadhut.naik@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250909185748.1621098-1-avadhut.naik@amd.com> References: <20250909185748.1621098-1-avadhut.naik@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB76:EE_|DM4PR12MB6400:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b7d09ab-b204-4dd0-b02d-08ddefd2d674 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2025 18:58:17.6189 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b7d09ab-b204-4dd0-b02d-08ddefd2d674 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB76.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6400 Content-Type: text/plain; charset="utf-8" Currently, the NUM_CONTROLLERS macro is only used to statically allocate the csels array of struct chip_select in struct amd64_pvt. The size of this array, however, will never exceed the number of UMCs on the SOC. Since, max_mcs variable in struct amd64_pvt already stores the number of UMCs on the SOC, the macro can be removed and the static array can be dynamically allocated instead. Signed-off-by: Avadhut Naik --- Changes in v3: Patch introduced. --- drivers/edac/amd64_edac.c | 19 +++++++++++++------ drivers/edac/amd64_edac.h | 5 ++--- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 3989794e4f29..0fade110c3fb 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -4000,30 +4000,34 @@ static int probe_one_instance(unsigned int nid) if (ret < 0) goto err_enable; =20 + pvt->csels =3D kcalloc(pvt->max_mcs, sizeof(*pvt->csels), GFP_KERNEL); + if (!pvt->csels) + goto err_enable; + ret =3D pvt->ops->hw_info_get(pvt); if (ret < 0) - goto err_enable; + goto err_csels; =20 ret =3D 0; if (!instance_has_memory(pvt)) { amd64_info("Node %d: No DIMMs detected.\n", nid); - goto err_enable; + goto err_csels; } =20 if (!pvt->ops->ecc_enabled(pvt)) { ret =3D -ENODEV; =20 if (!ecc_enable_override) - goto err_enable; + goto err_csels; =20 if (boot_cpu_data.x86 >=3D 0x17) { amd64_warn("Forcing ECC on is not recommended on newer systems. Please = enable ECC in BIOS."); - goto err_enable; + goto err_csels; } else amd64_warn("Forcing ECC on!\n"); =20 if (!enable_ecc_error_reporting(s, nid, F3)) - goto err_enable; + goto err_csels; } =20 ret =3D init_one_instance(pvt); @@ -4033,7 +4037,7 @@ static int probe_one_instance(unsigned int nid) if (boot_cpu_data.x86 < 0x17) restore_ecc_error_reporting(s, nid, F3); =20 - goto err_enable; + goto err_csels; } =20 amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id); @@ -4043,6 +4047,8 @@ static int probe_one_instance(unsigned int nid) =20 return ret; =20 +err_csels: + kfree(pvt->csels); err_enable: hw_info_put(pvt); kfree(pvt); @@ -4077,6 +4083,7 @@ static void remove_one_instance(unsigned int nid) /* Free the EDAC CORE resources */ mci->pvt_info =3D NULL; =20 + kfree(pvt->csels); hw_info_put(pvt); kfree(pvt); edac_mc_free(mci); diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 56999ed3ae56..39d30255c767 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -96,7 +96,6 @@ /* Hardware limit on ChipSelect rows per MC and processors per system */ #define NUM_CHIPSELECTS 8 #define DRAM_RANGES 8 -#define NUM_CONTROLLERS 12 =20 #define ON true #define OFF false @@ -347,8 +346,8 @@ struct amd64_pvt { u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ =20 - /* one for each DCT/UMC */ - struct chip_select csels[NUM_CONTROLLERS]; + /* Allocate one for each DCT/UMC */ + struct chip_select *csels; =20 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ struct dram_range ranges[DRAM_RANGES]; --=20 2.43.0