From nobody Thu Oct 2 22:52:49 2025 Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3E8B53A7; Tue, 9 Sep 2025 12:09:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.207.19.206 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419786; cv=none; b=pQBc+PbB9EeICOPp27pgGupprh4adoPJvbThFB9KviswY5d59Op3oYnHmmLagC7vaTeDIClq62aeqMN3EYX6n+1S4QwFCOhV9SYWE1MSOy2UGnbpMZb3XgVQbeqYu8lzhFXSLvklL3z3qr6nlT9k15wpkq8kXoEWOwJpPblcQKQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419786; c=relaxed/simple; bh=k6XQcNBhWqijnSk1QCQOdVeQBrDEadMHPOqg4455/Eo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qEufrQyMQ5tAb3UlNHKPNo4Uu+dcxOlc3HO/mhDhdbiz8o9AY1aP0VfrX2iUpuRtqhVdzMAc9S1YEKdhKKnTqnOegsnGd9nNY4m6dQ1MXzIk8SzgHQbTBwoD0kG+k5Uk7YmkGJzQpK/T0ZYPk8P5/Kg/5+JFRS97FNFiZ9NRDv0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mucse.com; spf=pass smtp.mailfrom=mucse.com; arc=none smtp.client-ip=54.207.19.206 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mucse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mucse.com X-QQ-mid: zesmtpsz6t1757419759t426d8ed0 X-QQ-Originating-IP: ndGM1YlHPOJthwTmAep6xTlzzsYoD0ffhUoPf8P37Ho= Received: from localhost.localdomain ( [203.174.112.180]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 09 Sep 2025 20:09:16 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 12613171477653480715 EX-QQ-RecipientCnt: 29 From: Dong Yibo To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, horms@kernel.org, corbet@lwn.net, gur.stavi@huawei.com, maddy@linux.ibm.com, mpe@ellerman.id.au, danishanwar@ti.com, lee@trager.us, gongfan1@huawei.com, lorenzo@kernel.org, geert+renesas@glider.be, Parthiban.Veerasooran@microchip.com, lukas.bulwahn@redhat.com, alexanderduyck@fb.com, richardcochran@gmail.com, kees@kernel.org, gustavoars@kernel.org, rdunlap@infradead.org, vadim.fedorenko@linux.dev Cc: netdev@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, dong100@mucse.com, Andrew Lunn Subject: [PATCH net-next v11 1/5] net: rnpgbe: Add build support for rnpgbe Date: Tue, 9 Sep 2025 20:09:02 +0800 Message-Id: <20250909120906.1781444-2-dong100@mucse.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250909120906.1781444-1-dong100@mucse.com> References: <20250909120906.1781444-1-dong100@mucse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpsz:mucse.com:qybglogicsvrgz:qybglogicsvrgz8a-1 X-QQ-XMAILINFO: M1Ss8/RkJRWgl7Iw/+RKGQmrNYJaYVjzFyP6QCh1JBfpb78iltBqkAjQ T5qdcr1VWiykVaFdud5BYr/PEAxb5LPJQyL0wDAoUhg9R56r3suBDeGI2Ffn7zc6fLZyRKN Ts7C4SHSk8My3nhmTdSHqUjpzqb7JBd5hSN+tGStjzHyJyYg5UlltGf3XsX6VFrnNS0W/+B OiTMYKTrG3KRqyrD8AwJPiCGE3hFYnnWzht8j9ZTNwMTW57hkeAPSZFwRyt6InBeUh4jm+z AS414NO0tCaiW6PjGMsg9ksjgCA+1QZ5oDqqAHY+JXERwKKoedKhBz5p1fHoyZcE/XsrQU2 Dn4nzEsJ9oLyeVnJsP8TlBwxmF/PyxLopSWFAbSa+i3/TdK/bMsOUOgKKC6ud57FwZ5X+Jf HddemVV7HDLetwQmUas9hGTcHiQarH14hVdBcRSZ18+DvxKdwBkfK5uRCh98j++JrITcBLl VWDR3ESValFkCjb19/nUkwGkEDvFFQlSFcQvRHKOw3cHKG+UHcjfiKtgkc8MwWDp1icp3hb FbxlcefWDc12mTI40oBy29ZDaikX/BmjQe5RL4IQ7C/L1ZsOgoxdv/639agnjSO3VbbLekW L284twptzWWGZttMYKSHVcp+N3OGqfMAtYt7HjdUB/x7UHonkaD2ScJ2pYR9drSveO4fvId RVfim/AYZR/SxJHpQBELOUWbEEvaJ5VXTPTuV0H4w1XdQa9mZZmnHViWaO4n/ZN/SD0PP4l t85u7m0Yv89l3jSRGGz471u0narwGJ8qBTW9b2gJQZuJ7bXAwyx84alBdI5ZCNl8BMQ8XqN ffcie66ewoCEPuiwG8OVo/NCRBDzCeEHe+bSDF6Diihwkr0NcAgCi9lILHtx/3QMfQpl8sf COYDEPLjU8bXAYc0zHwr9G1X8edfZrbtt4Dwol/hsA7UFmcfIkrWxY7HCqK+tXRX5VfATAa UI7ruFw4TuVI6ocsYapTqBV7zsPUxidn2pG04hqAVIpZMzQlnTkRbMk04ClizoVOtRAp7RM LiwgEdg3M9Z2C/D5bhvJY0R3T8calg+jKwUy/zkf0hBQCdLaLXd5KNjEloFMyglO3Hwo1KT A== X-QQ-XMRINFO: OWPUhxQsoeAVDbp3OJHYyFg= X-QQ-RECHKSPAM: 0 Content-Type: text/plain; charset="utf-8" Add build options and doc for mucse. Initialize pci device access for MUCSE devices. Signed-off-by: Dong Yibo Reviewed-by: Andrew Lunn Reviewed-by: Vadim Fedorenko --- .../device_drivers/ethernet/index.rst | 1 + .../device_drivers/ethernet/mucse/rnpgbe.rst | 21 +++ MAINTAINERS | 8 ++ drivers/net/ethernet/Kconfig | 1 + drivers/net/ethernet/Makefile | 1 + drivers/net/ethernet/mucse/Kconfig | 34 +++++ drivers/net/ethernet/mucse/Makefile | 7 + drivers/net/ethernet/mucse/rnpgbe/Makefile | 8 ++ drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h | 18 +++ .../net/ethernet/mucse/rnpgbe/rnpgbe_main.c | 124 ++++++++++++++++++ 10 files changed, 223 insertions(+) create mode 100644 Documentation/networking/device_drivers/ethernet/mucse/= rnpgbe.rst create mode 100644 drivers/net/ethernet/mucse/Kconfig create mode 100644 drivers/net/ethernet/mucse/Makefile create mode 100644 drivers/net/ethernet/mucse/rnpgbe/Makefile create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c diff --git a/Documentation/networking/device_drivers/ethernet/index.rst b/D= ocumentation/networking/device_drivers/ethernet/index.rst index 0b0a3eef6aae..41ff2152b7aa 100644 --- a/Documentation/networking/device_drivers/ethernet/index.rst +++ b/Documentation/networking/device_drivers/ethernet/index.rst @@ -47,6 +47,7 @@ Contents: mellanox/mlx5/index meta/fbnic microsoft/netvsc + mucse/rnpgbe neterion/s2io netronome/nfp pensando/ionic diff --git a/Documentation/networking/device_drivers/ethernet/mucse/rnpgbe.= rst b/Documentation/networking/device_drivers/ethernet/mucse/rnpgbe.rst new file mode 100644 index 000000000000..7562fb6b8f61 --- /dev/null +++ b/Documentation/networking/device_drivers/ethernet/mucse/rnpgbe.rst @@ -0,0 +1,21 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Linux Base Driver for MUCSE(R) Gigabit PCI Express Adapters +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +MUCSE Gigabit Linux driver. +Copyright (c) 2020 - 2025 MUCSE Co.,Ltd. + +Identifying Your Adapter +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The driver is compatible with devices based on the following: + + * MUCSE(R) Ethernet Controller N500 series + * MUCSE(R) Ethernet Controller N210 series + +Support +=3D=3D=3D=3D=3D=3D=3D + If you have problems with the software or hardware, please contact our + customer support team via email at techsupport@mucse.com or check our + website at https://www.mucse.com/en/ diff --git a/MAINTAINERS b/MAINTAINERS index b81595e9ea95..39b862347145 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17306,6 +17306,14 @@ T: git git://linuxtv.org/media.git F: Documentation/devicetree/bindings/media/i2c/aptina,mt9v111.yaml F: drivers/media/i2c/mt9v111.c =20 +MUCSE ETHERNET DRIVER +M: Yibo Dong +L: netdev@vger.kernel.org +S: Maintained +W: https://www.mucse.com/en/ +F: Documentation/networking/device_drivers/ethernet/mucse/ +F: drivers/net/ethernet/mucse/ + MULTIFUNCTION DEVICES (MFD) M: Lee Jones S: Maintained diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index f86d4557d8d7..167388f9c744 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -129,6 +129,7 @@ source "drivers/net/ethernet/microchip/Kconfig" source "drivers/net/ethernet/mscc/Kconfig" source "drivers/net/ethernet/microsoft/Kconfig" source "drivers/net/ethernet/moxa/Kconfig" +source "drivers/net/ethernet/mucse/Kconfig" source "drivers/net/ethernet/myricom/Kconfig" =20 config FEALNX diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index 67182339469a..1b8c4df3f594 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_NET_VENDOR_MICREL) +=3D micrel/ obj-$(CONFIG_NET_VENDOR_MICROCHIP) +=3D microchip/ obj-$(CONFIG_NET_VENDOR_MICROSEMI) +=3D mscc/ obj-$(CONFIG_NET_VENDOR_MOXART) +=3D moxa/ +obj-$(CONFIG_NET_VENDOR_MUCSE) +=3D mucse/ obj-$(CONFIG_NET_VENDOR_MYRI) +=3D myricom/ obj-$(CONFIG_FEALNX) +=3D fealnx.o obj-$(CONFIG_NET_VENDOR_NATSEMI) +=3D natsemi/ diff --git a/drivers/net/ethernet/mucse/Kconfig b/drivers/net/ethernet/mucs= e/Kconfig new file mode 100644 index 000000000000..be0fdf268484 --- /dev/null +++ b/drivers/net/ethernet/mucse/Kconfig @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Mucse network device configuration +# + +config NET_VENDOR_MUCSE + bool "Mucse devices" + default y + help + If you have a network (Ethernet) card from Mucse(R), say Y. + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about Mucse(R) cards. If you say Y, you will + be asked for your specific card in the following questions. + +if NET_VENDOR_MUCSE + +config MGBE + tristate "Mucse(R) 1GbE PCI Express adapters support" + depends on PCI + select PAGE_POOL + help + This driver supports Mucse(R) 1GbE PCI Express family of + adapters. + + More specific information on configuring the driver is in + . + + To compile this driver as a module, choose M here. The module + will be called rnpgbe. + +endif # NET_VENDOR_MUCSE + diff --git a/drivers/net/ethernet/mucse/Makefile b/drivers/net/ethernet/muc= se/Makefile new file mode 100644 index 000000000000..675173fa05f7 --- /dev/null +++ b/drivers/net/ethernet/mucse/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright(c) 2020 - 2025 MUCSE Corporation. +# +# Makefile for the MUCSE(R) network device drivers +# + +obj-$(CONFIG_MGBE) +=3D rnpgbe/ diff --git a/drivers/net/ethernet/mucse/rnpgbe/Makefile b/drivers/net/ether= net/mucse/rnpgbe/Makefile new file mode 100644 index 000000000000..9df536f0d04c --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright(c) 2020 - 2025 MUCSE Corporation. +# +# Makefile for the MUCSE(R) 1GbE PCI Express ethernet driver +# + +obj-$(CONFIG_MGBE) +=3D rnpgbe.o +rnpgbe-objs :=3D rnpgbe_main.o diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h b/drivers/net/ether= net/mucse/rnpgbe/rnpgbe.h new file mode 100644 index 000000000000..3c37fe2534a8 --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#ifndef _RNPGBE_H +#define _RNPGBE_H + +enum rnpgbe_boards { + board_n500, + board_n210 +}; + +/* Device IDs */ +#define PCI_VENDOR_ID_MUCSE 0x8848 +#define PCI_DEVICE_ID_N500_QUAD_PORT 0x8308 +#define PCI_DEVICE_ID_N500_DUAL_PORT 0x8318 +#define PCI_DEVICE_ID_N210 0x8208 +#define PCI_DEVICE_ID_N210L 0x820a +#endif /* _RNPGBE_H */ diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c b/drivers/net/= ethernet/mucse/rnpgbe/rnpgbe_main.c new file mode 100644 index 000000000000..60bbc806f17b --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#include + +#include "rnpgbe.h" + +static const char rnpgbe_driver_name[] =3D "rnpgbe"; + +/* rnpgbe_pci_tbl - PCI Device ID Table + * + * { PCI_DEVICE(Vendor ID, Device ID), + * driver_data (used for different hw chip) } + */ +static struct pci_device_id rnpgbe_pci_tbl[] =3D { + { PCI_DEVICE(PCI_VENDOR_ID_MUCSE, PCI_DEVICE_ID_N500_QUAD_PORT), + .driver_data =3D board_n500}, + { PCI_DEVICE(PCI_VENDOR_ID_MUCSE, PCI_DEVICE_ID_N500_DUAL_PORT), + .driver_data =3D board_n500}, + { PCI_DEVICE(PCI_VENDOR_ID_MUCSE, PCI_DEVICE_ID_N210), + .driver_data =3D board_n210}, + { PCI_DEVICE(PCI_VENDOR_ID_MUCSE, PCI_DEVICE_ID_N210L), + .driver_data =3D board_n210}, + /* required last entry */ + {0, }, +}; + +/** + * rnpgbe_probe - Device initialization routine + * @pdev: PCI device information struct + * @id: entry in rnpgbe_pci_tbl + * + * rnpgbe_probe initializes a PF adapter identified by a pci_dev + * structure. + * + * Return: 0 on success, negative errno on failure + **/ +static int rnpgbe_probe(struct pci_dev *pdev, const struct pci_device_id *= id) +{ + int err; + + err =3D pci_enable_device_mem(pdev); + if (err) + return err; + + err =3D dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(56)); + if (err) { + dev_err(&pdev->dev, + "No usable DMA configuration, aborting %d\n", err); + goto err_disable_dev; + } + + err =3D pci_request_mem_regions(pdev, rnpgbe_driver_name); + if (err) { + dev_err(&pdev->dev, + "pci_request_selected_regions failed %d\n", err); + goto err_disable_dev; + } + + pci_set_master(pdev); + err =3D pci_save_state(pdev); + if (err) { + dev_err(&pdev->dev, "pci_save_state failed %d\n", err); + goto err_free_regions; + } + + return 0; +err_free_regions: + pci_release_mem_regions(pdev); +err_disable_dev: + pci_disable_device(pdev); + return err; +} + +/** + * rnpgbe_remove - Device removal routine + * @pdev: PCI device information struct + * + * rnpgbe_remove is called by the PCI subsystem to alert the driver + * that it should release a PCI device. This could be caused by a + * Hot-Plug event, or because the driver is going to be removed from + * memory. + **/ +static void rnpgbe_remove(struct pci_dev *pdev) +{ + pci_release_mem_regions(pdev); + pci_disable_device(pdev); +} + +/** + * rnpgbe_dev_shutdown - Device shutdown routine + * @pdev: PCI device information struct + **/ +static void rnpgbe_dev_shutdown(struct pci_dev *pdev) +{ + pci_disable_device(pdev); +} + +/** + * rnpgbe_shutdown - Device shutdown routine + * @pdev: PCI device information struct + * + * rnpgbe_shutdown is called by the PCI subsystem to alert the driver + * that os shutdown. Device should setup wakeup state here. + **/ +static void rnpgbe_shutdown(struct pci_dev *pdev) +{ + rnpgbe_dev_shutdown(pdev); +} + +static struct pci_driver rnpgbe_driver =3D { + .name =3D rnpgbe_driver_name, + .id_table =3D rnpgbe_pci_tbl, + .probe =3D rnpgbe_probe, + .remove =3D rnpgbe_remove, + .shutdown =3D rnpgbe_shutdown, +}; + +module_pci_driver(rnpgbe_driver); + +MODULE_DEVICE_TABLE(pci, rnpgbe_pci_tbl); +MODULE_AUTHOR("Mucse Corporation, "); +MODULE_DESCRIPTION("Mucse(R) 1 Gigabit PCI Express Network Driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Thu Oct 2 22:52:49 2025 Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47E9D1B78F3; Tue, 9 Sep 2025 12:09:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=52.59.177.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419784; cv=none; b=N3SyXwceo/rkSynFs2m/p7RgliUVjZ9bfR55EfDJTp3fg9Vdfdxr056UoOG5Bbppia5g5bQ0Yub7x8CDMq5ISTBUFGewUhJ95iWOfqOwCxZShwcajLEfxgATL/0ujgWWDOcfVn881yLh+55mUtCAv8jQA6vwSHrBQMCKzaAYT78= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419784; c=relaxed/simple; bh=GaMsjjnsCrxG1jnK6+i13sqfkbQKOcsDVn4n1S6j6uI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VS2AhUH+VyG2AnBKhCGszMgyKaJkIqX9VAZ3MZKqmsI4lVwPw+3P33fXekdCKl2V41E0khwU1Vzfmw1/1/xhKAgmzVmpQVKLhOhcS0544V6HECYj7UT4MbThWRX3euljYkw1JqAjx8MxWBctTrqB20Sz4EBDYqZqfjzLCtD864A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mucse.com; spf=pass smtp.mailfrom=mucse.com; arc=none smtp.client-ip=52.59.177.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mucse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mucse.com X-QQ-mid: zesmtpsz6t1757419764tc459fa02 X-QQ-Originating-IP: +ZpL/WanXej060O0qZvysoRwPVHC5Q6zsOTH/B2nD5E= Received: from localhost.localdomain ( [203.174.112.180]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 09 Sep 2025 20:09:20 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 17648290205751983736 EX-QQ-RecipientCnt: 28 From: Dong Yibo To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, horms@kernel.org, corbet@lwn.net, gur.stavi@huawei.com, maddy@linux.ibm.com, mpe@ellerman.id.au, danishanwar@ti.com, lee@trager.us, gongfan1@huawei.com, lorenzo@kernel.org, geert+renesas@glider.be, Parthiban.Veerasooran@microchip.com, lukas.bulwahn@redhat.com, alexanderduyck@fb.com, richardcochran@gmail.com, kees@kernel.org, gustavoars@kernel.org, rdunlap@infradead.org, vadim.fedorenko@linux.dev Cc: netdev@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, dong100@mucse.com Subject: [PATCH net-next v11 2/5] net: rnpgbe: Add n500/n210 chip support with BAR2 mapping Date: Tue, 9 Sep 2025 20:09:03 +0800 Message-Id: <20250909120906.1781444-3-dong100@mucse.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250909120906.1781444-1-dong100@mucse.com> References: <20250909120906.1781444-1-dong100@mucse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpsz:mucse.com:qybglogicsvrgz:qybglogicsvrgz8a-1 X-QQ-XMAILINFO: MQZ/dZQlO/THfcA9T3Al8bsUPS+kA1cwHW/NRHWo7yMgdY17PT4pm6zE 9H5L3l9ZDyW3qaJ/QFajDStXnEhCwJ6eB7BRU1OhrM/p+M7dh6MdWG5wtua1LdC6WbFzBNp tu4g+GzYzpSqmpLr45M6ydGANSsEN3/xFX9iw1xStb9YbjuK+cee9qiLj0avzPRLtw1YP5l GFNPgRWgYeAPUHZ0jEgFuEMClMOrmoty+RLxb8W58iHq9v6x1IRP0BXqeAZOMYKtVa+fJON NjD6Dg48obb0Y257J0M2nQyomwKCiwNjcksvsEOVwMWRQQQcbPgGYzbXuVdTB/q2k0cJumA P9YpLTdmDUYXBYi/2uHKlPH7NXmUiNIRG5fCqH748OVjKX7n9uqGLhvNKmBMJUhJrst81Up S2rzrS8E4Tbj1D4izViXxwXHeq219I5ysKgJaHDDfzhndcvl57jm2BhkbffkShG2psm95pq JVdTXAs3BZP/b3wp/BK1EzwVIKH6rT1y/yMhG3zp8zlKZb/qZxg8S2M8iU9661JfAx0+EHq pqTswWeG6T93Jlzp9rUxOFDxr7n2I0Iv75vue6Zp2WwnEXgMemFzf+vyJrdI9sTLksJjyjF 4r9Az97XQqJ1sDhr1bxJy7zuX8KgRx6UI5xFz6E44SuW1Ksm3A5Y2WQnGSzezxdIAu+Jt14 /QVfVzfbtR5XNe205PTNlK7NRcLmQmPqLoEBqwQgGS6AtvuonFdtC0Q8XaI/SfMUeKOIsWy WsBqz2An/zwHm4x2BNhOK1NXWvlxiAXNbpWgmKRZU2vDAOQOAV59cl1ansNSVyFPGlCsoBT BUCEbSGKWn36sQ43LEgeNULLXuy05nLp+A+/3+pWqUVBMJC3I0WcEeuTcaROlfxTFfhshwQ td2zosWd35/ZO2IOjc3jEucjvAHqXUsqwMfU0BEjBTUWWrrIpWRRRlr6AJ5+5UVDi347aF2 mHEC5URNOZg2O1GA+BmBjnWZF/yp5J7miuB9co4mVFTiyIy+7IB4fynOl6QmLuBu22EPpFO cwOK2sACh6wHc1FdM5 X-QQ-XMRINFO: M/715EihBoGSf6IYSX1iLFg= X-QQ-RECHKSPAM: 0 Content-Type: text/plain; charset="utf-8" Add hardware initialization foundation for MUCSE 1Gbe controller, including: 1. Map PCI BAR2 as hardware register base; 2. Bind PCI device to driver private data (struct mucse) and initialize hardware context (struct mucse_hw); 3. Reserve board-specific init framework via rnpgbe_init_hw. Signed-off-by: Dong Yibo Reviewed-by: Vadim Fedorenko --- drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h | 10 +++ drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h | 9 +++ .../net/ethernet/mucse/rnpgbe/rnpgbe_main.c | 79 +++++++++++++++++++ 3 files changed, 98 insertions(+) create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h b/drivers/net/ether= net/mucse/rnpgbe/rnpgbe.h index 3c37fe2534a8..3b122dd508ce 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h @@ -9,6 +9,16 @@ enum rnpgbe_boards { board_n210 }; =20 +struct mucse_hw { + void __iomem *hw_addr; +}; + +struct mucse { + struct net_device *netdev; + struct pci_dev *pdev; + struct mucse_hw hw; +}; + /* Device IDs */ #define PCI_VENDOR_ID_MUCSE 0x8848 #define PCI_DEVICE_ID_N500_QUAD_PORT 0x8308 diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h b/drivers/net/et= hernet/mucse/rnpgbe/rnpgbe_hw.h new file mode 100644 index 000000000000..1a0b22d651b9 --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#ifndef _RNPGBE_HW_H +#define _RNPGBE_HW_H + +/**************** CHIP Resource ****************************/ +#define RNPGBE_MAX_QUEUES 8 +#endif /* _RNPGBE_HW_H */ diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c b/drivers/net/= ethernet/mucse/rnpgbe/rnpgbe_main.c index 60bbc806f17b..0afe39621661 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c @@ -2,8 +2,11 @@ /* Copyright(c) 2020 - 2025 Mucse Corporation. */ =20 #include +#include +#include =20 #include "rnpgbe.h" +#include "rnpgbe_hw.h" =20 static const char rnpgbe_driver_name[] =3D "rnpgbe"; =20 @@ -25,6 +28,54 @@ static struct pci_device_id rnpgbe_pci_tbl[] =3D { {0, }, }; =20 +/** + * rnpgbe_add_adapter - Add netdev for this pci_dev + * @pdev: PCI device information structure + * @board_type: board type + * + * rnpgbe_add_adapter initializes a netdev for this pci_dev + * structure. Initializes Bar map, private structure, and a + * hardware reset occur. + * + * Return: 0 on success, negative errno on failure + **/ +static int rnpgbe_add_adapter(struct pci_dev *pdev, + int board_type) +{ + struct net_device *netdev; + void __iomem *hw_addr; + struct mucse *mucse; + struct mucse_hw *hw; + int err; + + netdev =3D alloc_etherdev_mq(sizeof(struct mucse), RNPGBE_MAX_QUEUES); + if (!netdev) + return -ENOMEM; + + SET_NETDEV_DEV(netdev, &pdev->dev); + mucse =3D netdev_priv(netdev); + mucse->netdev =3D netdev; + mucse->pdev =3D pdev; + pci_set_drvdata(pdev, mucse); + + hw =3D &mucse->hw; + hw_addr =3D devm_ioremap(&pdev->dev, + pci_resource_start(pdev, 2), + pci_resource_len(pdev, 2)); + if (!hw_addr) { + err =3D -EIO; + goto err_free_net; + } + + hw->hw_addr =3D hw_addr; + + return 0; + +err_free_net: + free_netdev(netdev); + return err; +} + /** * rnpgbe_probe - Device initialization routine * @pdev: PCI device information struct @@ -37,6 +88,7 @@ static struct pci_device_id rnpgbe_pci_tbl[] =3D { **/ static int rnpgbe_probe(struct pci_dev *pdev, const struct pci_device_id *= id) { + int board_type =3D id->driver_data; int err; =20 err =3D pci_enable_device_mem(pdev); @@ -63,6 +115,9 @@ static int rnpgbe_probe(struct pci_dev *pdev, const stru= ct pci_device_id *id) dev_err(&pdev->dev, "pci_save_state failed %d\n", err); goto err_free_regions; } + err =3D rnpgbe_add_adapter(pdev, board_type); + if (err) + goto err_free_regions; =20 return 0; err_free_regions: @@ -72,6 +127,23 @@ static int rnpgbe_probe(struct pci_dev *pdev, const str= uct pci_device_id *id) return err; } =20 +/** + * rnpgbe_rm_adapter - Remove netdev for this mucse structure + * @pdev: PCI device information struct + * + * rnpgbe_rm_adapter remove a netdev for this mucse structure + **/ +static void rnpgbe_rm_adapter(struct pci_dev *pdev) +{ + struct mucse *mucse =3D pci_get_drvdata(pdev); + struct net_device *netdev; + + if (!mucse) + return; + netdev =3D mucse->netdev; + free_netdev(netdev); +} + /** * rnpgbe_remove - Device removal routine * @pdev: PCI device information struct @@ -83,6 +155,7 @@ static int rnpgbe_probe(struct pci_dev *pdev, const stru= ct pci_device_id *id) **/ static void rnpgbe_remove(struct pci_dev *pdev) { + rnpgbe_rm_adapter(pdev); pci_release_mem_regions(pdev); pci_disable_device(pdev); } @@ -93,6 +166,12 @@ static void rnpgbe_remove(struct pci_dev *pdev) **/ static void rnpgbe_dev_shutdown(struct pci_dev *pdev) { + struct mucse *mucse =3D pci_get_drvdata(pdev); + struct net_device *netdev =3D mucse->netdev; + + rtnl_lock(); + netif_device_detach(netdev); + rtnl_unlock(); pci_disable_device(pdev); } =20 --=20 2.25.1 From nobody Thu Oct 2 22:52:49 2025 Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51ADB32BF55; Tue, 9 Sep 2025 12:09:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.254.200.128 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419788; cv=none; b=Q4aM88RbWAdUPKNu7SJ+3KMZSdwdHU4wDTx6Kn+shDrAP/9GDtWdeSObUxG4d6U5C9Xdw3G57OLXqEPA/sIyMrcwnW/B8bV3lnkDMCvJ7LX5oSZCxWxCVRGutePkEpVO0PiYcag8OV3768RQIAb4rWau7p85QbdQ6TRIISkk9a0= ARC-Message-Signature: i=1; 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charset="utf-8" Add fundamental mailbox (MBX) communication operations between PF (Physical Function) and firmware for n500/n210 chips Signed-off-by: Dong Yibo --- drivers/net/ethernet/mucse/rnpgbe/Makefile | 4 +- drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h | 25 ++ .../net/ethernet/mucse/rnpgbe/rnpgbe_chip.c | 70 +++ drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h | 7 + .../net/ethernet/mucse/rnpgbe/rnpgbe_main.c | 5 + .../net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c | 425 ++++++++++++++++++ .../net/ethernet/mucse/rnpgbe/rnpgbe_mbx.h | 20 + 7 files changed, 555 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.h diff --git a/drivers/net/ethernet/mucse/rnpgbe/Makefile b/drivers/net/ether= net/mucse/rnpgbe/Makefile index 9df536f0d04c..5fc878ada4b1 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/Makefile +++ b/drivers/net/ethernet/mucse/rnpgbe/Makefile @@ -5,4 +5,6 @@ # =20 obj-$(CONFIG_MGBE) +=3D rnpgbe.o -rnpgbe-objs :=3D rnpgbe_main.o +rnpgbe-objs :=3D rnpgbe_main.o\ + rnpgbe_chip.o\ + rnpgbe_mbx.o diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h b/drivers/net/ether= net/mucse/rnpgbe/rnpgbe.h index 3b122dd508ce..ac28502a8860 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h @@ -4,13 +4,36 @@ #ifndef _RNPGBE_H #define _RNPGBE_H =20 +#include + enum rnpgbe_boards { board_n500, board_n210 }; =20 +struct mucse_mbx_stats { + u32 msgs_tx; /* Number of messages sent from PF to fw */ + u32 msgs_rx; /* Number of messages received from fw to PF */ + u32 acks; /* Number of ACKs received from firmware */ + u32 reqs; /* Number of requests sent to firmware */ +}; + +struct mucse_mbx_info { + struct mucse_mbx_stats stats; + u32 timeout_cnt; + u32 usec_delay; + u16 fw_req; + u16 fw_ack; + /* fw <--> pf mbx */ + u32 fwpf_shm_base; + u32 pf2fw_mbx_ctrl; + u32 fwpf_mbx_mask; + u32 fwpf_ctrl_base; +}; + struct mucse_hw { void __iomem *hw_addr; + struct mucse_mbx_info mbx; }; =20 struct mucse { @@ -19,6 +42,8 @@ struct mucse { struct mucse_hw hw; }; =20 +int rnpgbe_init_hw(struct mucse_hw *hw, int board_type); + /* Device IDs */ #define PCI_VENDOR_ID_MUCSE 0x8848 #define PCI_DEVICE_ID_N500_QUAD_PORT 0x8308 diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c b/drivers/net/= ethernet/mucse/rnpgbe/rnpgbe_chip.c new file mode 100644 index 000000000000..0e277e7557ee --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#include + +#include "rnpgbe.h" +#include "rnpgbe_hw.h" +#include "rnpgbe_mbx.h" + +/** + * rnpgbe_init_n500 - Setup n500 hw info + * @hw: hw information structure + * + * rnpgbe_init_n500 initializes all private + * structure for n500 + **/ +static void rnpgbe_init_n500(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + + mbx->fwpf_ctrl_base =3D MUCSE_N500_FWPF_CTRL_BASE; + mbx->fwpf_shm_base =3D MUCSE_N500_FWPF_SHM_BASE; +} + +/** + * rnpgbe_init_n210 - Setup n210 hw info + * @hw: hw information structure + * + * rnpgbe_init_n210 initializes all private + * structure for n210 + **/ +static void rnpgbe_init_n210(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + + mbx->fwpf_ctrl_base =3D MUCSE_N210_FWPF_CTRL_BASE; + mbx->fwpf_shm_base =3D MUCSE_N210_FWPF_SHM_BASE; +} + +/** + * rnpgbe_init_hw - Setup hw info according to board_type + * @hw: hw information structure + * @board_type: board type + * + * rnpgbe_init_hw initializes all hw data + * + * Return: 0 on success, negative errno on failure + **/ +int rnpgbe_init_hw(struct mucse_hw *hw, int board_type) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + + mbx->pf2fw_mbx_ctrl =3D MUCSE_GBE_PFFW_MBX_CTRL_OFFSET; + mbx->fwpf_mbx_mask =3D MUCSE_GBE_FWPF_MBX_MASK_OFFSET; + + switch (board_type) { + case board_n500: + rnpgbe_init_n500(hw); + break; + case board_n210: + rnpgbe_init_n210(hw); + break; + default: + return -EINVAL; + } + /* init_params with mbx base */ + mucse_init_mbx_params_pf(hw); + + return 0; +} diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h b/drivers/net/et= hernet/mucse/rnpgbe/rnpgbe_hw.h index 1a0b22d651b9..612f0ba65265 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h @@ -4,6 +4,13 @@ #ifndef _RNPGBE_HW_H #define _RNPGBE_HW_H =20 +/**************** MBX Resource ****************************/ +#define MUCSE_N500_FWPF_CTRL_BASE 0x28b00 +#define MUCSE_N500_FWPF_SHM_BASE 0x2d000 +#define MUCSE_GBE_PFFW_MBX_CTRL_OFFSET 0x5500 +#define MUCSE_GBE_FWPF_MBX_MASK_OFFSET 0x5700 +#define MUCSE_N210_FWPF_CTRL_BASE 0x29400 +#define MUCSE_N210_FWPF_SHM_BASE 0x2d900 /**************** CHIP Resource ****************************/ #define RNPGBE_MAX_QUEUES 8 #endif /* _RNPGBE_HW_H */ diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c b/drivers/net/= ethernet/mucse/rnpgbe/rnpgbe_main.c index 0afe39621661..c6cfb54f7c59 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c @@ -68,6 +68,11 @@ static int rnpgbe_add_adapter(struct pci_dev *pdev, } =20 hw->hw_addr =3D hw_addr; + err =3D rnpgbe_init_hw(hw, board_type); + if (err) { + dev_err(&pdev->dev, "Init hw err %d\n", err); + goto err_free_net; + } =20 return 0; =20 diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c b/drivers/net/e= thernet/mucse/rnpgbe/rnpgbe_mbx.c new file mode 100644 index 000000000000..9fcafda1bc5b --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2022 - 2025 Mucse Corporation. */ + +#include +#include +#include + +#include "rnpgbe_mbx.h" + +/** + * mbx_data_rd32 - Reads reg with base mbx->fwpf_shm_base + * @mbx: pointer to the MBX structure + * @reg: register offset + * + * Return: register value + **/ +static u32 mbx_data_rd32(struct mucse_mbx_info *mbx, u32 reg) +{ + struct mucse_hw *hw =3D container_of(mbx, struct mucse_hw, mbx); + + return readl(hw->hw_addr + mbx->fwpf_shm_base + reg); +} + +/** + * mbx_data_wr32 - Writes value to reg with base mbx->fwpf_shm_base + * @mbx: pointer to the MBX structure + * @reg: register offset + * @value: value to be written + * + **/ +static void mbx_data_wr32(struct mucse_mbx_info *mbx, u32 reg, u32 value) +{ + struct mucse_hw *hw =3D container_of(mbx, struct mucse_hw, mbx); + + writel(value, hw->hw_addr + mbx->fwpf_shm_base + reg); +} + +/** + * mbx_ctrl_rd32 - Reads reg with base mbx->fwpf_ctrl_base + * @mbx: pointer to the MBX structure + * @reg: register offset + * + * Return: register value + **/ +static u32 mbx_ctrl_rd32(struct mucse_mbx_info *mbx, u32 reg) +{ + struct mucse_hw *hw =3D container_of(mbx, struct mucse_hw, mbx); + + return readl(hw->hw_addr + mbx->fwpf_ctrl_base + reg); +} + +/** + * mbx_ctrl_wr32 - Writes value to reg with base mbx->fwpf_ctrl_base + * @mbx: pointer to the MBX structure + * @reg: register offset + * @value: value to be written + * + **/ +static void mbx_ctrl_wr32(struct mucse_mbx_info *mbx, u32 reg, u32 value) +{ + struct mucse_hw *hw =3D container_of(mbx, struct mucse_hw, mbx); + + writel(value, hw->hw_addr + mbx->fwpf_ctrl_base + reg); +} + +/** + * mucse_mbx_get_lock_pf - Write ctrl and read back lock status + * @hw: pointer to the HW structure + * + * Return: register value after write + **/ +static u32 mucse_mbx_get_lock_pf(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + u32 reg =3D MUCSE_MBX_PF2FW_CTRL(mbx); + + mbx_ctrl_wr32(mbx, reg, MUCSE_MBX_PFU); + + return mbx_ctrl_rd32(mbx, reg); +} + +/** + * mucse_obtain_mbx_lock_pf - Obtain mailbox lock + * @hw: pointer to the HW structure + * + * Pair with mucse_release_mbx_lock_pf() + * This function maybe used in an irq handler. + * + * Return: 0 on success, negative errno on failure + **/ +static int mucse_obtain_mbx_lock_pf(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + int count =3D mbx->timeout_cnt; + u32 val; + + return read_poll_timeout_atomic(mucse_mbx_get_lock_pf, + val, val & MUCSE_MBX_PFU, + mbx->usec_delay, + count * mbx->usec_delay, + false, hw); +} + +/** + * mucse_release_mbx_lock_pf - Release mailbox lock + * @hw: pointer to the HW structure + * @req: send a request or not + * + * Pair with mucse_obtain_mbx_lock_pf(): + * - Releases the mailbox lock by clearing MUCSE_MBX_PFU bit + * - Simultaneously sends the request by setting MUCSE_MBX_REQ bit + * if req is true + * (Both bits are in the same mailbox control register, + * so operations are combined) + **/ +static void mucse_release_mbx_lock_pf(struct mucse_hw *hw, bool req) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + u32 reg =3D MUCSE_MBX_PF2FW_CTRL(mbx); + + if (req) + mbx_ctrl_wr32(mbx, reg, MUCSE_MBX_REQ); + else + mbx_ctrl_wr32(mbx, reg, 0); +} + +/** + * mucse_mbx_get_fwreq - Read fw req from reg + * @mbx: pointer to the mbx structure + * + * Return: the fwreq value + **/ +static u16 mucse_mbx_get_fwreq(struct mucse_mbx_info *mbx) +{ + u32 val =3D mbx_data_rd32(mbx, MUCSE_MBX_FW2PF_CNT); + + return FIELD_GET(GENMASK_U32(15, 0), val); +} + +/** + * mucse_mbx_inc_pf_ack - Increase ack + * @hw: pointer to the HW structure + * + * mucse_mbx_inc_pf_ack read pf_ack from hw, then write + * new value back after increase + **/ +static void mucse_mbx_inc_pf_ack(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + u16 ack; + u32 val; + + val =3D mbx_data_rd32(mbx, MUCSE_MBX_PF2FW_CNT); + ack =3D FIELD_GET(GENMASK_U32(31, 16), val); + ack++; + val &=3D ~GENMASK_U32(31, 16); + val |=3D FIELD_PREP(GENMASK_U32(31, 16), ack); + mbx_data_wr32(mbx, MUCSE_MBX_PF2FW_CNT, val); + hw->mbx.stats.msgs_rx++; +} + +/** + * mucse_read_mbx_pf - Read a message from the mailbox + * @hw: pointer to the HW structure + * @msg: the message buffer + * @size: length of buffer + * + * This function copies a message from the mailbox buffer to the caller's + * memory buffer. The presumption is that the caller knows that there was + * a message due to a fw request so no polling for message is needed. + * + * Return: 0 on success, negative errno on failure + **/ +static int mucse_read_mbx_pf(struct mucse_hw *hw, u32 *msg, u16 size) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + int size_in_words =3D size / 4; + int ret; + int i; + + ret =3D mucse_obtain_mbx_lock_pf(hw); + if (ret) + return ret; + + for (i =3D 0; i < size_in_words; i++) + msg[i] =3D mbx_data_rd32(mbx, MUCSE_MBX_FWPF_SHM + 4 * i); + /* Hw needs write data_reg at last */ + mbx_data_wr32(mbx, MUCSE_MBX_FWPF_SHM, 0); + /* flush reqs as we have read this request data */ + hw->mbx.fw_req =3D mucse_mbx_get_fwreq(mbx); + mucse_mbx_inc_pf_ack(hw); + mucse_release_mbx_lock_pf(hw, false); + + return 0; +} + +/** + * mucse_check_for_msg_pf - Check to see if the fw has sent mail + * @hw: pointer to the HW structure + * + * Return: 0 if the fw has set the Status bit or else -EIO + **/ +static int mucse_check_for_msg_pf(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + u16 fw_req; + + fw_req =3D mucse_mbx_get_fwreq(mbx); + /* chip's register is reset to 0 when rc send reset + * mbx command. This causes 'fw_req !=3D hw->mbx.fw_req' + * be TRUE before fw really reply. Driver must wait fw reset + * done reply before using chip, we must check no-zero. + **/ + if (fw_req !=3D 0 && fw_req !=3D hw->mbx.fw_req) { + hw->mbx.stats.reqs++; + return 0; + } + + return -EIO; +} + +/** + * mucse_poll_for_msg - Wait for message notification + * @hw: pointer to the HW structure + * + * Return: 0 on success, negative errno on failure + **/ +static int mucse_poll_for_msg(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + int count =3D mbx->timeout_cnt; + int val; + + return read_poll_timeout(mucse_check_for_msg_pf, + val, !val, mbx->usec_delay, + count * mbx->usec_delay, + false, hw); +} + +/** + * mucse_poll_and_read_mbx - Wait for message notification and receive mes= sage + * @hw: pointer to the HW structure + * @msg: the message buffer + * @size: length of buffer + * + * Return: 0 if it successfully received a message notification and + * copied it into the receive buffer + **/ +int mucse_poll_and_read_mbx(struct mucse_hw *hw, u32 *msg, u16 size) +{ + int ret; + + ret =3D mucse_poll_for_msg(hw); + if (ret) + return ret; + + return mucse_read_mbx_pf(hw, msg, size); +} + +/** + * mucse_mbx_get_fwack - Read fw ack from reg + * @mbx: pointer to the MBX structure + * + * Return: the fwack value + **/ +static u16 mucse_mbx_get_fwack(struct mucse_mbx_info *mbx) +{ + u32 val =3D mbx_data_rd32(mbx, MUCSE_MBX_FW2PF_CNT); + + return FIELD_GET(GENMASK_U32(31, 16), val); +} + +/** + * mucse_mbx_inc_pf_req - Increase req + * @hw: pointer to the HW structure + * + * mucse_mbx_inc_pf_req read pf_req from hw, then write + * new value back after increase + **/ +static void mucse_mbx_inc_pf_req(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + u16 req; + u32 val; + + val =3D mbx_data_rd32(mbx, MUCSE_MBX_PF2FW_CNT); + req =3D FIELD_GET(GENMASK_U32(15, 0), val); + req++; + val &=3D ~GENMASK_U32(15, 0); + val |=3D FIELD_PREP(GENMASK_U32(15, 0), req); + mbx_data_wr32(mbx, MUCSE_MBX_PF2FW_CNT, val); + hw->mbx.stats.msgs_tx++; +} + +/** + * mucse_write_mbx_pf - Place a message in the mailbox + * @hw: pointer to the HW structure + * @msg: the message buffer + * @size: length of buffer + * + * This function maybe used in an irq handler. + * + * Return: 0 if it successfully copied message into the buffer + **/ +static int mucse_write_mbx_pf(struct mucse_hw *hw, u32 *msg, u16 size) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + int size_in_words =3D size / 4; + int ret; + int i; + + ret =3D mucse_obtain_mbx_lock_pf(hw); + if (ret) + return ret; + + for (i =3D 0; i < size_in_words; i++) + mbx_data_wr32(mbx, MUCSE_MBX_FWPF_SHM + i * 4, msg[i]); + + /* flush acks as we are overwriting the message buffer */ + hw->mbx.fw_ack =3D mucse_mbx_get_fwack(mbx); + mucse_mbx_inc_pf_req(hw); + mucse_release_mbx_lock_pf(hw, true); + + return 0; +} + +/** + * mucse_check_for_ack_pf - Check to see if the fw has ACKed + * @hw: pointer to the HW structure + * + * Return: 0 if the fw has set the Status bit or else -EIO + **/ +static int mucse_check_for_ack_pf(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + u16 fw_ack; + + fw_ack =3D mucse_mbx_get_fwack(mbx); + /* chip's register is reset to 0 when rc send reset + * mbx command. This causes 'fw_ack !=3D hw->mbx.fw_ack' + * be TRUE before fw really reply. Driver must wait fw reset + * done reply before using chip, we must check no-zero. + **/ + if (fw_ack !=3D 0 && fw_ack !=3D hw->mbx.fw_ack) { + hw->mbx.stats.acks++; + return 0; + } + + return -EIO; +} + +/** + * mucse_poll_for_ack - Wait for message acknowledgment + * @hw: pointer to the HW structure + * + * Return: 0 if it successfully received a message acknowledgment, + * else negative errno + **/ +static int mucse_poll_for_ack(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + int count =3D mbx->timeout_cnt; + int val; + + return read_poll_timeout(mucse_check_for_ack_pf, + val, !val, mbx->usec_delay, + count * mbx->usec_delay, + false, hw); +} + +/** + * mucse_write_and_wait_ack_mbx - Write a message to the mailbox, wait for= ack + * @hw: pointer to the HW structure + * @msg: the message buffer + * @size: length of buffer + * + * Return: 0 if it successfully copied message into the buffer and + * received an ack to that message within delay * timeout_cnt period + **/ +int mucse_write_and_wait_ack_mbx(struct mucse_hw *hw, u32 *msg, u16 size) +{ + int ret; + + ret =3D mucse_write_mbx_pf(hw, msg, size); + if (ret) + return ret; + return mucse_poll_for_ack(hw); +} + +/** + * mucse_mbx_reset - Reset mbx info, sync info from regs + * @hw: pointer to the HW structure + * + * This function reset all mbx variables to default. + **/ +static void mucse_mbx_reset(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + u32 v; + + v =3D mbx_data_rd32(mbx, MUCSE_MBX_FW2PF_CNT); + hw->mbx.fw_req =3D FIELD_GET(GENMASK_U32(15, 0), v); + hw->mbx.fw_ack =3D FIELD_GET(GENMASK_U32(31, 16), v); + mbx_ctrl_wr32(mbx, MUCSE_MBX_PF2FW_CTRL(mbx), 0); + mbx_ctrl_wr32(mbx, MUCSE_MBX_FWPF_MASK(mbx), GENMASK_U32(31, 16)); +} + +/** + * mucse_init_mbx_params_pf - Set initial values for pf mailbox + * @hw: pointer to the HW structure + * + * Initializes the hw->mbx struct to correct values for pf mailbox + */ +void mucse_init_mbx_params_pf(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + + mbx->usec_delay =3D 100; + mbx->timeout_cnt =3D (4 * USEC_PER_SEC) / mbx->usec_delay; + mbx->stats.msgs_tx =3D 0; + mbx->stats.msgs_rx =3D 0; + mbx->stats.reqs =3D 0; + mbx->stats.acks =3D 0; + mucse_mbx_reset(hw); +} diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.h b/drivers/net/e= thernet/mucse/rnpgbe/rnpgbe_mbx.h new file mode 100644 index 000000000000..eac99f13b6ff --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#ifndef _RNPGBE_MBX_H +#define _RNPGBE_MBX_H + +#include "rnpgbe.h" + +#define MUCSE_MBX_FW2PF_CNT 0 +#define MUCSE_MBX_PF2FW_CNT 4 +#define MUCSE_MBX_FWPF_SHM 8 +#define MUCSE_MBX_PF2FW_CTRL(mbx) ((mbx)->pf2fw_mbx_ctrl) +#define MUCSE_MBX_FWPF_MASK(mbx) ((mbx)->fwpf_mbx_mask) +#define MUCSE_MBX_REQ BIT(0) /* Request a req to mailbox */ +#define MUCSE_MBX_PFU BIT(3) /* PF owns the mailbox buffer */ + +int mucse_write_and_wait_ack_mbx(struct mucse_hw *hw, u32 *msg, u16 size); +void mucse_init_mbx_params_pf(struct mucse_hw *hw); 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charset="utf-8" Add fundamental firmware (FW) communication operations via PF-FW mailbox, including: - FW sync (via HW info query with retries) - HW reset (post FW command to reset hardware) - MAC address retrieval (request FW for port-specific MAC) - Power management (powerup/powerdown notification to FW) Signed-off-by: Dong Yibo --- drivers/net/ethernet/mucse/rnpgbe/Makefile | 3 +- drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h | 4 + .../net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c | 1 + .../net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.c | 249 ++++++++++++++++++ .../net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.h | 121 +++++++++ 5 files changed, 377 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.c create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.h diff --git a/drivers/net/ethernet/mucse/rnpgbe/Makefile b/drivers/net/ether= net/mucse/rnpgbe/Makefile index 5fc878ada4b1..de8bcb7772ab 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/Makefile +++ b/drivers/net/ethernet/mucse/rnpgbe/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_MGBE) +=3D rnpgbe.o rnpgbe-objs :=3D rnpgbe_main.o\ rnpgbe_chip.o\ - rnpgbe_mbx.o + rnpgbe_mbx.o\ + rnpgbe_mbx_fw.o diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h b/drivers/net/ether= net/mucse/rnpgbe/rnpgbe.h index ac28502a8860..3a1ad82c24bd 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h @@ -5,6 +5,7 @@ #define _RNPGBE_H =20 #include +#include =20 enum rnpgbe_boards { board_n500, @@ -24,6 +25,8 @@ struct mucse_mbx_info { u32 usec_delay; u16 fw_req; u16 fw_ack; + /* lock for only one use mbx */ + struct mutex lock; /* fw <--> pf mbx */ u32 fwpf_shm_base; u32 pf2fw_mbx_ctrl; @@ -34,6 +37,7 @@ struct mucse_mbx_info { struct mucse_hw { void __iomem *hw_addr; struct mucse_mbx_info mbx; + u8 pfvfnum; }; =20 struct mucse { diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c b/drivers/net/e= thernet/mucse/rnpgbe/rnpgbe_mbx.c index 9fcafda1bc5b..6ff3655033de 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c @@ -421,5 +421,6 @@ void mucse_init_mbx_params_pf(struct mucse_hw *hw) mbx->stats.msgs_rx =3D 0; mbx->stats.reqs =3D 0; mbx->stats.acks =3D 0; + mutex_init(&mbx->lock); mucse_mbx_reset(hw); } diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.c b/drivers/ne= t/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.c new file mode 100644 index 000000000000..9b81ee679622 --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.c @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#include +#include + +#include "rnpgbe.h" +#include "rnpgbe_mbx.h" +#include "rnpgbe_mbx_fw.h" + +/** + * mucse_fw_send_cmd_wait_resp - Send cmd req and wait for response + * @hw: pointer to the HW structure + * @req: pointer to the cmd req structure + * @reply: pointer to the fw reply structure + * + * mucse_fw_send_cmd_wait_resp sends req to pf-fw mailbox and wait + * reply from fw. + * + * Return: 0 on success, negative errno on failure + **/ +static int mucse_fw_send_cmd_wait_resp(struct mucse_hw *hw, + struct mbx_fw_cmd_req *req, + struct mbx_fw_cmd_reply *reply) +{ + int len =3D le16_to_cpu(req->datalen); + int retry_cnt =3D 3; + int err; + + mutex_lock(&hw->mbx.lock); + err =3D mucse_write_and_wait_ack_mbx(hw, (u32 *)req, len); + if (err) + goto out; + do { + err =3D mucse_poll_and_read_mbx(hw, (u32 *)reply, + sizeof(*reply)); + if (err) + goto out; + /* mucse_write_and_wait_ack_mbx return 0 means fw has + * received request, wait for the expect opcode + * reply with 'retry_cnt' times. + */ + } while (--retry_cnt >=3D 0 && reply->opcode !=3D req->opcode); +out: + mutex_unlock(&hw->mbx.lock); + if (!err && retry_cnt < 0) + return -ETIMEDOUT; + if (!err && reply->error_code) + return -EIO; + + return err; +} + +/** + * build_get_hw_info_req - build req with GET_HW_INFO opcode + * @req: pointer to the cmd req structure + **/ +static void build_get_hw_info_req(struct mbx_fw_cmd_req *req) +{ + req->flags =3D 0; + req->opcode =3D cpu_to_le16(GET_HW_INFO); + req->datalen =3D cpu_to_le16(MUCSE_MBX_REQ_HDR_LEN); + req->reply_lo =3D 0; + req->reply_hi =3D 0; +} + +/** + * mucse_mbx_get_info - Get hw info from fw + * @hw: pointer to the HW structure + * + * mucse_mbx_get_info tries to get hw info from hw. + * + * Return: 0 on success, negative errno on failure + **/ +static int mucse_mbx_get_info(struct mucse_hw *hw) +{ + struct mbx_fw_cmd_reply reply =3D {}; + struct mbx_fw_cmd_req req =3D {}; + struct mucse_hw_info info =3D {}; + int err; + + build_get_hw_info_req(&req); + + err =3D mucse_fw_send_cmd_wait_resp(hw, &req, &reply); + if (!err) { + memcpy(&info, &reply.hw_info, sizeof(struct mucse_hw_info)); + mucse_hw_info_update_host_endian(&info); + hw->pfvfnum =3D FIELD_GET(GENMASK_U16(7, 0), + le16_to_cpu(info.pfnum)); + } + + return err; +} + +/** + * mucse_mbx_sync_fw - Try to sync with fw + * @hw: pointer to the HW structure + * + * mucse_mbx_sync_fw tries to sync with fw. It is only called in + * probe. Nothing (register network) todo if failed. + * Try more times to do sync. + * + * Return: 0 on success, negative errno on failure + **/ +int mucse_mbx_sync_fw(struct mucse_hw *hw) +{ + int try_cnt =3D 3; + int err; + + do { + err =3D mucse_mbx_get_info(hw); + if (err =3D=3D -ETIMEDOUT) + continue; + break; + } while (try_cnt--); + + return err; +} + +/** + * build_powerup - build req with powerup opcode + * @req: pointer to the cmd req structure + * @is_powerup: true for powerup, false for powerdown + **/ +static void build_powerup(struct mbx_fw_cmd_req *req, + bool is_powerup) +{ + req->flags =3D 0; + req->opcode =3D cpu_to_le16(POWER_UP); + req->datalen =3D cpu_to_le16(sizeof(req->powerup) + + MUCSE_MBX_REQ_HDR_LEN); + req->reply_lo =3D 0; + req->reply_hi =3D 0; + /* fw needs this to reply correct cmd */ + req->powerup.version =3D cpu_to_le32(GENMASK_U32(31, 0)); + if (is_powerup) + req->powerup.status =3D cpu_to_le32(1); + else + req->powerup.status =3D cpu_to_le32(0); +} + +/** + * mucse_mbx_powerup - Echo fw to powerup + * @hw: pointer to the HW structure + * @is_powerup: true for powerup, false for powerdown + * + * mucse_mbx_powerup echo fw to change working frequency + * to normal after received true, and reduce working frequency + * if false. + * + * Return: 0 on success, negative errno on failure + **/ +int mucse_mbx_powerup(struct mucse_hw *hw, bool is_powerup) +{ + struct mbx_fw_cmd_req req =3D {}; + int len; + int err; + + build_powerup(&req, is_powerup); + len =3D le16_to_cpu(req.datalen); + mutex_lock(&hw->mbx.lock); + err =3D mucse_write_and_wait_ack_mbx(hw, (u32 *)&req, len); + mutex_unlock(&hw->mbx.lock); + + return err; +} + +/** + * build_reset_hw_req - build req with RESET_HW opcode + * @req: pointer to the cmd req structure + **/ +static void build_reset_hw_req(struct mbx_fw_cmd_req *req) +{ + req->flags =3D 0; + req->opcode =3D cpu_to_le16(RESET_HW); + req->datalen =3D cpu_to_le16(MUCSE_MBX_REQ_HDR_LEN); + req->reply_lo =3D 0; + req->reply_hi =3D 0; +} + +/** + * mucse_mbx_reset_hw - Posts a mbx req to reset hw + * @hw: pointer to the HW structure + * + * mucse_mbx_reset_hw posts a mbx req to firmware to reset hw. + * We use mucse_fw_send_cmd_wait_resp to wait hw reset ok. + * + * Return: 0 on success, negative errno on failure + **/ +int mucse_mbx_reset_hw(struct mucse_hw *hw) +{ + struct mbx_fw_cmd_reply reply =3D {}; + struct mbx_fw_cmd_req req =3D {}; + + build_reset_hw_req(&req); + + return mucse_fw_send_cmd_wait_resp(hw, &req, &reply); +} + +/** + * build_get_macaddress_req - build req with get_mac opcode + * @req: pointer to the cmd req structure + * @port_mask: port valid for this cmd + * @pfvfnum: pfvfnum for this cmd + **/ +static void build_get_macaddress_req(struct mbx_fw_cmd_req *req, + int port_mask, int pfvfnum) +{ + req->flags =3D 0; + req->opcode =3D cpu_to_le16(GET_MAC_ADDRESS); + req->datalen =3D cpu_to_le16(sizeof(req->get_mac_addr) + + MUCSE_MBX_REQ_HDR_LEN); + req->reply_lo =3D 0; + req->reply_hi =3D 0; + req->get_mac_addr.port_mask =3D cpu_to_le32(port_mask); + req->get_mac_addr.pfvf_num =3D cpu_to_le32(pfvfnum); +} + +/** + * mucse_mbx_get_macaddr - Posts a mbx req to request macaddr + * @hw: pointer to the HW structure + * @pfvfnum: index of pf/vf num + * @mac_addr: pointer to store mac_addr + * @port: port index + * + * mucse_mbx_get_macaddr posts a mbx req to firmware to get mac_addr. + * + * Return: 0 on success, negative errno on failure + **/ +int mucse_mbx_get_macaddr(struct mucse_hw *hw, int pfvfnum, + u8 *mac_addr, + int port) +{ + struct mbx_fw_cmd_reply reply =3D {}; + struct mbx_fw_cmd_req req =3D {}; + int err; + + build_get_macaddress_req(&req, BIT(port), pfvfnum); + err =3D mucse_fw_send_cmd_wait_resp(hw, &req, &reply); + if (err) + return err; + + if (le32_to_cpu(reply.mac_addr.ports) & BIT(port)) + memcpy(mac_addr, reply.mac_addr.addrs[port].mac, ETH_ALEN); + else + return -ENODATA; + + return 0; +} diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.h b/drivers/ne= t/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.h new file mode 100644 index 000000000000..9dee6029e630 --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#ifndef _RNPGBE_MBX_FW_H +#define _RNPGBE_MBX_FW_H + +#include + +#include "rnpgbe.h" + +#define MUCSE_MBX_REQ_HDR_LEN 24 + +enum MUCSE_FW_CMD { + GET_HW_INFO =3D 0x0601, + GET_MAC_ADDRESS =3D 0x0602, + RESET_HW =3D 0x0603, + POWER_UP =3D 0x0803, +}; + +struct mucse_hw_info { + u8 link_stat; + u8 port_mask; + __le32 speed; + __le16 phy_type; + __le16 nic_mode; + __le16 pfnum; + __le32 fw_version; + __le32 axi_mhz; + union { + u8 port_id[4]; + __le32 port_ids; + }; + __le32 bd_uid; + __le32 phy_id; + __le32 wol_status; + union { + __le32 ext_info; + struct { + u32 valid : 1; + u32 wol_en : 1; + u32 pci_preset_runtime_en : 1; + u32 smbus_en : 1; + u32 ncsi_en : 1; + u32 rpu_en : 1; + u32 v2 : 1; + u32 pxe_en : 1; + u32 mctp_en : 1; + u32 yt8614 : 1; + u32 pci_ext_reset : 1; + u32 rpu_availble : 1; + u32 fw_lldp_ability : 1; + u32 lldp_enabled : 1; + u32 only_1g : 1; + u32 force_down_en: 1; + } e_host; + }; +} __packed; + +/* FW stores extended information in 'ext_info' as a 32-bit + * little-endian value. To make these flags easily accessible in the + * kernel (via named 'bitfields' instead of raw bitmask operations), + * we use the union's 'e_host' struct, which provides named bits + * (e.g., 'wol_en', 'smbus_en') + */ +static inline void mucse_hw_info_update_host_endian(struct mucse_hw_info *= info) +{ + u32 host_val =3D le32_to_cpu(info->ext_info); + + memcpy(&info->e_host, &host_val, sizeof(info->e_host)); +} + +struct mbx_fw_cmd_req { + __le16 flags; + __le16 opcode; + __le16 datalen; + __le16 ret_value; + __le32 cookie_lo; + __le32 cookie_hi; + __le32 reply_lo; + __le32 reply_hi; + union { + u8 data[32]; + struct { + __le32 version; + __le32 status; + } powerup; + struct { + __le32 port_mask; + __le32 pfvf_num; + } get_mac_addr; + }; +} __packed; + +struct mbx_fw_cmd_reply { + __le16 flags; + __le16 opcode; + __le16 error_code; + __le16 datalen; + __le32 cookie_lo; + __le32 cookie_hi; + union { + u8 data[40]; + struct mac_addr { + __le32 ports; + struct _addr { + /* for macaddr:01:02:03:04:05:06 + * mac-hi=3D0x01020304 mac-lo=3D0x05060000 + */ + u8 mac[8]; + } addrs[4]; + } mac_addr; + struct mucse_hw_info hw_info; + }; +} __packed; + +int mucse_mbx_sync_fw(struct mucse_hw *hw); +int mucse_mbx_powerup(struct mucse_hw *hw, bool is_powerup); +int mucse_mbx_reset_hw(struct mucse_hw *hw); +int mucse_mbx_get_macaddr(struct mucse_hw *hw, int pfvfnum, + u8 *mac_addr, int port); +#endif /* _RNPGBE_MBX_FW_H */ --=20 2.25.1 From nobody Thu Oct 2 22:52:49 2025 Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDF74334704; Tue, 9 Sep 2025 12:09:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.207.22.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419803; cv=none; b=EbBD4TpU04+NwMAWb1IMtdj8y4nukbguuMMr58HsTL/SaYAqY0vGqPehGIsRTg/vTSsJcRj/vTE5+k9fsJMU1fhaV/oT5rg/YrdORMpvk+NjLmk7dcM9f3wLgolZgOjigSZoPtZ9chn3PiZMCFvLRzE3NJkMo6IVi5Y3Iy9PJaE= ARC-Message-Signature: i=1; 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charset="utf-8" Complete the network device (netdev) registration flow for Mucse Gbe Ethernet chips, including: 1. Hardware state initialization: - Send powerup notification to firmware (via echo_fw_status) - Sync with firmware - Reset hardware 2. MAC address handling: - Retrieve permanent MAC from firmware (via mucse_mbx_get_macaddr) - Fallback to random valid MAC (eth_random_addr) if not valid mac from Fw Signed-off-by: Dong Yibo --- drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h | 25 +++++ .../net/ethernet/mucse/rnpgbe/rnpgbe_chip.c | 85 +++++++++++++++ drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h | 2 + .../net/ethernet/mucse/rnpgbe/rnpgbe_main.c | 102 ++++++++++++++++++ 4 files changed, 214 insertions(+) diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h b/drivers/net/ether= net/mucse/rnpgbe/rnpgbe.h index 3a1ad82c24bd..5278cb1d421e 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h @@ -6,12 +6,17 @@ =20 #include #include +#include =20 enum rnpgbe_boards { board_n500, board_n210 }; =20 +struct mucse_dma_info { + void __iomem *dma_base_addr; +}; + struct mucse_mbx_stats { u32 msgs_tx; /* Number of messages sent from PF to fw */ u32 msgs_rx; /* Number of messages received from fw to PF */ @@ -34,9 +39,26 @@ struct mucse_mbx_info { u32 fwpf_ctrl_base; }; =20 +struct mucse_hw; + +struct mucse_hw_operations { + int (*reset_hw)(struct mucse_hw *hw); + int (*get_perm_mac)(struct mucse_hw *hw); + int (*mbx_send_notify)(struct mucse_hw *hw, bool enable, int mode); +}; + +enum { + mucse_fw_powerup, +}; + struct mucse_hw { void __iomem *hw_addr; + struct pci_dev *pdev; + const struct mucse_hw_operations *ops; + struct mucse_dma_info dma; struct mucse_mbx_info mbx; + int port; + u8 perm_addr[ETH_ALEN]; u8 pfvfnum; }; =20 @@ -54,4 +76,7 @@ int rnpgbe_init_hw(struct mucse_hw *hw, int board_type); #define PCI_DEVICE_ID_N500_DUAL_PORT 0x8318 #define PCI_DEVICE_ID_N210 0x8208 #define PCI_DEVICE_ID_N210L 0x820a + +#define rnpgbe_dma_wr32(dma, reg, val) \ + writel((val), (dma)->dma_base_addr + (reg)) #endif /* _RNPGBE_H */ diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c b/drivers/net/= ethernet/mucse/rnpgbe/rnpgbe_chip.c index 0e277e7557ee..436fb03f9736 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c @@ -1,11 +1,90 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright(c) 2020 - 2025 Mucse Corporation. */ =20 +#include #include +#include =20 #include "rnpgbe.h" #include "rnpgbe_hw.h" #include "rnpgbe_mbx.h" +#include "rnpgbe_mbx_fw.h" + +/** + * rnpgbe_get_permanent_mac - Get permanent mac + * @hw: hw information structure + * + * rnpgbe_get_permanent_mac tries to get mac from hw + * + * Return: 0 on success, negative errno on failure + **/ +static int rnpgbe_get_permanent_mac(struct mucse_hw *hw) +{ + struct device *dev =3D &hw->pdev->dev; + u8 *mac_addr =3D hw->perm_addr; + int err; + + err =3D mucse_mbx_get_macaddr(hw, hw->pfvfnum, mac_addr, hw->port); + if (err) { + dev_err(dev, "Failed to get MAC from FW %d\n", err); + return err; + } + + if (!is_valid_ether_addr(mac_addr)) { + dev_err(dev, "Failed to get valid MAC from FW\n"); + return -EINVAL; + } + + return 0; +} + +/** + * rnpgbe_reset - Do a hardware reset + * @hw: hw information structure + * + * rnpgbe_reset calls fw to do a hardware + * reset, and cleans some regs to default. + * + * Return: 0 on success, negative errno on failure + **/ +static int rnpgbe_reset(struct mucse_hw *hw) +{ + struct mucse_dma_info *dma =3D &hw->dma; + + rnpgbe_dma_wr32(dma, RNPGBE_DMA_AXI_EN, 0); + return mucse_mbx_reset_hw(hw); +} + +/** + * rnpgbe_mbx_send_notify - Echo fw status + * @hw: hw information structure + * @enable: true or false status + * @mode: status mode + * + * Return: 0 on success, negative errno on failure + **/ +static int rnpgbe_mbx_send_notify(struct mucse_hw *hw, + bool enable, + int mode) +{ + int err; + + switch (mode) { + case mucse_fw_powerup: + err =3D mucse_mbx_powerup(hw, enable); + break; + default: + err =3D -EINVAL; + } + + return err; +} + +static const struct mucse_hw_operations rnpgbe_hw_ops =3D { + .reset_hw =3D rnpgbe_reset, + .get_perm_mac =3D rnpgbe_get_permanent_mac, + .mbx_send_notify =3D rnpgbe_mbx_send_notify, +}; =20 /** * rnpgbe_init_n500 - Setup n500 hw info @@ -48,8 +127,14 @@ static void rnpgbe_init_n210(struct mucse_hw *hw) **/ int rnpgbe_init_hw(struct mucse_hw *hw, int board_type) { + struct mucse_dma_info *dma =3D &hw->dma; struct mucse_mbx_info *mbx =3D &hw->mbx; =20 + hw->ops =3D &rnpgbe_hw_ops; + hw->port =3D 0; + + dma->dma_base_addr =3D hw->hw_addr; + mbx->pf2fw_mbx_ctrl =3D MUCSE_GBE_PFFW_MBX_CTRL_OFFSET; mbx->fwpf_mbx_mask =3D MUCSE_GBE_FWPF_MBX_MASK_OFFSET; =20 diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h b/drivers/net/et= hernet/mucse/rnpgbe/rnpgbe_hw.h index 612f0ba65265..00bf7571bf35 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h @@ -11,6 +11,8 @@ #define MUCSE_GBE_FWPF_MBX_MASK_OFFSET 0x5700 #define MUCSE_N210_FWPF_CTRL_BASE 0x29400 #define MUCSE_N210_FWPF_SHM_BASE 0x2d900 +/**************** DMA Registers ****************************/ +#define RNPGBE_DMA_AXI_EN 0x0010 /**************** CHIP Resource ****************************/ #define RNPGBE_MAX_QUEUES 8 #endif /* _RNPGBE_HW_H */ diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c b/drivers/net/= ethernet/mucse/rnpgbe/rnpgbe_main.c index c6cfb54f7c59..94de1693c4a0 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c @@ -7,6 +7,7 @@ =20 #include "rnpgbe.h" #include "rnpgbe_hw.h" +#include "rnpgbe_mbx_fw.h" =20 static const char rnpgbe_driver_name[] =3D "rnpgbe"; =20 @@ -28,6 +29,55 @@ static struct pci_device_id rnpgbe_pci_tbl[] =3D { {0, }, }; =20 +/** + * rnpgbe_open - Called when a network interface is made active + * @netdev: network interface device structure + * + * The open entry point is called when a network interface is made + * active by the system (IFF_UP). + * + * Return: 0 on success, negative value on failure + **/ +static int rnpgbe_open(struct net_device *netdev) +{ + return 0; +} + +/** + * rnpgbe_close - Disables a network interface + * @netdev: network interface device structure + * + * The close entry point is called when an interface is de-activated + * by the OS. + * + * Return: 0, this is not allowed to fail + **/ +static int rnpgbe_close(struct net_device *netdev) +{ + return 0; +} + +/** + * rnpgbe_xmit_frame - Send a skb to driver + * @skb: skb structure to be sent + * @netdev: network interface device structure + * + * Return: NETDEV_TX_OK or NETDEV_TX_BUSY + **/ +static netdev_tx_t rnpgbe_xmit_frame(struct sk_buff *skb, + struct net_device *netdev) +{ + dev_kfree_skb_any(skb); + netdev->stats.tx_dropped++; + return NETDEV_TX_OK; +} + +static const struct net_device_ops rnpgbe_netdev_ops =3D { + .ndo_open =3D rnpgbe_open, + .ndo_stop =3D rnpgbe_close, + .ndo_start_xmit =3D rnpgbe_xmit_frame, +}; + /** * rnpgbe_add_adapter - Add netdev for this pci_dev * @pdev: PCI device information structure @@ -68,11 +118,55 @@ static int rnpgbe_add_adapter(struct pci_dev *pdev, } =20 hw->hw_addr =3D hw_addr; + hw->pdev =3D pdev; + err =3D rnpgbe_init_hw(hw, board_type); if (err) { dev_err(&pdev->dev, "Init hw err %d\n", err); goto err_free_net; } + /* Step 1: Send power-up notification to firmware (no response expected) + * This informs firmware to initialize hardware power state, but + * firmware only acknowledges receipt without returning data. Must be + * done before synchronization as firmware may be in low-power idle + * state initially. + */ + err =3D hw->ops->mbx_send_notify(hw, true, mucse_fw_powerup); + if (err) { + dev_warn(&pdev->dev, "Send powerup to hw failed %d\n", err); + dev_warn(&pdev->dev, "Maybe low performance\n"); + } + /* Step 2: Synchronize mailbox communication with firmware (requires + * response) After power-up, confirm firmware is ready to process + * requests with responses. This ensures subsequent request/response + * interactions work reliably. + */ + err =3D mucse_mbx_sync_fw(hw); + if (err) { + dev_err(&pdev->dev, "Sync fw failed! %d\n", err); + goto err_free_net; + } + + netdev->netdev_ops =3D &rnpgbe_netdev_ops; + err =3D hw->ops->reset_hw(hw); + if (err) { + dev_err(&pdev->dev, "Hw reset failed %d\n", err); + goto err_free_net; + } + + err =3D hw->ops->get_perm_mac(hw); + if (err =3D=3D -EINVAL) { + dev_warn(&pdev->dev, "Using random MAC\n"); + eth_random_addr(hw->perm_addr); + } else if (err) { + dev_err(&pdev->dev, "get perm_addr failed %d\n", err); + goto err_free_net; + } + + eth_hw_addr_set(netdev, hw->perm_addr); + err =3D register_netdev(netdev); + if (err) + goto err_free_net; =20 return 0; =20 @@ -141,11 +235,17 @@ static int rnpgbe_probe(struct pci_dev *pdev, const s= truct pci_device_id *id) static void rnpgbe_rm_adapter(struct pci_dev *pdev) { struct mucse *mucse =3D pci_get_drvdata(pdev); + struct mucse_hw *hw =3D &mucse->hw; struct net_device *netdev; + int err; =20 if (!mucse) return; netdev =3D mucse->netdev; + unregister_netdev(netdev); + err =3D hw->ops->mbx_send_notify(hw, false, mucse_fw_powerup); + if (err) + dev_warn(&pdev->dev, "Send powerdown to hw failed %d\n", err); free_netdev(netdev); } =20 @@ -176,6 +276,8 @@ static void rnpgbe_dev_shutdown(struct pci_dev *pdev) =20 rtnl_lock(); netif_device_detach(netdev); + if (netif_running(netdev)) + rnpgbe_close(netdev); rtnl_unlock(); pci_disable_device(pdev); } --=20 2.25.1