From nobody Thu Oct 2 23:48:26 2025 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5ED1C32CF71; Tue, 9 Sep 2025 12:01:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419286; cv=none; b=jkiv+crjb56VlZsZB+81u5Si6zFYGA9BVw9UNo3zgszT6Sd/EpVtyTQS08yDi6zNLxvsBLl3GVOHr3/rtvVv78EWWa6P3lHrFOFJb+0/HjujD7kaEjFvJEzKLnHRYreZMyI2leV6EFftUpM4RxOTwGwqXwC2XQKtUrHS7VVV/Is= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419286; c=relaxed/simple; bh=VXqAsTkP8pRNA71qjFKnccY+EqssJbde5MQbankgew4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k8ByRv9Fzr+TC5FmtaReY+pAqVyiGKgQhmghZRPH950H1G3fbqHh3QemJmpSHBHn2cO5/YtSTiZlErWQLUYv7HEakaL533gqWDAoIYLTvBor8epjYMQznK+k0Lk9W2HozFvzhWKpygib13dcOuvG2sqtoZuaYEUw022kQFOInZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=hfFrLIXp; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="hfFrLIXp" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id A48FA1A0E15; Tue, 9 Sep 2025 12:01:21 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 7E10060630; Tue, 9 Sep 2025 12:01:21 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C5E1C102F2907; Tue, 9 Sep 2025 14:01:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1757419280; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=HsW0cZ9EbLnOGTHwvUhelG9CYt2QpPeJTLFnCHhucUw=; b=hfFrLIXpmInQRb6tKJhpsNWnBf3Gxt1lxkNdTgdMRCFVP80rkh4URwmCiPkgM8hXNOA1nm WD7aeR7AFfHIybdTcNUIa1LWzcasmbVYx9t2/S2VRIxS3O7QqMu6wxTBZQmjwUZXW6+vwL FnEBZ+PTpUnd/MvHqSdm5oYKPcMCd0IfWkiXG8YJraepA2nhRb98xT29phtgcxKaFWFZfs DQ6E4eD4kFbJQAIqLejLldS2FVnPQrC3NIcY9YdTrFpAI9wsCQZGHHJS0yPIW5wWu+Dl0H fDv9bul/ArVfMAS1P1IfoXN10en4W45pxICuoLY0g2vEOAfQMA56TWSI2BZoNQ== From: "Herve Codina (Schneider Electric)" To: Wolfram Sang , Hoan Tran , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Saravana Kannan , Serge Semin , Herve Codina Cc: Phil Edworthy , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni Subject: [PATCH v2 1/8] ARM: dts: r9a06g032: Add GPIO controllers Date: Tue, 9 Sep 2025 14:00:32 +0200 Message-ID: <20250909120041.154459-2-herve.codina@bootlin.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250909120041.154459-1-herve.codina@bootlin.com> References: <20250909120041.154459-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add GPIO controllers (Synosys DesignWare IPs) available in the r9a06g032 (RZ/N1D) SoC. Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 121 +++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 13a60656b044..da977cdd8487 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -499,6 +499,127 @@ gic: interrupt-controller@44101000 { ; }; =20 + /* + * The GPIO mapping to the corresponding pins is not obvious. + * See the hardware documentation for details. + */ + gpio0: gpio@5000b000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x5000b000 0x80>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&sysctrl R9A06G032_HCLK_GPIO0>; + clock-names =3D "bus"; + status =3D "disabled"; + + /* GPIO0a[0] connected to pin GPIO0 */ + /* GPIO0a[1..2] connected to pins GPIO3..4 */ + /* GPIO0a[3..4] connected to pins GPIO9..10 */ + /* GPIO0a[5] connected to pin GPIO12 */ + /* GPIO0a[6..7] connected to pins GPIO15..16 */ + /* GPIO0a[8..9] connected to pins GPIO21..22 */ + /* GPIO0a[10] connected to pin GPIO24 */ + /* GPIO0a[11..12] connected to pins GPIO27..28 */ + /* GPIO0a[13..14] connected to pins GPIO33..34 */ + /* GPIO0a[15] connected to pin GPIO36 */ + /* GPIO0a[16..17] connected to pins GPIO39..40 */ + /* GPIO0a[18..19] connected to pins GPIO45..46 */ + /* GPIO0a[20] connected to pin GPIO48 */ + /* GPIO0a[21..22] connected to pins GPIO51..52 */ + /* GPIO0a[23..24] connected to pins GPIO57..58 */ + /* GPIO0a[25..31] connected to pins GPIO62..68 */ + gpio0a: gpio-port@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <32>; + reg =3D <0>; + }; + + /* GPIO0b[0..1] connected to pins GPIO1..2 */ + /* GPIO0b[2..5] connected to pins GPIO5..8 */ + /* GPIO0b[6] connected to pin GPIO11 */ + /* GPIO0b[7..8] connected to pins GPIO13..14 */ + /* GPIO0b[9..12] connected to pins GPIO17..20 */ + /* GPIO0b[13] connected to pin GPIO23 */ + /* GPIO0b[14..15] connected to pins GPIO25..26 */ + /* GPIO0b[16..19] connected to pins GPIO29..32 */ + /* GPIO0b[20] connected to pin GPIO35 */ + /* GPIO0b[21..22] connected to pins GPIO37..38 */ + /* GPIO0b[23..26] connected to pins GPIO41..44 */ + /* GPIO0b[27] connected to pin GPIO47 */ + /* GPIO0b[28..29] connected to pins GPIO49..50 */ + /* GPIO0b[30..31] connected to pins GPIO53..54 */ + gpio0b: gpio-port@1 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <32>; + reg =3D <1>; + }; + }; + + gpio1: gpio@5000c000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x5000c000 0x80>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&sysctrl R9A06G032_HCLK_GPIO1>; + clock-names =3D "bus"; + status =3D "disabled"; + + /* GPIO1a[0..4] connected to pins GPIO69..73 */ + /* GPIO1a[5..31] connected to pins GPIO95..121 */ + gpio1a: gpio-port@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <32>; + reg =3D <0>; + }; + + /* GPIO1b[0..1] connected to pins GPIO55..56 */ + /* GPIO1b[2..4] connected to pins GPIO59..61 */ + /* GPIO1b[5..25] connected to pins GPIO74..94 */ + /* GPIO1b[26..31] connected to pins GPIO150..155 */ + gpio1b: gpio-port@1 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <32>; + reg =3D <1>; + }; + }; + + gpio2: gpio@5000d000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x5000d000 0x80>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&sysctrl R9A06G032_HCLK_GPIO2>; + clock-names =3D "bus"; + status =3D "disabled"; + + /* GPIO2a[0..27] connected to pins GPIO122..149 */ + /* GPIO2a[28..31] connected to pins GPIO156..159 */ + gpio2a: gpio-port@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <32>; + reg =3D <0>; + }; + + /* GPIO2b[0..9] connected to pins GPIO160..169 */ + gpio2b: gpio-port@1 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <10>; + reg =3D <1>; + }; + }; + can0: can@52104000 { compatible =3D "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; reg =3D <0x52104000 0x800>; --=20 2.51.0 From nobody Thu Oct 2 23:48:26 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B14A432BF35; Tue, 9 Sep 2025 12:01:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; 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charset="utf-8" On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines. The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines. Signed-off-by: Herve Codina (Schneider Electric) --- .../soc/renesas/renesas,rzn1-gpioirqmux.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r= zn1-gpioirqmux.yaml diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpi= oirqmux.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-g= pioirqmux.yaml new file mode 100644 index 000000000000..4a5aad8b2c44 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux= .yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,rzn1-gpioirqmux.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 SoCs GPIO Interrupt Multiplexer + +description: | + The Renesas RZ/N1 GPIO Interrupt Multiplexer multiplexes GPIO interrupt + lines to the interrupt controller available in the SoC. + + It selects up to 8 of the 96 GPIO interrupt lines available and connect= them + to 8 output interrupt lines. + +maintainers: + - Herve Codina + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-gpioirqmux + - const: renesas,rzn1-gpioirqmux + + reg: + maxItems: 1 + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: + items: + - const: 0x7f + + interrupt-map: + description: + Specifies the mapping from external GPIO interrupt lines to the outp= ut + interrupts. The array items have to be ordered with the first item + related to the output line 0 (IRQ 103), the next one to the output l= ine 1 + (IRQ 104) and so on up to the output line 8 (IRQ 110). + +required: + - compatible + - reg + - "#address-cells" + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +additionalProperties: false + +examples: + - | + #include + + gic: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + interrupt-controller@51000480 { + compatible =3D "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioi= rqmux"; + reg =3D <0x51000480 0x20>; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x7f>; + /* + * The child interrupt number is computed using the following form= ula: + * gpio_bank * 32 + gpio_number + * + * with: + * - gpio_bank: The GPIO bank number + * - 0 for GPIO0A, + * - 1 for GPIO1A, + * - 2 for GPIO2A + * - gpio_number: Number of the gpio in the bank (0..31) + */ + interrupt-map =3D + <32 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1A.0 */ + <89 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* GPIO2A.25 */ + <9 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 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charset="utf-8" for_each_of_imap_item is an iterator designed to help a driver to parse an interrupt-map property. Indeed some drivers need to know details about the interrupt mapping described in the device-tree in order to set internal registers accordingly. Signed-off-by: Herve Codina (Schneider Electric) --- drivers/of/irq.c | 70 ++++++++++++++++++++++++++++++++++++++++++ include/linux/of_irq.h | 41 ++++++++++++++++++++++++- 2 files changed, 110 insertions(+), 1 deletion(-) diff --git a/drivers/of/irq.c b/drivers/of/irq.c index 74aaea61de13..0723ae4153a0 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -157,6 +157,76 @@ const __be32 *of_irq_parse_imap_parent(const __be32 *i= map, int len, struct of_ph return imap; } =20 +int of_imap_parser_init(struct of_imap_parser *parser, struct device_node = *node, + struct of_imap_item *item) +{ + int imaplen; + u32 tmp; + int ret; + + /* + * parent_offset is the offset where the parent part is starting. + * In other words, the offset where the parent interrupt controller + * phandle is present. + * + * Compute this offset (child #interrupt-cells + child #address-cells) + */ + parser->parent_offset =3D of_bus_n_addr_cells(node); + + ret =3D of_property_read_u32(node, "#interrupt-cells", &tmp); + if (ret) + return ret; + + parser->parent_offset +=3D tmp; + + if (WARN(parser->parent_offset > ARRAY_SIZE(item->child_imap), + "child part size =3D %u, cannot fit in array of %zu items", + parser->parent_offset, ARRAY_SIZE(item->child_imap))) + return -EINVAL; + + parser->imap =3D of_get_property(node, "interrupt-map", &imaplen); + if (!parser->imap) + return -ENOENT; + + imaplen /=3D sizeof(*parser->imap); + parser->imap_end =3D parser->imap + imaplen; + + memset(item, 0, sizeof(*item)); + item->child_imap_count =3D parser->parent_offset; + + return 0; +} +EXPORT_SYMBOL_GPL(of_imap_parser_init); + +struct of_imap_item *of_imap_parser_one(struct of_imap_parser *parser, + struct of_imap_item *item) +{ + const __be32 *imap_parent, *imap_next; + int i; + + /* Release previously get parent node */ + of_node_put(item->parent_args.np); + + if (parser->imap + parser->parent_offset + 1 >=3D parser->imap_end) + return NULL; + + imap_parent =3D parser->imap + parser->parent_offset; + + imap_next =3D of_irq_parse_imap_parent(imap_parent, + parser->imap_end - imap_parent, + &item->parent_args); + if (!imap_next) + return NULL; + + for (i =3D 0; i < parser->parent_offset; i++) + item->child_imap[i] =3D be32_to_cpu(*(parser->imap + i)); + + parser->imap =3D imap_next; + + return item; +} +EXPORT_SYMBOL_GPL(of_imap_parser_one); + /** * of_irq_parse_raw - Low level interrupt tree parsing * @addr: address specifier (start of "reg" property of the device) in be3= 2 format diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h index a480063c9cb1..f42757b245c4 100644 --- a/include/linux/of_irq.h +++ b/include/linux/of_irq.h @@ -11,6 +11,30 @@ =20 typedef int (*of_irq_init_cb_t)(struct device_node *, struct device_node *= ); =20 +struct of_imap_parser { + struct device_node *node; + const __be32 *imap; + const __be32 *imap_end; + u32 parent_offset; +}; + +struct of_imap_item { + struct of_phandle_args parent_args; + u32 child_imap_count; + u32 child_imap[16]; /* Arbitrary size. + * Should be #address-cells + #interrupt-cells but + * avoid using allocation and so, expect that 16 + * should be enough + */ +}; + +/* + * If the iterator is exited prematurely (break, goto, return) of_node_put= () has + * to be called on item.parent_args.np + */ +#define for_each_of_imap_item(parser, item) \ + for (; of_imap_parser_one(parser, item);) + /* * Workarounds only applied to 32bit powermac machines */ @@ -47,6 +71,11 @@ extern int of_irq_get_byname(struct device_node *dev, co= nst char *name); extern int of_irq_to_resource_table(struct device_node *dev, struct resource *res, int nr_irqs); extern struct device_node *of_irq_find_parent(struct device_node *child); +extern int of_imap_parser_init(struct of_imap_parser *parser, + struct device_node *node, + struct of_imap_item *item); +extern struct of_imap_item *of_imap_parser_one(struct of_imap_parser *pars= er, + struct of_imap_item *item); extern struct irq_domain *of_msi_get_domain(struct device *dev, const struct device_node *np, enum irq_domain_bus_token token); @@ -86,7 +115,17 @@ static inline void *of_irq_find_parent(struct device_no= de *child) { return NULL; } - +static inline int of_imap_parser_init(struct of_imap_parser *parser, + struct device_node *node, + struct of_imap_item *item) +{ + return -ENOSYS; +} +extern struct of_imap_item *of_imap_parser_one(struct of_imap_parser *pars= er, + struct of_imap_item *item) +{ + return NULL; +} static inline struct irq_domain *of_msi_get_domain(struct device *dev, struct device_node *np, enum irq_domain_bus_token token) --=20 2.51.0 From nobody Thu Oct 2 23:48:26 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22E8A334364; Tue, 9 Sep 2025 12:01:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419294; cv=none; b=fbxxL06W36eF9+FoLd+VL4LsK7IBgSslDjdFz9nfDcEPm/NetGuMLqaMDeKhvGpFJhbbldgF+z62UGNZgXeHQyjV/V/LCOpamEotmrcOlIsM1LsyHXfn4P0QsmtDiVZklfyJv/3UKRGGlMzNQoZly7VNfXODn6Sc75ur0Nigf7Y= ARC-Message-Signature: i=1; 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charset="utf-8" Recently for_each_of_imap_item iterator has been introduce to help drivers in parsing the interrupt-map property. Add a test case for this iterator. Signed-off-by: Herve Codina (Schneider Electric) --- .../of/unittest-data/tests-interrupts.dtsi | 9 ++ drivers/of/unittest.c | 116 ++++++++++++++++++ 2 files changed, 125 insertions(+) diff --git a/drivers/of/unittest-data/tests-interrupts.dtsi b/drivers/of/un= ittest-data/tests-interrupts.dtsi index 4ccb54f91c30..974f888c9b15 100644 --- a/drivers/of/unittest-data/tests-interrupts.dtsi +++ b/drivers/of/unittest-data/tests-interrupts.dtsi @@ -50,6 +50,15 @@ test_intmap1: intmap1 { interrupt-map =3D <0x5000 1 2 &test_intc0 15>; }; =20 + intmap2 { + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-map =3D <1 11 &test_intc0 100>, + <2 22 &test_intc1 200 201 202>, + <3 33 &test_intc2 300 301>, + <4 44 &test_intc2 400 401>; + }; + test_intc_intmap0: intc-intmap0 { #interrupt-cells =3D <1>; #address-cells =3D <1>; diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index e3503ec20f6c..be4d9571f16e 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -1654,6 +1654,121 @@ static void __init of_unittest_parse_interrupts_ext= ended(void) of_node_put(np); } =20 +struct of_unittest_expected_imap_item { + u32 child_imap_count; + u32 child_imap[2]; + const char *parent_path; + int parent_args_count; + u32 parent_args[3]; +}; + +static const struct of_unittest_expected_imap_item of_unittest_expected_im= ap_items[] =3D { + { + .child_imap_count =3D 2, + .child_imap =3D {1, 11}, + .parent_path =3D "/testcase-data/interrupts/intc0", + .parent_args_count =3D 1, + .parent_args =3D {100}, + }, { + .child_imap_count =3D 2, + .child_imap =3D {2, 22}, + .parent_path =3D "/testcase-data/interrupts/intc1", + .parent_args_count =3D 3, + .parent_args =3D {200, 201, 202}, + }, { + .child_imap_count =3D 2, + .child_imap =3D {3, 33}, + .parent_path =3D "/testcase-data/interrupts/intc2", + .parent_args_count =3D 2, + .parent_args =3D {300, 301}, + }, { + .child_imap_count =3D 2, + .child_imap =3D {4, 44}, + .parent_path =3D "/testcase-data/interrupts/intc2", + .parent_args_count =3D 2, + .parent_args =3D {400, 401}, + } +}; + +static void __init of_unittest_parse_interrupt_map(void) +{ + const struct of_unittest_expected_imap_item *expected_item; + struct device_node *imap_np, *expected_parent_np; + struct of_imap_parser imap_parser; + struct of_imap_item imap_item; + int count, ret, i; + + if (of_irq_workarounds & (OF_IMAP_NO_PHANDLE | OF_IMAP_OLDWORLD_MAC)) + return; + + imap_np =3D of_find_node_by_path("/testcase-data/interrupts/intmap2"); + if (!imap_np) { + pr_err("missing testcase data\n"); + return; + } + + ret =3D of_imap_parser_init(&imap_parser, imap_np, &imap_item); + if (unittest(!ret, "of_imap_parser_init(%pOF) returned error %d\n", + imap_np, ret)) + goto end; + + expected_item =3D of_unittest_expected_imap_items; + count =3D 0; + + for_each_of_imap_item(&imap_parser, &imap_item) { + if (unittest(count < ARRAY_SIZE(of_unittest_expected_imap_items), + "imap item number %d not expected. Max number %zu\n", + count, ARRAY_SIZE(of_unittest_expected_imap_items) - 1)) { + of_node_put(imap_item.parent_args.np); + goto end; + } + + expected_parent_np =3D of_find_node_by_path(expected_item->parent_path); + if (unittest(expected_parent_np, + "missing dependent testcase data (%s)\n", + expected_item->parent_path)) { + of_node_put(imap_item.parent_args.np); + goto end; + } + + unittest(imap_item.child_imap_count =3D=3D expected_item->child_imap_cou= nt, + "imap[%d] child_imap_count =3D %u, expected %u\n", + count, imap_item.child_imap_count, + expected_item->child_imap_count); + + for (i =3D 0; i < expected_item->child_imap_count; i++) + unittest(imap_item.child_imap[i] =3D=3D expected_item->child_imap[i], + "imap[%d] child_imap[%d] =3D %u, expected %u\n", + count, i, imap_item.child_imap[i], + expected_item->child_imap[i]); + + unittest(imap_item.parent_args.np =3D=3D expected_parent_np, + "imap[%d] parent np =3D %pOF, expected %pOF\n", + count, imap_item.parent_args.np, expected_parent_np); + + unittest(imap_item.parent_args.args_count =3D=3D expected_item->parent_a= rgs_count, + "imap[%d] parent param_count =3D %d, expected %d\n", + count, imap_item.parent_args.args_count, + expected_item->parent_args_count); + + for (i =3D 0; i < expected_item->parent_args_count; i++) + unittest(imap_item.parent_args.args[i] =3D=3D expected_item->parent_arg= s[i], + "imap[%d] parent param[%d] =3D %u, expected %u\n", + count, i, imap_item.parent_args.args[i], + expected_item->parent_args[i]); + + of_node_put(expected_parent_np); + count++; + expected_item++; + } + + unittest(count =3D=3D ARRAY_SIZE(of_unittest_expected_imap_items), + "Missing items. %d parsed, expected %zu\n", + count, ARRAY_SIZE(of_unittest_expected_imap_items)); +end: + of_node_put(imap_np); +} + #if IS_ENABLED(CONFIG_OF_DYNAMIC) static void __init of_unittest_irq_refcount(void) { @@ -4394,6 +4509,7 @@ static int __init of_unittest(void) of_unittest_changeset_prop(); of_unittest_parse_interrupts(); of_unittest_parse_interrupts_extended(); + of_unittest_parse_interrupt_map(); of_unittest_irq_refcount(); of_unittest_dma_get_max_cpu_address(); of_unittest_parse_dma_ranges(); --=20 2.51.0 From nobody Thu Oct 2 23:48:26 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A0F93314C4; Tue, 9 Sep 2025 12:01:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419296; cv=none; b=NvNAhDfRqyJgr+WMMtcGJv9XwHmEZhPj6QQBzcrzjEQnSNUoBek+X0USzW/fx45xuAtQjU0HlIfRi9cusv0ukDVKgCW76uFkfz5u5DeAfFtrX3WOa6wi+GVILl/QOxk2+mwjqoRvliDWKaZtQtNfNf5gXi10ooHvNgIsHew7lPE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419296; c=relaxed/simple; bh=wKTOuqBfnalEmfN7yoZWb6HUSWjmCULlR5vNporkClE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" The ls-extirq driver parses the interrupt-map property. It does it using open code. Recently for_each_of_imap_item iterator has been introduce to help drivers in this parsing. Convert the ls-extirq driver to use the for_each_of_imap_item iterator instead of open code. Signed-off-by: Herve Codina (Schneider Electric) --- drivers/irqchip/irq-ls-extirq.c | 47 ++++++++++++--------------------- 1 file changed, 17 insertions(+), 30 deletions(-) diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extir= q.c index 50a7b38381b9..ed8755777349 100644 --- a/drivers/irqchip/irq-ls-extirq.c +++ b/drivers/irqchip/irq-ls-extirq.c @@ -125,45 +125,32 @@ static const struct irq_domain_ops extirq_domain_ops = =3D { static int ls_extirq_parse_map(struct ls_extirq_data *priv, struct device_node *node) { - const __be32 *map; - u32 mapsize; + struct of_imap_parser imap_parser; + struct of_imap_item imap_item; int ret; =20 - map =3D of_get_property(node, "interrupt-map", &mapsize); - if (!map) - return -ENOENT; - if (mapsize % sizeof(*map)) - return -EINVAL; - mapsize /=3D sizeof(*map); + ret =3D of_imap_parser_init(&imap_parser, node, &imap_item); + if (ret) + return ret; =20 - while (mapsize) { + for_each_of_imap_item(&imap_parser, &imap_item) { struct device_node *ipar; - u32 hwirq, intsize, j; + u32 hwirq; + int i; =20 - if (mapsize < 3) - return -EINVAL; - hwirq =3D be32_to_cpup(map); - if (hwirq >=3D MAXIRQ) + hwirq =3D imap_item.child_imap[0]; + if (hwirq >=3D MAXIRQ) { + of_node_put(imap_item.parent_args.np); return -EINVAL; + } priv->nirq =3D max(priv->nirq, hwirq + 1); =20 - ipar =3D of_find_node_by_phandle(be32_to_cpup(map + 2)); - map +=3D 3; - mapsize -=3D 3; - if (!ipar) - return -EINVAL; - priv->map[hwirq].fwnode =3D &ipar->fwnode; - ret =3D of_property_read_u32(ipar, "#interrupt-cells", &intsize); - if (ret) - return ret; - - if (intsize > mapsize) - return -EINVAL; + ipar =3D of_node_get(imap_item.parent_args.np); + priv->map[hwirq].fwnode =3D of_fwnode_handle(ipar); =20 - priv->map[hwirq].param_count =3D intsize; - for (j =3D 0; j < intsize; ++j) - priv->map[hwirq].param[j] =3D be32_to_cpup(map++); - mapsize -=3D intsize; + priv->map[hwirq].param_count =3D imap_item.parent_args.args_count; + for (i =3D 0; i < priv->map[hwirq].param_count; i++) + priv->map[hwirq].param[i] =3D imap_item.parent_args.args[i]; } return 0; } --=20 2.51.0 From nobody Thu Oct 2 23:48:26 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CFB8334722; Tue, 9 Sep 2025 12:01:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419298; cv=none; b=DW2BOa1WDKf9pvDB52prRI3d46C64vumq2gx/9r8kU/wtA+9uWUlgwZ5fhjefbDU7mlsqlraw1/ajZw1TkCuiGci/d0Zpemv6Jb47X8d6ON2qMjaUCXFyb2kq91zcrzCYgAf7zuYTkbRz9GCjkliHieONVTlxt5H0YxnBOylIeI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757419298; c=relaxed/simple; bh=piDyw/JBKCG/8fXN+QSQlF/zxGTFUxOsg8dUrAeAvbo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" The renesas-rza1 driver parses the interrupt-map property. It does it using open code. Recently for_each_of_imap_item iterator has been introduce to help drivers in this parsing. Convert the renesas-rza1 driver to use the for_each_of_imap_item iterator instead of open code. Signed-off-by: Herve Codina (Schneider Electric) --- drivers/irqchip/irq-renesas-rza1.c | 43 +++++++++++------------------- 1 file changed, 16 insertions(+), 27 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rza1.c b/drivers/irqchip/irq-renes= as-rza1.c index a697eb55ac90..789196b71656 100644 --- a/drivers/irqchip/irq-renesas-rza1.c +++ b/drivers/irqchip/irq-renesas-rza1.c @@ -142,46 +142,35 @@ static const struct irq_domain_ops rza1_irqc_domain_o= ps =3D { static int rza1_irqc_parse_map(struct rza1_irqc_priv *priv, struct device_node *gic_node) { - unsigned int imaplen, i, j, ret; + struct of_imap_parser imap_parser; struct device *dev =3D priv->dev; + struct of_imap_item imap_item; struct device_node *ipar; - const __be32 *imap; - u32 intsize; + int j, ret; + u32 i =3D 0; =20 - imap =3D of_get_property(dev->of_node, "interrupt-map", &imaplen); - if (!imap) - return -EINVAL; - - for (i =3D 0; i < IRQC_NUM_IRQ; i++) { - if (imaplen < 3) - return -EINVAL; + ret =3D of_imap_parser_init(&imap_parser, dev->of_node, &imap_item); + if (ret) + return ret; =20 + for_each_of_imap_item(&imap_parser, &imap_item) { /* Check interrupt number, ignore sense */ - if (be32_to_cpup(imap) !=3D i) + if (imap_item.child_imap[0] !=3D i) { + of_node_put(imap_item.parent_args.np); return -EINVAL; + } =20 - ipar =3D of_find_node_by_phandle(be32_to_cpup(imap + 2)); + ipar =3D imap_item.parent_args.np; if (ipar !=3D gic_node) { of_node_put(ipar); return -EINVAL; } =20 - imap +=3D 3; - imaplen -=3D 3; - - ret =3D of_property_read_u32(ipar, "#interrupt-cells", &intsize); - of_node_put(ipar); - if (ret) - return ret; - - if (imaplen < intsize) - return -EINVAL; - - priv->map[i].args_count =3D intsize; - for (j =3D 0; j < intsize; j++) - priv->map[i].args[j] =3D be32_to_cpup(imap++); + priv->map[i].args_count =3D imap_item.parent_args.args_count; + for (j =3D 0; j < priv->map[i].args_count; j++) + priv->map[i].args[j] =3D imap_item.parent_args.args[j]; =20 - imaplen -=3D intsize; + i++; } =20 return 0; --=20 2.51.0 From nobody Thu Oct 2 23:48:26 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEEFB32C31C; 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charset="utf-8" On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines. The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines. Signed-off-by: Herve Codina (Schneider Electric) --- drivers/soc/renesas/Kconfig | 4 ++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/rzn1_irqmux.c | 110 ++++++++++++++++++++++++++++++ 3 files changed, 115 insertions(+) create mode 100644 drivers/soc/renesas/rzn1_irqmux.c diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 719b7f4f376f..0878b6884515 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -58,6 +58,7 @@ config ARCH_RZN1 select PM select PM_GENERIC_DOMAINS select ARM_AMBA + select RZN1_IRQMUX =20 if ARM && ARCH_RENESAS =20 @@ -447,6 +448,9 @@ config PWC_RZV2M config RST_RCAR bool "Reset Controller support for R-Car" if COMPILE_TEST =20 +config RZN1_IRQMUX + bool "Renesas RZ/N1 GPIO IRQ multiplexer support" if COMPILE_TEST + config SYSC_RZ bool "System controller for RZ SoCs" if COMPILE_TEST =20 diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 3bdcc6a395d5..daa932c7698d 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -14,4 +14,5 @@ obj-$(CONFIG_SYS_R9A09G057) +=3D r9a09g057-sys.o # Family obj-$(CONFIG_PWC_RZV2M) +=3D pwc-rzv2m.o obj-$(CONFIG_RST_RCAR) +=3D rcar-rst.o +obj-$(CONFIG_RZN1_IRQMUX) +=3D rzn1_irqmux.o obj-$(CONFIG_SYSC_RZ) +=3D rz-sysc.o diff --git a/drivers/soc/renesas/rzn1_irqmux.c b/drivers/soc/renesas/rzn1_i= rqmux.c new file mode 100644 index 000000000000..3855e132c15f --- /dev/null +++ b/drivers/soc/renesas/rzn1_irqmux.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RZ/N1 GPIO Interrupt Multiplexer + * + * Copyright 2025 Schneider Electric + * Author: Herve Codina + */ + +#include +#include +#include +#include +#include + +#define IRQMUX_MAX_IRQS 8 + +static int irqmux_setup(struct device *dev, struct device_node *np, u32 __= iomem *regs) +{ + struct of_imap_parser imap_parser; + struct of_imap_item imap_item; + unsigned int index =3D 0; + u32 tmp; + int ret; + + /* We support only #interrupt-cells =3D <1> and #address-cells =3D <0> */ + ret =3D of_property_read_u32(np, "#interrupt-cells", &tmp); + if (ret) + return ret; + if (tmp !=3D 1) + return -EINVAL; + + ret =3D of_property_read_u32(np, "#address-cells", &tmp); + if (ret) + return ret; + if (tmp !=3D 0) + return -EINVAL; + + ret =3D of_imap_parser_init(&imap_parser, np, &imap_item); + if (ret) + return ret; + + for_each_of_imap_item(&imap_parser, &imap_item) { + /* + * The child #address-cells is 0 (already checked). The first + * value in imap item is the src hwirq. + * + * imap items matches 1:1 the interrupt lines that could + * be configured by registers (same order, same number). + * Configure the related register with the src hwirq retrieved + * from the interrupt-map. + */ + if (index > IRQMUX_MAX_IRQS) { + of_node_put(imap_item.parent_args.np); + dev_err(dev, "too much items in interrupt-map\n"); + return -EINVAL; + } + + writel(imap_item.child_imap[0], regs + index); + index++; + } + + return 0; +} + +static int irqmux_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + u32 __iomem *regs; + int nr_irqs; + int ret; + + regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + nr_irqs =3D of_irq_count(np); + if (nr_irqs < 0) + return nr_irqs; + + if (nr_irqs > IRQMUX_MAX_IRQS) { + dev_err(dev, "too many output interrupts\n"); + return -ENOENT; + } + + ret =3D irqmux_setup(dev, np, regs); + if (ret) + return dev_err_probe(dev, ret, "failed to setup mux\n"); + + return 0; +} + +static const struct of_device_id irqmux_of_match[] =3D { + { .compatible =3D "renesas,rzn1-gpioirqmux", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, irq_mux_of_match); + +static struct platform_driver irqmux_driver =3D { + .probe =3D irqmux_probe, + .driver =3D { + .name =3D "rzn1_irqmux", + .of_match_table =3D irqmux_of_match, + }, +}; +module_platform_driver(irqmux_driver); + +MODULE_AUTHOR("Herve Codina "); +MODULE_DESCRIPTION("Renesas RZ/N1 GPIO IRQ Multiplexer Driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Thu Oct 2 23:48:26 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6F2532C322; Tue, 9 Sep 2025 12:01:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; 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charset="utf-8" In the RZ/N1 SoC, the GPIO interrupts are multiplexed using the GPIO Interrupt Multiplexer. Add the multiplexer node and connect GPIO interrupt lines to the multiplexer. The interrupt-map available in the multiplexer node has to be updated in dts files depending on the GPIO usage. Indeed, the usage of an interrupt for a GPIO is board dependent. Up to 8 GPIOs can be used as an interrupt line (one per multiplexer output interrupt). Signed-off-by: Herve Codina (Schneider Electric) --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index da977cdd8487..3cd7ac38eb7a 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -534,6 +534,14 @@ gpio0a: gpio-port@0 { #gpio-cells =3D <2>; snps,nr-gpios =3D <32>; reg =3D <0>; + + interrupt-controller; + interrupt-parent =3D <&gpioirqmux>; + interrupts =3D < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 >; + #interrupt-cells =3D <2>; }; =20 /* GPIO0b[0..1] connected to pins GPIO1..2 */ @@ -576,6 +584,14 @@ gpio1a: gpio-port@0 { #gpio-cells =3D <2>; snps,nr-gpios =3D <32>; reg =3D <0>; + + interrupt-controller; + interrupt-parent =3D <&gpioirqmux>; + interrupts =3D < 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 >; + #interrupt-cells =3D <2>; }; =20 /* GPIO1b[0..1] connected to pins GPIO55..56 */ @@ -608,6 +624,14 @@ gpio2a: gpio-port@0 { #gpio-cells =3D <2>; snps,nr-gpios =3D <32>; reg =3D <0>; + + interrupt-controller; + interrupt-parent =3D <&gpioirqmux>; + interrupts =3D < 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 >; + #interrupt-cells =3D <2>; }; =20 /* GPIO2b[0..9] connected to pins GPIO160..169 */ @@ -620,6 +644,31 @@ gpio2b: gpio-port@1 { }; }; =20 + gpioirqmux: interrupt-controller@51000480 { + compatible =3D "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux= "; + reg =3D <0x51000480 0x20>; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + interrupt-map-mask =3D <0x7f>; + + /* + * interrupt-map has to be updated according to GPIO + * usage. The order has to be kept. Only the src irq + * (0 field) has to be updated with the needed GPIO + * interrupt number. + */ + interrupt-map =3D <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <0 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <0 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <0 &gic GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + can0: can@52104000 { compatible =3D "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; reg =3D <0x52104000 0x800>; --=20 2.51.0