From nobody Thu Oct 2 23:53:22 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3AABC32275D; Tue, 9 Sep 2025 11:44:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757418247; cv=none; b=KJhngmqFzwxoI0V4Tm2yh86nOLEk21n9leU8frqVRC3xotEvmMTdtA1I0IRqlSOSE9Dcx17GEPMuUKorWKbZTDMxd5A59Ykkaef5i72f7cTOLU3WuX0IjJEPQdLWLwuRMLHdeGz0sbA3KqvSuol4si6iE7M0/NuVBO7cL4g7leg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757418247; c=relaxed/simple; bh=sJzNiat9/vvoEo8GWmbDdFvAXzNFVsgoXdR8gHDWEXw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qrZGZUtf0FN5IO4SlUqofd0KKiRh3ETwh+jdwzEyqLLhqdk4s1DlcU6BWIpCGjKURQi5BCFPkIhuf49ci+MTvAH8hntzklpbIUBcDxPXgDySYAlTskK+aYs1+b9ENUO2MAnEnAthMIDHIWP9Os2lwJBYjknB5q1a6Im8A20YXf4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: tjNF6jKfSvaScX9qEndaTg== X-CSE-MsgGUID: vGn9OjD3TcuZ2jYxLOtZLQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 09 Sep 2025 20:39:01 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.24.0.1]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A3FFA401E4F5; Tue, 9 Sep 2025 20:38:54 +0900 (JST) From: John Madieu To: catalin.marinas@arm.com, conor+dt@kernel.org, daniel.lezcano@linaro.org, geert+renesas@glider.be, krzk+dt@kernel.org, lukasz.luba@arm.com, magnus.damm@gmail.com, mturquette@baylibre.com, p.zabel@pengutronix.de, robh@kernel.org, rui.zhang@intel.com, sboyd@kernel.org, will@kernel.org Cc: biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, john.madieu@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, rafael@kernel.org, John Madieu Subject: [PATCH v8 1/4] dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit Date: Tue, 9 Sep 2025 13:38:36 +0200 Message-ID: <20250909113840.122785-2-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250909113840.122785-1-john.madieu.xa@bp.renesas.com> References: <20250909113840.122785-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/G3E SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel (channel 1) for temperature sensing. Reviewed-by: Rob Herring (Arm) Signed-off-by: John Madieu --- Changes: v1 -> v2: * Fixes reg property specifier to get rid of yamlint warnings * Fixes IRQ name to reflect TSU expectations v2 -> v3: * Removees useless 'renesas,tsu-operating-mode' property=20 v3 -> v4: * Fixes commit message * Fixes interrupt description * Removes trip point definition v5: no changes v6: no changes v7: Adds documentation for 'renesas,tsu-trim' and removes Rb tag from Krzys= ztof due to this change v8: Address Rob's comments (about node naming and line wrapping) and collect Rb tag .../thermal/renesas,r9a09g047-tsu.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a09= g047-tsu.yaml diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-ts= u.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.ya= ml new file mode 100644 index 000000000000..8d3f3c24f0f2 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/renesas,r9a09g047-tsu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E Temperature Sensor Unit (TSU) + +maintainers: + - John Madieu + +description: + The Temperature Sensor Unit (TSU) is an integrated thermal sensor that + monitors the chip temperature on the Renesas RZ/G3E SoC. The TSU provides + real-time temperature measurements for thermal management. + +properties: + compatible: + const: renesas,r9a09g047-tsu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + interrupts: + items: + - description: Conversion complete interrupt signal (pulse) + - description: Comparison result interrupt signal (level) + + interrupt-names: + items: + - const: adi + - const: adcmpi + + "#thermal-sensor-cells": + const: 0 + + renesas,tsu-trim: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to system controller + - description: offset of trim registers + description: + Phandle and offset to the system controller containing the TSU + calibration trim values. The offset points to the first trim register + (OTPTSU1TRMVAL0), with the second trim register (OTPTSU1TRMVAL1) loc= ated + at offset + 4. + +required: + - compatible + - reg + - clocks + - resets + - power-domains + - interrupts + - interrupt-names + - "#thermal-sensor-cells" + - renesas,tsu-trim + +additionalProperties: false + +examples: + - | + #include + #include + + thermal-sensor@14002000 { + compatible =3D "renesas,r9a09g047-tsu"; + reg =3D <0x14002000 0x1000>; + clocks =3D <&cpg CPG_MOD 0x10a>; + resets =3D <&cpg 0xf8>; + power-domains =3D <&cpg>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + #thermal-sensor-cells =3D <0>; + renesas,tsu-trim =3D <&sys 0x330>; + }; --=20 2.25.1 From nobody Thu Oct 2 23:53:22 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AA5BC322763; Tue, 9 Sep 2025 11:44:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757418262; cv=none; b=h9ztxaCoUj4sfN3Z6RXvlPNKnMQCqcqZJk7pX/9vLABxkpEOT4PcjghR2TBNk+iKldluLG4Pi8ef3PIe78hPLVcRKLXnlZMCRzqoMPRfHncrBuFdiBllfFTZjQHDxvQ91btOFcKC58TyGPDLkj8WB+/0xOU8VhjzjiIctFyMgxI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757418262; c=relaxed/simple; bh=OJ7onWmBzxfQ3byEM1l7+dh8uGGZYjTgNE1sbTqahT0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=r5hR8a2jDBMyVuh2+4wIJZeZe4yFSRuo+MLKo3FiLZIvTt78/eiZRtn1t9cNSS/W9rkK0sGH6za+vrlYAIr9/fUnK3r3ewmgQ1qP62cKC8pSJGJ5/Q0yfdMQ7WckYLL6PGDhi61efTBbn3E09OPo2lbXmz93alQub/bN+GO6OdA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: hvyy3UqaRrynlfdxdSuTqg== X-CSE-MsgGUID: 84sEOOpeSTKWmo0pVAKJrw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 09 Sep 2025 20:39:09 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.24.0.1]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 47173400753A; Tue, 9 Sep 2025 20:39:02 +0900 (JST) From: John Madieu To: catalin.marinas@arm.com, conor+dt@kernel.org, daniel.lezcano@linaro.org, geert+renesas@glider.be, krzk+dt@kernel.org, lukasz.luba@arm.com, magnus.damm@gmail.com, mturquette@baylibre.com, p.zabel@pengutronix.de, robh@kernel.org, rui.zhang@intel.com, sboyd@kernel.org, will@kernel.org Cc: biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, john.madieu@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, rafael@kernel.org, John Madieu Subject: [PATCH v8 2/4] thermal: renesas: rzg3e: Add thermal driver for the Renesas RZ/G3E SoC Date: Tue, 9 Sep 2025 13:38:37 +0200 Message-ID: <20250909113840.122785-3-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250909113840.122785-1-john.madieu.xa@bp.renesas.com> References: <20250909113840.122785-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The RZ/G3E SoC integrates a Temperature Sensor Unit (TSU) block designed to monitor the chip's junction temperature. This sensor is connected to channel 1 of the APB port clock/reset and provides temperature measurements. It also requires calibration values stored in the system controller registe= rs for accurate temperature measurement. Add a driver for the Renesas RZ/G3E T= SU. Signed-off-by: John Madieu --- Changes: v1 -> v2: fixes IRQ names v2 -> v3: no changes v3 -> v4: no changes v5: Removed curly braces arround single-line protected scoped guards v6: Clarified comments in driver v7: Refactored driver structure: - removes splinlock usage - updates polling timeout as per the datasheet - uses average mode to be more accurate - uses polling (faster than irq mode) for get_temp() while keeping IRQ fo= r hw trip-point cross detection. - adds both runtime and sleep PM support v8: - Use of_parse_phandle_with_fixed_args() for trim values - Use millidegree computation to for better precision MAINTAINERS | 7 + drivers/thermal/renesas/Kconfig | 7 + drivers/thermal/renesas/Makefile | 1 + drivers/thermal/renesas/rzg3e_thermal.c | 564 ++++++++++++++++++++++++ 4 files changed, 579 insertions(+) create mode 100644 drivers/thermal/renesas/rzg3e_thermal.c diff --git a/MAINTAINERS b/MAINTAINERS index 10614ca41ed0..5480412f556d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21544,6 +21544,13 @@ S: Maintained F: Documentation/devicetree/bindings/iio/potentiometer/renesas,x9250.yaml F: drivers/iio/potentiometer/x9250.c =20 +RENESAS RZ/G3E THERMAL SENSOR UNIT DRIVER +M: John Madieu +L: linux-pm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml +F: drivers/thermal/renesas/rzg3e_thermal.c + RESET CONTROLLER FRAMEWORK M: Philipp Zabel S: Maintained diff --git a/drivers/thermal/renesas/Kconfig b/drivers/thermal/renesas/Kcon= fig index dcf5fc5ae08e..10cf90fc4bfa 100644 --- a/drivers/thermal/renesas/Kconfig +++ b/drivers/thermal/renesas/Kconfig @@ -26,3 +26,10 @@ config RZG2L_THERMAL help Enable this to plug the RZ/G2L thermal sensor driver into the Linux thermal framework. + +config RZG3E_THERMAL + tristate "Renesas RZ/G3E thermal driver" + depends on ARCH_RENESAS || COMPILE_TEST + help + Enable this to plug the RZ/G3E thermal sensor driver into the Linux + thermal framework. diff --git a/drivers/thermal/renesas/Makefile b/drivers/thermal/renesas/Mak= efile index bf9cb3cb94d6..5a3eba0dedd0 100644 --- a/drivers/thermal/renesas/Makefile +++ b/drivers/thermal/renesas/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_RCAR_GEN3_THERMAL) +=3D rcar_gen3_thermal.o obj-$(CONFIG_RCAR_THERMAL) +=3D rcar_thermal.o obj-$(CONFIG_RZG2L_THERMAL) +=3D rzg2l_thermal.o +obj-$(CONFIG_RZG3E_THERMAL) +=3D rzg3e_thermal.o diff --git a/drivers/thermal/renesas/rzg3e_thermal.c b/drivers/thermal/rene= sas/rzg3e_thermal.c new file mode 100644 index 000000000000..e8c599be0b2c --- /dev/null +++ b/drivers/thermal/renesas/rzg3e_thermal.c @@ -0,0 +1,564 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G3E TSU Temperature Sensor Unit + * + * Copyright (C) 2025 Renesas Electronics Corporation + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_hwmon.h" + +/* TSU Register offsets and bits */ +#define TSU_SSUSR 0x00 +#define TSU_SSUSR_EN_TS BIT(0) +#define TSU_SSUSR_ADC_PD_TS BIT(1) +#define TSU_SSUSR_SOC_TS_EN BIT(2) + +#define TSU_STRGR 0x04 +#define TSU_STRGR_ADST BIT(0) + +#define TSU_SOSR1 0x08 +#define TSU_SOSR1_ADCT_8 0x03 +#define TSU_SOSR1_ADCS BIT(4) +#define TSU_SOSR1_OUTSEL BIT(9) + +#define TSU_SCRR 0x10 +#define TSU_SCRR_OUT12BIT_TS GENMASK(11, 0) + +#define TSU_SSR 0x14 +#define TSU_SSR_CONV BIT(0) + +#define TSU_CMSR 0x18 +#define TSU_CMSR_CMPEN BIT(0) + +#define TSU_LLSR 0x1C +#define TSU_ULSR 0x20 + +#define TSU_SISR 0x30 +#define TSU_SISR_ADF BIT(0) +#define TSU_SISR_CMPF BIT(1) + +#define TSU_SIER 0x34 +#define TSU_SIER_CMPIE BIT(1) + +#define TSU_SICR 0x38 +#define TSU_SICR_ADCLR BIT(0) +#define TSU_SICR_CMPCLR BIT(1) + +/* Temperature calculation constants from datasheet */ +#define TSU_TEMP_D (-41) +#define TSU_TEMP_E 126 +#define TSU_CODE_MAX 0xFFF + +/* Timing specifications from datasheet */ +#define TSU_POWERUP_TIME_US 120 /* 120T at 1MHz sensor clock per datasheet= */ +#define TSU_CONV_TIME_US 50 /* Per sample conversion time */ +#define TSU_POLL_DELAY_US 10 /* Polling interval */ +#define TSU_MIN_CLOCK_RATE 24000000 /* TSU_PCLK minimum 24MHz */ + +/** + * struct rzg3e_thermal_priv - RZ/G3E TSU private data + * @base: TSU register base + * @dev: device pointer + * @syscon: regmap for calibration values + * @zone: thermal zone device + * @rstc: reset control + * @trmval0: calibration value 0 (b) + * @trmval1: calibration value 1 (c) + * @trim_offset: offset for trim registers in syscon + * @lock: protects hardware access during conversions + */ +struct rzg3e_thermal_priv { + void __iomem *base; + struct device *dev; + struct regmap *syscon; + struct thermal_zone_device *zone; + struct reset_control *rstc; + u16 trmval0; + u16 trmval1; + u32 trim_offset; + struct mutex lock; +}; + +static inline u32 rzg3e_thermal_read(struct rzg3e_thermal_priv *priv, u32 = reg) +{ + return readl(priv->base + reg); +} + +static inline void rzg3e_thermal_write(struct rzg3e_thermal_priv *priv, + u32 reg, u32 val) +{ + writel(val, priv->base + reg); +} + +static int rzg3e_thermal_power_on(struct rzg3e_thermal_priv *priv) +{ + u32 val; + int ret; + + /* Clear any pending interrupts */ + rzg3e_thermal_write(priv, TSU_SICR, TSU_SICR_ADCLR | TSU_SICR_CMPCLR); + + /* Disable all interrupts during setup */ + rzg3e_thermal_write(priv, TSU_SIER, 0); + + /* + * Power-on sequence per datasheet 7.11.9.1: + * SOC_TS_EN must be set at same time or before EN_TS and ADC_PD_TS + */ + val =3D TSU_SSUSR_SOC_TS_EN | TSU_SSUSR_EN_TS; + rzg3e_thermal_write(priv, TSU_SSUSR, val); + + /* Wait for sensor stabilization per datasheet 7.11.7.1 */ + usleep_range(TSU_POWERUP_TIME_US, TSU_POWERUP_TIME_US + 10); + + /* Configure for average mode with 8 samples */ + val =3D TSU_SOSR1_OUTSEL | TSU_SOSR1_ADCT_8; + rzg3e_thermal_write(priv, TSU_SOSR1, val); + + /* Ensure we're in single scan mode (default) */ + val =3D rzg3e_thermal_read(priv, TSU_SOSR1); + if (val & TSU_SOSR1_ADCS) { + dev_err(priv->dev, "Invalid scan mode setting\n"); + return -EINVAL; + } + + /* Wait for any ongoing conversion to complete */ + ret =3D readl_poll_timeout(priv->base + TSU_SSR, val, + !(val & TSU_SSR_CONV), + TSU_POLL_DELAY_US, + USEC_PER_MSEC); + if (ret) { + dev_err(priv->dev, "Timeout waiting for conversion\n"); + return ret; + } + + return 0; +} + +static void rzg3e_thermal_power_off(struct rzg3e_thermal_priv *priv) +{ + /* Disable all interrupts */ + rzg3e_thermal_write(priv, TSU_SIER, 0); + + /* Clear pending interrupts */ + rzg3e_thermal_write(priv, TSU_SICR, TSU_SICR_ADCLR | TSU_SICR_CMPCLR); + + /* Power down sequence per datasheet */ + rzg3e_thermal_write(priv, TSU_SSUSR, TSU_SSUSR_ADC_PD_TS); +} + +/* + * Convert 12-bit sensor code to temperature in millicelsius + * Formula from datasheet 7.11.7.8: + * T(=C2=B0C) =3D ((e - d) / (c - b)) * (a - b) + d + * where: a =3D sensor code, b =3D trmval0, c =3D trmval1, d =3D -41, e = =3D 126 + */ +static int rzg3e_thermal_code_to_temp(struct rzg3e_thermal_priv *priv, u16= code) +{ + int temp_e_mc =3D TSU_TEMP_E * MILLIDEGREE_PER_DEGREE; + int temp_d_mc =3D TSU_TEMP_D * MILLIDEGREE_PER_DEGREE; + s64 numerator, denominator; + int temp_mc; + + numerator =3D (temp_e_mc - temp_d_mc) * (s64)(code - priv->trmval0); + denominator =3D priv->trmval1 - priv->trmval0; + + temp_mc =3D div64_s64(numerator, denominator) + temp_d_mc; + + return clamp(temp_mc, temp_d_mc, temp_e_mc); +} + +/* + * Convert temperature in millicelsius to 12-bit sensor code + * Formula from datasheet 7.11.7.9 (inverse of above) + */ +static u16 rzg3e_thermal_temp_to_code(struct rzg3e_thermal_priv *priv, int= temp_mc) +{ + int temp_e_mc =3D TSU_TEMP_E * MILLIDEGREE_PER_DEGREE; + int temp_d_mc =3D TSU_TEMP_D * MILLIDEGREE_PER_DEGREE; + s64 numerator, denominator; + s64 code; + + numerator =3D (temp_mc - temp_d_mc) * (priv->trmval1 - priv->trmval0); + denominator =3D temp_e_mc - temp_d_mc; + + code =3D div64_s64(numerator, denominator) + priv->trmval0; + + return clamp_val(code, 0, TSU_CODE_MAX); +} + +static int rzg3e_thermal_get_temp(struct thermal_zone_device *tz, int *tem= p) +{ + struct rzg3e_thermal_priv *priv =3D thermal_zone_device_priv(tz); + u32 status, code; + int ret, timeout; + + ret =3D pm_runtime_resume_and_get(priv->dev); + if (ret < 0) + return ret; + + guard(mutex)(&priv->lock); + + /* Clear any previous conversion status */ + rzg3e_thermal_write(priv, TSU_SICR, TSU_SICR_ADCLR); + + /* Start single conversion */ + rzg3e_thermal_write(priv, TSU_STRGR, TSU_STRGR_ADST); + + /* Wait for conversion completion - 8 samples at ~50us each */ + timeout =3D TSU_CONV_TIME_US * 8 * 2; /* Double for margin */ + ret =3D readl_poll_timeout(priv->base + TSU_SISR, status, + status & TSU_SISR_ADF, + TSU_POLL_DELAY_US, timeout); + if (ret) { + dev_err(priv->dev, "Conversion timeout (status=3D0x%08x)\n", status); + goto out; + } + + /* Read the averaged result and clear the complete flag */ + code =3D rzg3e_thermal_read(priv, TSU_SCRR) & TSU_SCRR_OUT12BIT_TS; + rzg3e_thermal_write(priv, TSU_SICR, TSU_SICR_ADCLR); + + /* Convert to temperature */ + *temp =3D rzg3e_thermal_code_to_temp(priv, code); + + dev_dbg(priv->dev, "temp=3D%d mC (%d.%03d=C2=B0C), code=3D0x%03x\n", + *temp, *temp / 1000, abs(*temp) % 1000, code); + +out: + pm_runtime_mark_last_busy(priv->dev); + pm_runtime_put_autosuspend(priv->dev); + return ret; +} + +static int rzg3e_thermal_set_trips(struct thermal_zone_device *tz, + int low, int high) +{ + struct rzg3e_thermal_priv *priv =3D thermal_zone_device_priv(tz); + u16 low_code, high_code; + u32 val; + int ret; + + /* Hardware requires low < high */ + if (low >=3D high) + return -EINVAL; + + ret =3D pm_runtime_resume_and_get(priv->dev); + if (ret < 0) + return ret; + + guard(mutex)(&priv->lock); + + /* Convert temperatures to codes */ + low_code =3D rzg3e_thermal_temp_to_code(priv, low); + high_code =3D rzg3e_thermal_temp_to_code(priv, high); + + dev_dbg(priv->dev, "set_trips: low=3D%d high=3D%d (codes: 0x%03x/0x%03x)\= n", + low, high, low_code, high_code); + + /* Disable comparison during reconfiguration */ + rzg3e_thermal_write(priv, TSU_SIER, 0); + rzg3e_thermal_write(priv, TSU_CMSR, 0); + + /* Clear any pending comparison interrupts */ + rzg3e_thermal_write(priv, TSU_SICR, TSU_SICR_CMPCLR); + + /* Set trip points */ + rzg3e_thermal_write(priv, TSU_LLSR, low_code); + rzg3e_thermal_write(priv, TSU_ULSR, high_code); + + /* + * Ensure OUTSEL is set for comparison per datasheet 7.11.7.4 + * Comparison uses averaged data + */ + val =3D rzg3e_thermal_read(priv, TSU_SOSR1); + val |=3D TSU_SOSR1_OUTSEL; + rzg3e_thermal_write(priv, TSU_SOSR1, val); + + /* Enable comparison with "out of range" mode (CMPCOND=3D0) */ + rzg3e_thermal_write(priv, TSU_CMSR, TSU_CMSR_CMPEN); + + /* Unmask compare IRQ and start a conversion to evaluate window */ + rzg3e_thermal_write(priv, TSU_SIER, TSU_SIER_CMPIE); + rzg3e_thermal_write(priv, TSU_STRGR, TSU_STRGR_ADST); + + pm_runtime_mark_last_busy(priv->dev); + pm_runtime_put_autosuspend(priv->dev); + + return 0; +} + +static irqreturn_t rzg3e_thermal_irq_thread(int irq, void *data) +{ + struct rzg3e_thermal_priv *priv =3D data; + + dev_dbg(priv->dev, "Temperature threshold crossed\n"); + + /* Notify thermal framework to re-evaluate trip points */ + thermal_zone_device_update(priv->zone, THERMAL_TRIP_VIOLATED); + + return IRQ_HANDLED; +} + +static irqreturn_t rzg3e_thermal_irq(int irq, void *data) +{ + struct rzg3e_thermal_priv *priv =3D data; + u32 status; + + status =3D rzg3e_thermal_read(priv, TSU_SISR); + + /* Check if comparison interrupt occurred */ + if (status & TSU_SISR_CMPF) { + /* Clear irq flag and disable interrupt until reconfigured */ + rzg3e_thermal_write(priv, TSU_SICR, TSU_SICR_CMPCLR); + rzg3e_thermal_write(priv, TSU_SIER, 0); + + return IRQ_WAKE_THREAD; + } + + return IRQ_NONE; +} + +static const struct thermal_zone_device_ops rzg3e_tz_ops =3D { + .get_temp =3D rzg3e_thermal_get_temp, + .set_trips =3D rzg3e_thermal_set_trips, +}; + +static int rzg3e_thermal_get_calibration(struct rzg3e_thermal_priv *priv) +{ + u32 val; + int ret; + + /* Read calibration values from syscon */ + ret =3D regmap_read(priv->syscon, priv->trim_offset, &val); + if (ret) + return ret; + priv->trmval0 =3D val & GENMASK(11, 0); + + ret =3D regmap_read(priv->syscon, priv->trim_offset + 4, &val); + if (ret) + return ret; + priv->trmval1 =3D val & GENMASK(11, 0); + + /* Validate calibration data */ + if (!priv->trmval0 || !priv->trmval1 || + priv->trmval0 =3D=3D priv->trmval1 || + priv->trmval0 =3D=3D 0xFFF || priv->trmval1 =3D=3D 0xFFF) { + dev_err(priv->dev, "Invalid calibration: b=3D0x%03x, c=3D0x%03x\n", + priv->trmval0, priv->trmval1); + return -EINVAL; + } + + dev_dbg(priv->dev, "Calibration: b=3D0x%03x (%u), c=3D0x%03x (%u)\n", + priv->trmval0, priv->trmval0, priv->trmval1, priv->trmval1); + + return 0; +} + +static int rzg3e_thermal_parse_dt(struct rzg3e_thermal_priv *priv) +{ + struct device_node *np =3D priv->dev->of_node; + struct of_phandle_args args; + int ret; + + ret =3D of_parse_phandle_with_fixed_args(np, "renesas,tsu-trim", 1, 0, &a= rgs); + if (ret) + return dev_err_probe(priv->dev, ret, + "Failed to parse renesas,tsu-trim\n"); + + priv->trim_offset =3D args.args[0]; + priv->syscon =3D syscon_node_to_regmap(args.np); + of_node_put(args.np); + + if (IS_ERR(priv->syscon)) + return dev_err_probe(priv->dev, PTR_ERR(priv->syscon), + "Failed to get syscon regmap\n"); + + return 0; +} + +static int rzg3e_thermal_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rzg3e_thermal_priv *priv; + struct clk *clk; + int irq, ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + mutex_init(&priv->lock); + platform_set_drvdata(pdev, priv); + + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + /* Parse device tree for trim register info */ + ret =3D rzg3e_thermal_parse_dt(priv); + if (ret) + return ret; + + /* Get clock to verify frequency - clock is managed by power domain */ + clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get clock\n"); + + if (clk_get_rate(clk) < TSU_MIN_CLOCK_RATE) + return dev_err_probe(dev, -EINVAL, + "Clock rate %lu Hz too low (min %u Hz)\n", + clk_get_rate(clk), TSU_MIN_CLOCK_RATE); + + priv->rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(priv->rstc)) + return dev_err_probe(dev, PTR_ERR(priv->rstc), + "Failed to get/deassert reset control\n"); + + /* Get calibration data */ + ret =3D rzg3e_thermal_get_calibration(priv); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get valid calibration data\n"); + + /* Get comparison interrupt */ + irq =3D platform_get_irq_byname(pdev, "adcmpi"); + if (irq < 0) + return irq; + + /* Enable runtime PM */ + pm_runtime_set_autosuspend_delay(dev, 1000); + pm_runtime_use_autosuspend(dev); + devm_pm_runtime_enable(dev); + + /* Initial hardware setup */ + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Runtime resume failed\n"); + + /* Register thermal zone - this will trigger DT parsing */ + priv->zone =3D devm_thermal_of_zone_register(dev, 0, priv, &rzg3e_tz_ops); + if (IS_ERR(priv->zone)) { + ret =3D PTR_ERR(priv->zone); + dev_err(dev, "Failed to register thermal zone: %d\n", ret); + goto err_pm_put; + } + + /* Request threaded IRQ for comparison interrupt */ + ret =3D devm_request_threaded_irq(dev, irq, rzg3e_thermal_irq, + rzg3e_thermal_irq_thread, + IRQF_ONESHOT, "rzg3e_thermal", priv); + if (ret) { + dev_err(dev, "Failed to request IRQ: %d\n", ret); + goto err_pm_put; + } + + /* Add hwmon sysfs interface */ + ret =3D devm_thermal_add_hwmon_sysfs(dev, priv->zone); + if (ret) + dev_warn(dev, "Failed to add hwmon sysfs attributes\n"); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + dev_info(dev, "RZ/G3E thermal sensor registered\n"); + + return 0; + +err_pm_put: + pm_runtime_put_sync(dev); + return ret; +} + +static int rzg3e_thermal_runtime_suspend(struct device *dev) +{ + struct rzg3e_thermal_priv *priv =3D dev_get_drvdata(dev); + + rzg3e_thermal_power_off(priv); + return 0; +} + +static int rzg3e_thermal_runtime_resume(struct device *dev) +{ + struct rzg3e_thermal_priv *priv =3D dev_get_drvdata(dev); + + return rzg3e_thermal_power_on(priv); +} + +static int rzg3e_thermal_suspend(struct device *dev) +{ + struct rzg3e_thermal_priv *priv =3D dev_get_drvdata(dev); + + /* If device is active, power it off */ + if (pm_runtime_active(dev)) + rzg3e_thermal_power_off(priv); + + /* Assert reset to ensure clean state after resume */ + reset_control_assert(priv->rstc); + + return 0; +} + +static int rzg3e_thermal_resume(struct device *dev) +{ + struct rzg3e_thermal_priv *priv =3D dev_get_drvdata(dev); + int ret; + + /* Deassert reset */ + ret =3D reset_control_deassert(priv->rstc); + if (ret) { + dev_err(dev, "Failed to deassert reset: %d\n", ret); + return ret; + } + + /* If device was active before suspend, power it back on */ + if (pm_runtime_active(dev)) + return rzg3e_thermal_power_on(priv); + + return 0; +} + +static const struct dev_pm_ops rzg3e_thermal_pm_ops =3D { + RUNTIME_PM_OPS(rzg3e_thermal_runtime_suspend, + rzg3e_thermal_runtime_resume, NULL) + SYSTEM_SLEEP_PM_OPS(rzg3e_thermal_suspend, rzg3e_thermal_resume) +}; + +static const struct of_device_id rzg3e_thermal_dt_ids[] =3D { + { .compatible =3D "renesas,r9a09g047-tsu" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids); + +static struct platform_driver rzg3e_thermal_driver =3D { + .driver =3D { + .name =3D "rzg3e_thermal", + .of_match_table =3D rzg3e_thermal_dt_ids, + .pm =3D pm_ptr(&rzg3e_thermal_pm_ops), + }, + .probe =3D rzg3e_thermal_probe, +}; +module_platform_driver(rzg3e_thermal_driver); + +MODULE_DESCRIPTION("Renesas RZ/G3E TSU Thermal Sensor Driver"); +MODULE_AUTHOR("John Madieu "); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Thu Oct 2 23:53:22 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9D2E4321F30; Tue, 9 Sep 2025 11:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757417961; cv=none; b=b0ZP1cPD1f3f37pyamAfhlj6ai+v9i+BjHQrRJy5h7f9UnikuJBq1VlXc2BumYJvPlkU9KMKsqu2oxgEbpFSkw0gt1LLmBcA8xEg8XtyPtVpuXUmY2GT1jul3ch0UMfYOBjw8jqmBJJNfP4eY2KN6TN7TxDBHchR3D3mE5HxK4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757417961; c=relaxed/simple; bh=CHPbTooWowOL079vaBy/qBwFT7KJeeIl2InuLMLVYvs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MSJ7jaoZOZ03ZXwAhDo1k+zErZLiN7CLmEZR7n0LjO1l0NtiBRhXUgsd/YRc2pn2epRYTnKhAzM8z/azCLu3U8FtZeZdCS717WnUF8up9W9nNS/66IHaT46/8l+QtvThL+U7HuaTiEfUm/10CAjkbfXjCJkIwx858nhj76eSL6g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: XG4teax0ScWfSw974WDPmA== X-CSE-MsgGUID: Q86cjfVuTQOozpLkHMby7w== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 09 Sep 2025 20:39:17 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.24.0.1]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 47829400753A; Tue, 9 Sep 2025 20:39:09 +0900 (JST) From: John Madieu To: catalin.marinas@arm.com, conor+dt@kernel.org, daniel.lezcano@linaro.org, geert+renesas@glider.be, krzk+dt@kernel.org, lukasz.luba@arm.com, magnus.damm@gmail.com, mturquette@baylibre.com, p.zabel@pengutronix.de, robh@kernel.org, rui.zhang@intel.com, sboyd@kernel.org, will@kernel.org Cc: biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, john.madieu@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, rafael@kernel.org, John Madieu Subject: [PATCH v8 3/4] arm64: dts: renesas: r9a09g047: Add TSU node Date: Tue, 9 Sep 2025 13:38:38 +0200 Message-ID: <20250909113840.122785-4-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250909113840.122785-1-john.madieu.xa@bp.renesas.com> References: <20250909113840.122785-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add TSU node along with thermal zones and keep it enabled in the SoC DTSI. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven --- v1 -> v2: Fix IRQ names v2 -> v3: remove useless 'renesas,tsu-operating-mode' property' v3 -> v4: no changes v5: no changes v6: no changes v7: updated both property name and specifier () for trim pr= operty. v8: removed #address-cells property arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index e4fac7e0d764..7bf0b4a6c67a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -64,6 +64,7 @@ cpu0: cpu@0 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -74,6 +75,7 @@ cpu1: cpu@100 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -84,6 +86,7 @@ cpu2: cpu@200 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -94,6 +97,7 @@ cpu3: cpu@300 { next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; clocks =3D <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; + #cooling-cells =3D <2>; operating-points-v2 =3D <&cluster0_opp>; }; =20 @@ -412,6 +416,19 @@ wdt3: watchdog@13000400 { status =3D "disabled"; }; =20 + tsu: thermal@14002000 { + compatible =3D "renesas,r9a09g047-tsu"; + reg =3D <0 0x14002000 0 0x1000>; + interrupts =3D , + ; + interrupt-names =3D "adi", "adcmpi"; + clocks =3D <&cpg CPG_MOD 0x10a>; + resets =3D <&cpg 0xf8>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + renesas,tsu-trim =3D <&sys 0x330>; + }; + i2c0: i2c@14400400 { compatible =3D "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; reg =3D <0 0x14400400 0 0x400>; @@ -970,6 +987,37 @@ stmmac_axi_setup: stmmac-axi-config { snps,blen =3D <16 8 4 0 0 0 0>; }; =20 + thermal-zones { + cpu-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&tsu>; + + cooling-maps { + map0 { + trip =3D <&target>; + cooling-device =3D <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution =3D <1024>; + }; + }; + + trips { + target: trip-point { + temperature =3D <95000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + sensor_crit: sensor-crit { + temperature =3D <120000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts-extended =3D <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, --=20 2.25.1 From nobody Thu Oct 2 23:53:22 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 034D1321F30; Tue, 9 Sep 2025 11:39:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 507sXnTvQliEhFBs3Q4Mdg== X-CSE-MsgGUID: Qc/LLW2OR6SwhPfPrNNvTA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 09 Sep 2025 20:39:26 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.24.0.1]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4AF0E401E4F5; Tue, 9 Sep 2025 20:39:17 +0900 (JST) From: John Madieu To: catalin.marinas@arm.com, conor+dt@kernel.org, daniel.lezcano@linaro.org, geert+renesas@glider.be, krzk+dt@kernel.org, lukasz.luba@arm.com, magnus.damm@gmail.com, mturquette@baylibre.com, p.zabel@pengutronix.de, robh@kernel.org, rui.zhang@intel.com, sboyd@kernel.org, will@kernel.org Cc: biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, john.madieu@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, rafael@kernel.org, John Madieu , Krzysztof Kozlowski Subject: [PATCH v8 4/4] arm64: defconfig: Enable the Renesas RZ/G3E thermal driver Date: Tue, 9 Sep 2025 13:38:39 +0200 Message-ID: <20250909113840.122785-5-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250909113840.122785-1-john.madieu.xa@bp.renesas.com> References: <20250909113840.122785-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the Renesas RZ/G3E thermal driver, as used on the Renesas RZ/G3E SMARC EVK board. Reviewed-by: Krzysztof Kozlowski Signed-off-by: John Madieu --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 58f87d09366c..8def47e094d0 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -728,6 +728,7 @@ CONFIG_ROCKCHIP_THERMAL=3Dm CONFIG_RCAR_THERMAL=3Dy CONFIG_RCAR_GEN3_THERMAL=3Dy CONFIG_RZG2L_THERMAL=3Dy +CONFIG_RZG3E_THERMAL=3Dy CONFIG_ARMADA_THERMAL=3Dy CONFIG_MTK_THERMAL=3Dm CONFIG_MTK_LVTS_THERMAL=3Dm --=20 2.25.1