From nobody Fri Oct 3 01:09:27 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 380D51D5AC6; Tue, 9 Sep 2025 09:40:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757410811; cv=none; b=X0rFF+jflhj4AMvp7nF/nzTuYMNFK9bLazaWu5/+cQQKGB/yJkN7xbDbJOgij6bHjDp+ewA1IwMWc30b7rXswTDeOYQ6uh5AxlgXPqK/Ks1o8Wks273PhRMElfUOyVm9PbD5WAWNqegu1eEPtOHDwsVE7xcT/6ns7KTPEJAa7wc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757410811; c=relaxed/simple; bh=wpvcrJHwYBLC5/dciOZjQsOznM/ZeVV2wM2oj/cDelA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KFVcJR/2z1v4DKFAMNmRHlM2xOQs2VOqCzR+K1mU6pDja7cTSxmaDVT7/DKzfSrpYqqVnRO4MsbxESqHOWvar17WnXjLftzIfdTdAtN+eiKsOGTqKyIIQDq+gMNxefKV0GbI+Q6QS2ZkR2WFeqyvAKU5uUAY45EACQ/UQl0/ODY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YCm1OXhS; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YCm1OXhS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757410809; x=1788946809; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wpvcrJHwYBLC5/dciOZjQsOznM/ZeVV2wM2oj/cDelA=; b=YCm1OXhSEN5fSLNvT7SXMcgd/+YkrPmYgdDp0ZH/iprLYsDhlO5rpVBI dOBaoteZJIna2N7CmiMlXcd1F2pcBmwIp/6OK19bvifFXMMSfFJMOsAjB Oe75r6LQU+NTxPHOHS+GnOYqnS4JqprR7uCrZE//Rvi7Qu0j6QuxaWsZu zJMPaGt0GTzQKwi7AihP130V1eTCIcwgXlixXnC0jKjD+skCMJcyb31FU HZFWf5iNSibzVP2J3TLL5QbTz/382+HP6jo1Ieq1Rxg9BzdKA6Pys97d6 OAZYs6LRwBE+CefJXYdqfktQLhCHTMEjpOcCvtqAP7ILs3JxA+boB3Hxc g==; X-CSE-ConnectionGUID: F2eDeufRQBCr7KZD4TmrsQ== X-CSE-MsgGUID: PN0fOxfYT+u21T8nymWI7w== X-IronPort-AV: E=McAfee;i="6800,10657,11547"; a="70307331" X-IronPort-AV: E=Sophos;i="6.18,251,1751266800"; d="scan'208";a="70307331" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2025 02:39:57 -0700 X-CSE-ConnectionGUID: NpBX9s3cSAmOB2EK1pFUAQ== X-CSE-MsgGUID: 5BZ5dLArRBqPMyAJQnHZfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,251,1751266800"; d="scan'208";a="172207442" Received: from unknown (HELO CannotLeaveINTEL.jf.intel.com) ([10.165.54.94]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2025 02:39:57 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: acme@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, john.allen@amd.com, mingo@kernel.org, mingo@redhat.com, minipli@grsecurity.net, mlevitsk@redhat.com, namhyung@kernel.org, pbonzini@redhat.com, prsampat@amd.com, rick.p.edgecombe@intel.com, seanjc@google.com, shuah@kernel.org, tglx@linutronix.de, weijiang.yang@intel.com, x86@kernel.org, xin@zytor.com, xiaoyao.li@intel.com Subject: [PATCH v14 19/22] KVM: nVMX: Add consistency checks for CR0.WP and CR4.CET Date: Tue, 9 Sep 2025 02:39:50 -0700 Message-ID: <20250909093953.202028-20-chao.gao@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20250909093953.202028-1-chao.gao@intel.com> References: <20250909093953.202028-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add consistency checks for CR4.CET and CR0.WP in guest-state or host-state area in the VMCS12. This ensures that configurations with CR4.CET set and CR0.WP not set result in VM-entry failure, aligning with architectural behavior. Tested-by: Mathias Krause Tested-by: John Allen Tested-by: Rick Edgecombe Signed-off-by: Chao Gao --- arch/x86/kvm/vmx/nested.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 51d69f368689..a73f38d7eea1 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -3111,6 +3111,9 @@ static int nested_vmx_check_host_state(struct kvm_vcp= u *vcpu, CC(!kvm_vcpu_is_legal_cr3(vcpu, vmcs12->host_cr3))) return -EINVAL; =20 + if (CC(vmcs12->host_cr4 & X86_CR4_CET && !(vmcs12->host_cr0 & X86_CR0_WP)= )) + return -EINVAL; + if (CC(is_noncanonical_msr_address(vmcs12->host_ia32_sysenter_esp, vcpu))= || CC(is_noncanonical_msr_address(vmcs12->host_ia32_sysenter_eip, vcpu))) return -EINVAL; @@ -3225,6 +3228,9 @@ static int nested_vmx_check_guest_state(struct kvm_vc= pu *vcpu, CC(!nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))) return -EINVAL; =20 + if (CC(vmcs12->guest_cr4 & X86_CR4_CET && !(vmcs12->guest_cr0 & X86_CR0_W= P))) + return -EINVAL; + if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) && (CC(!kvm_dr7_valid(vmcs12->guest_dr7)) || CC(!vmx_is_valid_debugctl(vcpu, vmcs12->guest_ia32_debugctl, false))= )) --=20 2.47.3