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[86.139.30.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45deff68b43sm6975685e9.2.2025.09.09.02.12.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Sep 2025 02:12:29 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v2 3/8] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip Date: Tue, 9 Sep 2025 10:12:13 +0100 Message-ID: <20250909091225.128658-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250909091225.128658-1-biju.das.jz@bp.renesas.com> References: <20250909091225.128658-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G3E GPT IP is similar to the one found on RZ/G2L GPT, but there are some differences. The field width of prescalar on RZ/G3E is 4 whereas on RZ/G2L it is 3. Add rzg2l_gpt_info variable to handle this differences. The FIELD_PREP and FIELD_GET macro is giving compilation issue as the parameters are not build time constants. So added Non-constant mask variant of FIELD_GET() and FIELD_PREP(). Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v1->v2: * Collected tag. --- drivers/pwm/pwm-rzg2l-gpt.c | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index f0a8531457ca..bf989defa527 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -33,6 +33,19 @@ #include #include =20 +/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ +#define field_get(_mask, _reg) \ +({\ + typeof(_mask) (mask) =3D (_mask); \ + (((_reg) & (mask)) >> (ffs(mask) - 1)); \ +}) + +#define field_prep(_mask, _val) \ +({\ + typeof(_mask) (mask) =3D (_mask); \ + (((_val) << (ffs(mask) - 1)) & (mask)); \ +}) + #define RZG2L_GET_CH(hwpwm) ((hwpwm) / 2) #define RZG2L_GET_CH_OFFS(ch) (0x100 * (ch)) =20 @@ -46,7 +59,6 @@ =20 #define RZG2L_GTCR_CST BIT(0) #define RZG2L_GTCR_MD GENMASK(18, 16) -#define RZG2L_GTCR_TPCS GENMASK(26, 24) =20 #define RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE FIELD_PREP(RZG2L_GTCR_MD, 0) =20 @@ -77,9 +89,14 @@ #define RZG2L_MAX_SCALE_FACTOR 1024 #define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR) =20 +struct rzg2l_gpt_info { + u32 gtcr_tpcs_mask; +}; + struct rzg2l_gpt_chip { void __iomem *mmio; struct mutex lock; /* lock to protect shared channel resources */ + const struct rzg2l_gpt_info *info; unsigned long rate_khz; u32 period_ticks[RZG2L_MAX_HW_CHANNELS]; u32 channel_request_count[RZG2L_MAX_HW_CHANNELS]; @@ -317,7 +334,7 @@ static int rzg2l_gpt_read_waveform(struct pwm_chip *chi= p, =20 if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm)) { gtcr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch)); - wfhw->prescale =3D FIELD_GET(RZG2L_GTCR_TPCS, gtcr); + wfhw->prescale =3D field_get(rzg2l_gpt->info->gtcr_tpcs_mask, gtcr); wfhw->gtpr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch)); wfhw->gtccr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch)); if (wfhw->gtccr > wfhw->gtpr) @@ -354,8 +371,8 @@ static int rzg2l_gpt_write_waveform(struct pwm_chip *ch= ip, rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTUDDTYC(ch), RZG2L_GTUDDTYC_UP_COUNTIN= G); =20 /* Select count clock */ - rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS, - FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale)); + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), rzg2l_gpt->info->gtcr_tpcs_m= ask, + field_prep(rzg2l_gpt->info->gtcr_tpcs_mask, wfhw->prescale)); =20 /* Set period */ rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr); @@ -414,6 +431,8 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) if (IS_ERR(rzg2l_gpt->mmio)) return PTR_ERR(rzg2l_gpt->mmio); =20 + rzg2l_gpt->info =3D of_device_get_match_data(dev); + rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); if (IS_ERR(rstc)) return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\= n"); @@ -456,8 +475,12 @@ static int rzg2l_gpt_probe(struct platform_device *pde= v) return 0; } =20 +static const struct rzg2l_gpt_info rzg2l_data =3D { + .gtcr_tpcs_mask =3D GENMASK(26, 24), +}; + static const struct of_device_id rzg2l_gpt_of_table[] =3D { - { .compatible =3D "renesas,rzg2l-gpt", }, + { .compatible =3D "renesas,rzg2l-gpt", .data =3D &rzg2l_data }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table); --=20 2.43.0