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charset="utf-8" Add support for reading and configuring the OPP table in the GENI I2C driver. This enables setting the frequency based on device tree data, removing dependency on bootloader configuration. Signed-off-by: Manikanta Mylavarapu --- v3: Fix the format-specifier to correctly display the clock rate and change '&pdev->dev' to 'dev' as per suggestions from Andi Shyti. =20 drivers/i2c/busses/i2c-qcom-geni.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index ff2289b52c84..380581a3699c 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -779,11 +780,13 @@ static int setup_gpi_dma(struct geni_i2c_dev *gi2c) =20 static int geni_i2c_probe(struct platform_device *pdev) { - struct geni_i2c_dev *gi2c; + const struct geni_i2c_desc *desc =3D NULL; u32 proto, tx_depth, fifo_disable; - int ret; struct device *dev =3D &pdev->dev; - const struct geni_i2c_desc *desc =3D NULL; + unsigned long freq =3D ULONG_MAX; + struct geni_i2c_dev *gi2c; + struct dev_pm_opp *opp; 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charset="utf-8" Serial engines 2 and 3 on the IPQ5424 support I2C. The I2C instance operates on serial engine 2, designated as i2c0, and on serial engine 3, designated as i2c1. Add both the i2c0 and i2c1 nodes. Reviewed-by: Konrad Dybcio Signed-off-by: Manikanta Mylavarapu --- v3: Pick up R-b tag. arch/arm64/boot/dts/qcom/ipq5424.dtsi | 28 +++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index ef2b52f3597d..81a89e425c20 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -173,6 +173,14 @@ memory@80000000 { reg =3D <0x0 0x80000000 0x0 0x0>; }; =20 + i2c_opp_table_64mhz: opp-table-qup64mhz { + compatible =3D "operating-points-v2"; + + opp-64000000 { + opp-hz =3D /bits/ 64 <64000000>; + }; + }; + pmu-a55 { compatible =3D "arm,cortex-a55-pmu"; interrupts =3D ; @@ -525,6 +533,26 @@ uart1: serial@1a84000 { interrupts =3D ; }; =20 + i2c0: i2c@1a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x01a88000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_I2C0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + operating-points-v2 =3D <&i2c_opp_table_64mhz>; + status =3D "disabled"; + }; + + i2c1: i2c@1a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x01a8c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_I2C1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + operating-points-v2 =3D <&i2c_opp_table_64mhz>; + status =3D "disabled"; + }; + spi0: spi@1a90000 { compatible =3D "qcom,geni-spi"; reg =3D <0 0x01a90000 0 0x4000>; --=20 2.34.1