From nobody Fri Oct 3 00:00:55 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D32783019B1; Tue, 9 Sep 2025 06:21:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757398894; cv=none; b=eWWeW/xeV+O7uc9WNDELvfc0cNAbMCrkmOiS92RR3OUPgwjNhAhK5xunaNfPGGU4mMkvUGy4vQdItrMxz1QoCESUZkxiKKx6ZfDWsEMgoLLMoDhmn3NYNR1f03zpG2HNlgr0unQx/9F/WDYG9Iec9aQwz/UI2VfX8OKa67+tFYo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757398894; c=relaxed/simple; bh=Z0ytwrdU8Zy3z2M0PKSyDzd7L21tYMFmz7LhDS59cwE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L/SdGEg8/zWdl71Hnhj6qg2c0eZpiblW60oG23XhIvFy2FenzmpAb/lSijQ1Vtx/WuFSh8IgIa3GzgBqmdoncvNeVeyNSCj3UAD+ZCTU8uLVqoDW8T1UYg5twRGV6wWgQ0Rwp6mrsjUVCMgDfCaTJFzqdynnLQ+zq7/QIzNCedQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bZ8But7X; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bZ8But7X" Received: by smtp.kernel.org (Postfix) with ESMTPS id 64140C4CEF5; Tue, 9 Sep 2025 06:21:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757398894; bh=Z0ytwrdU8Zy3z2M0PKSyDzd7L21tYMFmz7LhDS59cwE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bZ8But7XpEdM+O/nEpWaE4EqqmQxWTBG0Zw9lfAoLKwMk+uW0b3UDzuayBjrjT3Dw GaAK3fqXvGGOGH1hxJ4nCuuNO3C1NBFflAU8LJx8ed0uFRC3zJJt5dn/M85cGu6ZGQ HFbf+GEaklaJqOkHhL4LedngS2tQMptp+68ejI+BNYXE6Y30H6+7oLm+4XcoqsVbjO Z4r9Yht3df+HdZ13rh6i5z+phXHbaJhFEKFu5ZVe4y3w5cSrQFghVQr8fCP1o0+GnB IgtiKhyE1MkZCMx5wrM6ogMdwSenCcnf4Mfzb+SdLAg5VyAcjBJo4qt7Okakj0S3yK hWzN8Qcsbzhyw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56B41CA0FED; Tue, 9 Sep 2025 06:21:34 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Tue, 09 Sep 2025 01:21:29 -0500 Subject: [PATCH v2 1/8] cpufreq: tegra186: add OPP support and set bandwidth Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-tegra186-icc-v2-1-09413724e781@gmail.com> References: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> In-Reply-To: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , "Rafael J. Wysocki" , Viresh Kumar , Krzysztof Kozlowski Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757398893; l=8394; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=NZJsduZw7/XAh0XqzH09l51I14O7mE+MWIT2CwMrZHU=; b=wpYKN2+155wE9rOglp8skrW+dF+DGagpC4ATWh1bDpEXMRmb7dscSkWfTgvLj2L3Vh4ML/2AT Mm/KZJxG939BhNPSmmqcslI+vKwxEurNYTC1xPXaxlqRYpyknxmKUSG X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add support to use OPP table from DT in Tegra186 cpufreq driver. Tegra SoC's receive the frequency lookup table (LUT) from BPMP-FW. Cross check the OPP's present in DT against the LUT from BPMP-FW and enable only those DT OPP's which are present in LUT also. The OPP table in DT has CPU Frequency to bandwidth mapping where the bandwidth value is per MC channel. DRAM bandwidth depends on the number of MC channels which can vary as per the boot configuration. This per channel bandwidth from OPP table will be later converted by MC driver to final bandwidth value by multiplying with number of channels before being handled in the EMC driver. If OPP table is not present in DT, then use the LUT from BPMP-FW directy as the CPU frequency table and not do the DRAM frequency scaling which is same as the current behavior. Signed-off-by: Aaron Kling --- drivers/cpufreq/tegra186-cpufreq.c | 152 +++++++++++++++++++++++++++++++++= ++-- 1 file changed, 145 insertions(+), 7 deletions(-) diff --git a/drivers/cpufreq/tegra186-cpufreq.c b/drivers/cpufreq/tegra186-= cpufreq.c index bd94beebc4cc2fe6870e13ca55343cedb9729e99..cb7a033e8ae6e81b18bbf3bc636= 32c631e99129b 100644 --- a/drivers/cpufreq/tegra186-cpufreq.c +++ b/drivers/cpufreq/tegra186-cpufreq.c @@ -8,6 +8,7 @@ #include #include #include +#include =20 #include #include @@ -58,7 +59,7 @@ static const struct tegra186_cpufreq_cpu tegra186_cpus[] = =3D { }; =20 struct tegra186_cpufreq_cluster { - struct cpufreq_frequency_table *table; + struct cpufreq_frequency_table *bpmp_lut; u32 ref_clk_khz; u32 div; }; @@ -66,16 +67,121 @@ struct tegra186_cpufreq_cluster { struct tegra186_cpufreq_data { void __iomem *regs; const struct tegra186_cpufreq_cpu *cpus; + bool icc_dram_bw_scaling; struct tegra186_cpufreq_cluster clusters[]; }; =20 +static int tegra_cpufreq_set_bw(struct cpufreq_policy *policy, unsigned lo= ng freq_khz) +{ + struct tegra186_cpufreq_data *data =3D cpufreq_get_driver_data(); + struct dev_pm_opp *opp __free(put_opp); + struct device *dev; + int ret; + + dev =3D get_cpu_device(policy->cpu); + if (!dev) + return -ENODEV; + + opp =3D dev_pm_opp_find_freq_exact(dev, freq_khz * HZ_PER_KHZ, true); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + ret =3D dev_pm_opp_set_opp(dev, opp); + if (ret) + data->icc_dram_bw_scaling =3D false; + + return ret; +} + +static int tegra_cpufreq_init_cpufreq_table(struct cpufreq_policy *policy, + struct cpufreq_frequency_table *bpmp_lut, + struct cpufreq_frequency_table **opp_table) +{ + struct tegra186_cpufreq_data *data =3D cpufreq_get_driver_data(); + struct cpufreq_frequency_table *freq_table =3D NULL; + struct cpufreq_frequency_table *pos; + struct device *cpu_dev; + unsigned long rate; + int ret, max_opps; + int j =3D 0; + + cpu_dev =3D get_cpu_device(policy->cpu); + if (!cpu_dev) { + pr_err("%s: failed to get cpu%d device\n", __func__, policy->cpu); + return -ENODEV; + } + + /* Initialize OPP table mentioned in operating-points-v2 property in DT */ + ret =3D dev_pm_opp_of_add_table_indexed(cpu_dev, 0); + if (ret) { + dev_err(cpu_dev, "Invalid or empty opp table in device tree\n"); + data->icc_dram_bw_scaling =3D false; + return ret; + } + + max_opps =3D dev_pm_opp_get_opp_count(cpu_dev); + if (max_opps <=3D 0) { + dev_err(cpu_dev, "Failed to add OPPs\n"); + return max_opps; + } + + /* Disable all opps and cross-validate against LUT later */ + for (rate =3D 0; ; rate++) { + struct dev_pm_opp *opp __free(put_opp); + + opp =3D dev_pm_opp_find_freq_ceil(cpu_dev, &rate); + if (IS_ERR(opp)) + break; + + dev_pm_opp_disable(cpu_dev, rate); + } + + freq_table =3D kcalloc((max_opps + 1), sizeof(*freq_table), GFP_KERNEL); + if (!freq_table) + return -ENOMEM; + + /* + * Cross check the frequencies from BPMP-FW LUT against the OPP's present= in DT. + * Enable only those DT OPP's which are present in LUT also. + */ + cpufreq_for_each_valid_entry(pos, bpmp_lut) { + struct dev_pm_opp *opp __free(put_opp); + + opp =3D dev_pm_opp_find_freq_exact(cpu_dev, pos->frequency * HZ_PER_KHZ,= false); + if (IS_ERR(opp)) + continue; + + ret =3D dev_pm_opp_enable(cpu_dev, pos->frequency * HZ_PER_KHZ); + if (ret < 0) + return ret; + + freq_table[j].driver_data =3D pos->driver_data; + freq_table[j].frequency =3D pos->frequency; + j++; + } + + freq_table[j].driver_data =3D pos->driver_data; + freq_table[j].frequency =3D CPUFREQ_TABLE_END; + + *opp_table =3D &freq_table[0]; + + dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); + + /* Prime interconnect data */ + tegra_cpufreq_set_bw(policy, freq_table[j - 1].frequency); + + return ret; +} + static int tegra186_cpufreq_init(struct cpufreq_policy *policy) { struct tegra186_cpufreq_data *data =3D cpufreq_get_driver_data(); unsigned int cluster =3D data->cpus[policy->cpu].bpmp_cluster_id; + struct cpufreq_frequency_table *freq_table; + struct cpufreq_frequency_table *bpmp_lut; u32 cpu; + int ret; =20 - policy->freq_table =3D data->clusters[cluster].table; policy->cpuinfo.transition_latency =3D 300 * 1000; policy->driver_data =3D NULL; =20 @@ -85,6 +191,20 @@ static int tegra186_cpufreq_init(struct cpufreq_policy = *policy) cpumask_set_cpu(cpu, policy->cpus); } =20 + bpmp_lut =3D data->clusters[cluster].bpmp_lut; + + if (data->icc_dram_bw_scaling) { + ret =3D tegra_cpufreq_init_cpufreq_table(policy, bpmp_lut, &freq_table); + if (!ret) { + policy->freq_table =3D freq_table; + return 0; + } + } + + data->icc_dram_bw_scaling =3D false; + policy->freq_table =3D bpmp_lut; + pr_info("OPP tables missing from DT, EMC frequency scaling disabled\n"); + return 0; } =20 @@ -102,6 +222,10 @@ static int tegra186_cpufreq_set_target(struct cpufreq_= policy *policy, writel(edvd_val, data->regs + edvd_offset); } =20 + if (data->icc_dram_bw_scaling) + tegra_cpufreq_set_bw(policy, tbl->frequency); + + return 0; } =20 @@ -136,7 +260,7 @@ static struct cpufreq_driver tegra186_cpufreq_driver = =3D { .init =3D tegra186_cpufreq_init, }; =20 -static struct cpufreq_frequency_table *init_vhint_table( +static struct cpufreq_frequency_table *tegra_cpufreq_bpmp_read_lut( struct platform_device *pdev, struct tegra_bpmp *bpmp, struct tegra186_cpufreq_cluster *cluster, unsigned int cluster_id, int *num_rates) @@ -231,6 +355,7 @@ static int tegra186_cpufreq_probe(struct platform_devic= e *pdev) { struct tegra186_cpufreq_data *data; struct tegra_bpmp *bpmp; + struct device *cpu_dev; unsigned int i =3D 0, err, edvd_offset; int num_rates =3D 0; u32 edvd_val, cpu; @@ -256,9 +381,9 @@ static int tegra186_cpufreq_probe(struct platform_devic= e *pdev) for (i =3D 0; i < TEGRA186_NUM_CLUSTERS; i++) { struct tegra186_cpufreq_cluster *cluster =3D &data->clusters[i]; =20 - cluster->table =3D init_vhint_table(pdev, bpmp, cluster, i, &num_rates); - if (IS_ERR(cluster->table)) { - err =3D PTR_ERR(cluster->table); + cluster->bpmp_lut =3D tegra_cpufreq_bpmp_read_lut(pdev, bpmp, cluster, i= , &num_rates); + if (IS_ERR(cluster->bpmp_lut)) { + err =3D PTR_ERR(cluster->bpmp_lut); goto put_bpmp; } else if (!num_rates) { err =3D -EINVAL; @@ -267,7 +392,7 @@ static int tegra186_cpufreq_probe(struct platform_devic= e *pdev) =20 for (cpu =3D 0; cpu < ARRAY_SIZE(tegra186_cpus); cpu++) { if (data->cpus[cpu].bpmp_cluster_id =3D=3D i) { - edvd_val =3D cluster->table[num_rates - 1].driver_data; + edvd_val =3D cluster->bpmp_lut[num_rates - 1].driver_data; edvd_offset =3D data->cpus[cpu].edvd_offset; writel(edvd_val, data->regs + edvd_offset); } @@ -276,6 +401,19 @@ static int tegra186_cpufreq_probe(struct platform_devi= ce *pdev) =20 tegra186_cpufreq_driver.driver_data =3D data; =20 + /* Check for optional OPPv2 and interconnect paths on CPU0 to enable ICC = scaling */ + cpu_dev =3D get_cpu_device(0); + if (!cpu_dev) { + err =3D -EPROBE_DEFER; + goto put_bpmp; + } + + if (dev_pm_opp_of_get_opp_desc_node(cpu_dev)) { + err =3D dev_pm_opp_of_find_icc_paths(cpu_dev, NULL); + if (!err) + data->icc_dram_bw_scaling =3D true; + } + err =3D cpufreq_register_driver(&tegra186_cpufreq_driver); =20 put_bpmp: --=20 2.50.1 From nobody Fri Oct 3 00:00:55 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D31CF3019B0; Tue, 9 Sep 2025 06:21:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-tegra186-icc-v2-2-09413724e781@gmail.com> References: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> In-Reply-To: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , "Rafael J. Wysocki" , Viresh Kumar , Krzysztof Kozlowski Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757398893; l=816; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=68sWGSUz7jYX5/edcY0jO4D+Q2zCiMMqrwxxXnLD9fA=; b=mvAyvsFOy2n0FwXJSnneawdexs0XZv6RZZeag9Qn7pJTitpp2x2xwnAt8idRCMpnxX4A4yavH JMQEsNyKQWvCKJz5WgX7etI0kAjslKURC3a/kEpL8bc0FOmYKj2une6 X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add ICC IDs for dummy software clients representing CCPLEX clusters. Signed-off-by: Aaron Kling --- include/dt-bindings/memory/tegra186-mc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/memory/tegra186-mc.h b/include/dt-bindings= /memory/tegra186-mc.h index 82a1e27f73576212bc227c74adff28c5f33c6bb1..8abbc26f3123aad2dffaec6be21= f99f8de1ccf89 100644 --- a/include/dt-bindings/memory/tegra186-mc.h +++ b/include/dt-bindings/memory/tegra186-mc.h @@ -247,4 +247,8 @@ #define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2 #define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3 =20 +/* ICC ID's for dummy MC clients used to represent CPU Clusters */ +#define TEGRA_ICC_MC_CPU_CLUSTER0 1003 +#define TEGRA_ICC_MC_CPU_CLUSTER1 1004 + #endif --=20 2.50.1 From nobody Fri Oct 3 00:00:55 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D312F2D8DA6; Tue, 9 Sep 2025 06:21:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757398894; cv=none; b=Ei/1dNjJ1bUlwkpADex7z1W3NtduZAbzsqPbEqn4l3nhPVv56Vz3ja9DzW2mRejvSoI5Gca1AZSUWP9NY/Nijtzq8dEtLD6QtQU2Noqz106z4jaUSGy06co0P94MfAkFSWZiOuzLWgZIn1Az4Eo6/oKjjQ0k2h33bbf36qhJnYA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757398894; c=relaxed/simple; bh=lTzEzt7B30YSrqMuZRySEr37koys5vP4NQ0cnXVdvZg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VV+7F86gGq+RZ1+S52FoyfcyQ5dDdKF+/w0VhAEOpe0zxkKKiNk+/9hmza6+I8r9Lcd8rPFIZQdifnUpDi4lvexG1Js5HQGOtWflD+POjWke7T5d7W0nmW/nONv8ocdMNZm63fPq9F4XZ6AqP3V8X8kEBYmp/Qz8+zKa0Gb0quY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lfzlJW6U; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lfzlJW6U" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7BC26C4CEFD; Tue, 9 Sep 2025 06:21:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757398894; bh=lTzEzt7B30YSrqMuZRySEr37koys5vP4NQ0cnXVdvZg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lfzlJW6UsAknGSO0If68NLKDr6YjhxTyzBBm5eG9Y19bVAhjr70wGnngseQ+7wvGE dqd0c63VEiGI7LBvLpLh8MzOpzl5jg9POvaidFrth45+CMVvhx0wlf7tlKHa7H1vTU UvZ+BU5fnPhb5jcj2M2LbelxtCxkMdnHd387SNCPF5t5nPXt82foU1LFkO7Adla561 zssH2ALKXZKzouf15M2/MqMQrSsTikhUuXlCSx/INXbdWmb6cwMk6ZLbsRmNjx5W0N ddjAaq7gUi65Iy1i/NYgvboVkyvgagJVacm9CQhweY0iE6r40cHePEg2KoPqA1zaij XcP7rsN8EUxCg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71AB7CAC58B; Tue, 9 Sep 2025 06:21:34 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Tue, 09 Sep 2025 01:21:31 -0500 Subject: [PATCH v2 3/8] dt-bindings: memory: tegra194-mc: Add dummy client IDs for Tegra194 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-tegra186-icc-v2-3-09413724e781@gmail.com> References: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> In-Reply-To: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , "Rafael J. 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Signed-off-by: Aaron Kling --- include/dt-bindings/memory/tegra194-mc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/memory/tegra194-mc.h b/include/dt-bindings= /memory/tegra194-mc.h index eed48b746bc94072a6bd0af7f344dbb6f6618859..a7d97a1a470cd3cfb18c7ef45c4= 21426ea3c7abf 100644 --- a/include/dt-bindings/memory/tegra194-mc.h +++ b/include/dt-bindings/memory/tegra194-mc.h @@ -407,4 +407,10 @@ /* MSS internal memqual MIU6 write clients */ #define TEGRA194_MEMORY_CLIENT_MIU6W 0xff =20 +/* ICC ID's for dummy MC clients used to represent CPU Clusters */ +#define TEGRA_ICC_MC_CPU_CLUSTER0 1003 +#define TEGRA_ICC_MC_CPU_CLUSTER1 1004 +#define TEGRA_ICC_MC_CPU_CLUSTER2 1005 +#define TEGRA_ICC_MC_CPU_CLUSTER3 1006 + #endif --=20 2.50.1 From nobody Fri Oct 3 00:00:55 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F422A3019CE; Tue, 9 Sep 2025 06:21:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757398895; cv=none; b=kxRLiRjmAgyEJSZOsjYWu3O4g5rRizdgzRHPlpZRO+258zvqCOKzylmtIkgIesWS+N4v3Tri4KymfZgdDQUFiJXrA7aI8KyO3kmWukttWuZq7qZ7KvowI6RNfUhfx+EfA4HgtuevCogJUkZBOAsgn+Arh7mBmdJZ3dbAZjkwL48= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757398895; c=relaxed/simple; bh=BKe3rw3YctsLXqkrtMOW6fQhzekowbwuSEaXRAbhv5A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=J/NS3rk9gJpNAjybYj0dX7y6on07TC8rEQZ2JpD433xJjOQFKfNkSlDIRhq/6usAdPGpyf6zDdo7NS1rKFF0wI7s8d6U6R5gkpul0R3a3W+EmQTwJoAO2E1c7KH4eEqGqpDIrj0tb90kIP3USeyAnfdHvVToFpKui1AphQMFCqQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NwEDmB7z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NwEDmB7z" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8AA2CC4CEFC; Tue, 9 Sep 2025 06:21:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757398894; bh=BKe3rw3YctsLXqkrtMOW6fQhzekowbwuSEaXRAbhv5A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NwEDmB7zcmc2QgvSD6A6qc2f7u0+i5Z81+s2OSVMolYjIBd9tjIzhIC1M+Q52Pbf6 2nTsWAw948753i+Jw2o5LhAmEf8SL0GC1WOwypRo60RRewgGGAUQUFCnxp6q3tcou6 r4lxn46f93mbAz2Kngpt9P5RCVbmBfhsCsKTZjzqxGXn+Nm2SH6kAI5A26W8ZnqZ1n CvHzA0/tbsE1bpXsi532atZ8J6R9xkMHh5hlDfNxsp1fgznqKNn/N4NSiTMwlb/Mde VHiObO5BeGkldb+KiWkawInHJorfTgZAcLh6jOnaQGqc+UskznFt1nr0UafqEdeGpc nrWShxyjTKXvg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80EB1CAC587; Tue, 9 Sep 2025 06:21:34 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Tue, 09 Sep 2025 01:21:32 -0500 Subject: [PATCH v2 4/8] memory: tegra186-emc: Support non-bpmp icc scaling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-tegra186-icc-v2-4-09413724e781@gmail.com> References: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> In-Reply-To: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , "Rafael J. Wysocki" , Viresh Kumar , Krzysztof Kozlowski Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757398893; l=5749; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=nugNxNxYRHTU1Ah7DRFanUlqmkAHHZfFkwW/lWONkrk=; b=UadDwcZLXXoMx0yghu0dODBC3ueT0DxULOvz3Bqp11m0TEcHZxc1eBEWl4sonh8p1lcBgKkPI RSIMdXhFJ43D4+TLGM/0DOKKu+T3A2ugLYn2I47lPa1t0YBrsOJJsOV X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling This adds support for dynamic frequency scaling of external memory on devices with bpmp firmware that does not support bwmgr. Signed-off-by: Aaron Kling --- drivers/memory/tegra/tegra186-emc.c | 132 ++++++++++++++++++++++++++++++++= +++- 1 file changed, 130 insertions(+), 2 deletions(-) diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/teg= ra186-emc.c index d6cd90c7ad5380a9ff9052a60f62c9bcc4fdac5f..1711f2e85ad07692feb8f6f14c8= c2b10ea42fde5 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -18,6 +18,17 @@ struct tegra186_emc_dvfs { unsigned long rate; }; =20 +enum emc_rate_request_type { + EMC_RATE_DEBUG, + EMC_RATE_ICC, + EMC_RATE_TYPE_MAX, +}; + +struct emc_rate_request { + unsigned long min_rate; + unsigned long max_rate; +}; + struct tegra186_emc { struct tegra_bpmp *bpmp; struct device *dev; @@ -33,8 +44,90 @@ struct tegra186_emc { } debugfs; =20 struct icc_provider provider; + + /* + * There are multiple sources in the EMC driver which could request + * a min/max clock rate, these rates are contained in this array. + */ + struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX]; + + /* protect shared rate-change code path */ + struct mutex rate_lock; }; =20 +static void tegra_emc_rate_requests_init(struct tegra186_emc *emc) +{ + unsigned int i; + + for (i =3D 0; i < EMC_RATE_TYPE_MAX; i++) { + emc->requested_rate[i].min_rate =3D 0; + emc->requested_rate[i].max_rate =3D ULONG_MAX; + } +} + +static int emc_request_rate(struct tegra186_emc *emc, + unsigned long new_min_rate, + unsigned long new_max_rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req =3D emc->requested_rate; + unsigned long min_rate =3D 0, max_rate =3D ULONG_MAX; + unsigned int i; + int err; + + /* select minimum and maximum rates among the requested rates */ + for (i =3D 0; i < EMC_RATE_TYPE_MAX; i++, req++) { + if (i =3D=3D type) { + min_rate =3D max(new_min_rate, min_rate); + max_rate =3D min(new_max_rate, max_rate); + } else { + min_rate =3D max(req->min_rate, min_rate); + max_rate =3D min(req->max_rate, max_rate); + } + } + + if (min_rate > max_rate) { + dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", + __func__, type, min_rate, max_rate); + return -ERANGE; + } + + err =3D clk_set_rate(emc->clk, min_rate); + if (err) + return err; + + emc->requested_rate[type].min_rate =3D new_min_rate; + emc->requested_rate[type].max_rate =3D new_max_rate; + + return 0; +} + +static int emc_set_min_rate(struct tegra186_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req =3D &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret =3D emc_request_rate(emc, rate, req->max_rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + +static int emc_set_max_rate(struct tegra186_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req =3D &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret =3D emc_request_rate(emc, req->min_rate, rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + /* * debugfs interface * @@ -107,7 +200,7 @@ static int tegra186_emc_debug_min_rate_set(void *data, = u64 rate) if (!tegra186_emc_validate_rate(emc, rate)) return -EINVAL; =20 - err =3D clk_set_min_rate(emc->clk, rate); + err =3D emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; =20 @@ -137,7 +230,7 @@ static int tegra186_emc_debug_max_rate_set(void *data, = u64 rate) if (!tegra186_emc_validate_rate(emc, rate)) return -EINVAL; =20 - err =3D clk_set_max_rate(emc->clk, rate); + err =3D emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; =20 @@ -217,6 +310,12 @@ static int tegra186_emc_get_emc_dvfs_latency(struct te= gra186_emc *emc) return 0; } =20 +static inline struct tegra186_emc * +to_tegra186_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra186_emc, provider); +} + /* * tegra_emc_icc_set_bw() - Set BW api for EMC provider * @src: ICC node for External Memory Controller (EMC) @@ -227,6 +326,33 @@ static int tegra186_emc_get_emc_dvfs_latency(struct te= gra186_emc *emc) */ static int tegra_emc_icc_set_bw(struct icc_node *src, struct icc_node *dst) { + struct tegra186_emc *emc =3D to_tegra186_emc_provider(dst->provider); + struct tegra_mc *mc =3D dev_get_drvdata(emc->dev->parent); + unsigned long long peak_bw =3D icc_units_to_bps(dst->peak_bw); + unsigned long long avg_bw =3D icc_units_to_bps(dst->avg_bw); + unsigned long long rate =3D max(avg_bw, peak_bw); + const unsigned int ddr =3D 2; + int err; + + /* + * Do nothing here if bwmgr is supported in BPMP-FW. BPMP-FW sets the fin= al + * Freq based on the passed values. + */ + if (mc->bwmgr_mrq_supported) + return 0; + + /* + * Tegra186 EMC runs on a clock rate of SDRAM bus. This means that + * EMC clock rate is twice smaller than the peak data rate because + * data is sampled on both EMC clock edges. + */ + do_div(rate, ddr); + rate =3D min_t(u64, rate, U32_MAX); + + err =3D emc_set_min_rate(emc, rate, EMC_RATE_ICC); + if (err) + return err; + return 0; } =20 @@ -334,6 +460,8 @@ static int tegra186_emc_probe(struct platform_device *p= dev) platform_set_drvdata(pdev, emc); emc->dev =3D &pdev->dev; =20 + tegra_emc_rate_requests_init(emc); + if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_EMC_DVFS_LATENCY)) { err =3D tegra186_emc_get_emc_dvfs_latency(emc); if (err) --=20 2.50.1 From nobody Fri Oct 3 00:00:55 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C4B4303A0D; Tue, 9 Sep 2025 06:21:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757398895; cv=none; b=B+/zBq6l3Rjq0FiE0LEkDvkuc/x36MeKFVFc5bXWUeel+xdf8BL8auybifqABnAkzu3I5MnUW3CEl9uwuVg1Sl4tYdUlwZde5v5USc+nKHweImyilBPhhYQ8FQQSX/9UvpTqX1Ekp61q5uN3MzPLrWWjv3oJzVL8CKN9oXDddDM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757398895; c=relaxed/simple; bh=r3pUzrkcWVNCbofMp9WGG3qQXL4dcWz8Z9kujWaLZG4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L5RU3uirMZdBx3kanWNK075mkZQBj55ZzWGtRbMTglCJHq1LIJX3he5Xdh1NQIbV23nBJVDpuMP+L19dK36M+DoYJVkzkv4s0/L2fVbhUo2XJ+HWN6+tZuqDHJiY1WCG0oYMZB0JUkexDYRWgZcE+y9czX3swru3u2Z0j/XARSk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=euR2njjp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="euR2njjp" Received: by smtp.kernel.org (Postfix) with ESMTPS id 974F0C113D0; Tue, 9 Sep 2025 06:21:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757398894; bh=r3pUzrkcWVNCbofMp9WGG3qQXL4dcWz8Z9kujWaLZG4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=euR2njjpCL0K0XlUx3Rmr/abZiMy51sDC1mZGY2obhsxW0FjehSpDpG81BW5szN/T K9kfHA11tdEqWiaPgW/IEANT6fL34D9tWOOQsaJG0PSwvfAgP0R4lhSr6GeeDkyDWx nCR8rINe612wqs8ua8my0KXMRufL8Mxm/FOhldIk08hftEEDdtYhJsBBYInluJjdq2 LUTKTJ1awGYR2MDE45tCp8cJBOVUZe4S4mpcTzcgNHVbfoU7WQqhyqreMQoZ8TP4hw pHA9z4hv+UFmklEvjhRyh58tvXJ0bNkHVbcI5Zc1RjjMu/we7RNL0ICoS2KKt+/gbh 37NaabbQArh6Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F73CCAC586; Tue, 9 Sep 2025 06:21:34 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Tue, 09 Sep 2025 01:21:33 -0500 Subject: [PATCH v2 5/8] memory: tegra186: Support icc scaling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-tegra186-icc-v2-5-09413724e781@gmail.com> References: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> In-Reply-To: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , "Rafael J. Wysocki" , Viresh Kumar , Krzysztof Kozlowski Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757398893; l=2383; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=oxIJSUp3ozTyoLouc+lEW3YE1MQYQJbWMy5w5OZ/8c0=; b=BwsysDaa1RMo3/YlfQyUuSonmsPj+xyonfnb0VuVt3vBGaitMYME5DzkxvLRz3uazZPi+2acp 7peacNrmcI2BcYeaAXf+Yd4hp8trorjCM943TaLfuSLpUSnHGsgXI6Y X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add Interconnect framework support to dynamically set the DRAM bandwidth from different clients. The MC driver is added as an ICC provider and the EMC driver is already a provider. Signed-off-by: Aaron Kling --- drivers/memory/tegra/tegra186.c | 48 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 48 insertions(+) diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra18= 6.c index aee11457bf8e032637d1772affb87da0cac68494..1384164f624af5d4aaccedc8444= 3d203ba3db2c6 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -899,9 +899,56 @@ static const struct tegra_mc_client tegra186_mc_client= s[] =3D { .security =3D 0x51c, }, }, + }, { + .id =3D TEGRA_ICC_MC_CPU_CLUSTER0, + .name =3D "sw_cluster0", + .type =3D TEGRA_ICC_NISO, + }, { + .id =3D TEGRA_ICC_MC_CPU_CLUSTER1, + .name =3D "sw_cluster1", + .type =3D TEGRA_ICC_NISO, }, }; =20 +static int tegra186_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + /* TODO: program PTSA */ + return 0; +} + +static int tegra186_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 a= vg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + struct icc_provider *p =3D node->provider; + struct tegra_mc *mc =3D icc_provider_to_tegra_mc(p); + + if (node->id =3D=3D TEGRA_ICC_MC_CPU_CLUSTER0 || + node->id =3D=3D TEGRA_ICC_MC_CPU_CLUSTER1) { + if (mc) + peak_bw =3D peak_bw * mc->num_channels; + } + + *agg_avg +=3D avg_bw; + *agg_peak =3D max(*agg_peak, peak_bw); + + return 0; +} + +static int tegra186_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u3= 2 *peak) +{ + *avg =3D 0; + *peak =3D 0; + + return 0; +} + +static const struct tegra_mc_icc_ops tegra186_mc_icc_ops =3D { + .xlate =3D tegra_mc_icc_xlate, + .aggregate =3D tegra186_mc_icc_aggregate, + .get_bw =3D tegra186_mc_icc_get_init_bw, + .set =3D tegra186_mc_icc_set, +}; + const struct tegra_mc_soc tegra186_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra186_mc_clients), .clients =3D tegra186_mc_clients, @@ -912,6 +959,7 @@ const struct tegra_mc_soc tegra186_mc_soc =3D { MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .ops =3D &tegra186_mc_ops, + .icc_ops =3D &tegra186_mc_icc_ops, .ch_intmask =3D 0x0000000f, .global_intstatus_channel_shift =3D 0, }; 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Tue, 9 Sep 2025 06:21:34 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Tue, 09 Sep 2025 01:21:34 -0500 Subject: [PATCH v2 6/8] memory: tegra194: Support icc scaling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-tegra186-icc-v2-6-09413724e781@gmail.com> References: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> In-Reply-To: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , "Rafael J. Wysocki" , Viresh Kumar , Krzysztof Kozlowski Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757398893; l=2712; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=3MNvz35Who37oCQFtQGQqKBjr1XzOGhEfbsNxRdRmLQ=; b=9TUPlrXy5MPMzLxaXGR6HI6g2rU8jq8oKe9JYY1cIBcxVHQ7yQRRaNk6U8TEAYstVhrFftoVN 57mbONCg6c6CJw5BWE1SXweNkq93EGbdUE/io+qeNOudktpXot+mIVp X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add Interconnect framework support to dynamically set the DRAM bandwidth from different clients. The MC driver is added as an ICC provider and the EMC driver is already a provider. Signed-off-by: Aaron Kling --- drivers/memory/tegra/tegra194.c | 59 +++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra19= 4.c index 26035ac3a1eb51a3d8ce3830427b4412b48baf3c..e478587586e7f01afd41ff74d26= a9a3f1d881347 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1340,9 +1340,66 @@ static const struct tegra_mc_client tegra194_mc_clie= nts[] =3D { .security =3D 0x7fc, }, }, + }, { + .id =3D TEGRA_ICC_MC_CPU_CLUSTER0, + .name =3D "sw_cluster0", + .type =3D TEGRA_ICC_NISO, + }, { + .id =3D TEGRA_ICC_MC_CPU_CLUSTER1, + .name =3D "sw_cluster1", + .type =3D TEGRA_ICC_NISO, + }, { + .id =3D TEGRA_ICC_MC_CPU_CLUSTER2, + .name =3D "sw_cluster2", + .type =3D TEGRA_ICC_NISO, + }, { + .id =3D TEGRA_ICC_MC_CPU_CLUSTER3, + .name =3D "sw_cluster3", + .type =3D TEGRA_ICC_NISO, }, }; =20 +static int tegra194_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + /* TODO: program PTSA */ + return 0; +} + +static int tegra194_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 a= vg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + struct icc_provider *p =3D node->provider; + struct tegra_mc *mc =3D icc_provider_to_tegra_mc(p); + + if (node->id =3D=3D TEGRA_ICC_MC_CPU_CLUSTER0 || + node->id =3D=3D TEGRA_ICC_MC_CPU_CLUSTER1 || + node->id =3D=3D TEGRA_ICC_MC_CPU_CLUSTER2 || + node->id =3D=3D TEGRA_ICC_MC_CPU_CLUSTER3) { + if (mc) + peak_bw =3D peak_bw * mc->num_channels; + } + + *agg_avg +=3D avg_bw; + *agg_peak =3D max(*agg_peak, peak_bw); + + return 0; +} + +static int tegra194_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u3= 2 *peak) +{ + *avg =3D 0; + *peak =3D 0; + + return 0; +} + +static const struct tegra_mc_icc_ops tegra194_mc_icc_ops =3D { + .xlate =3D tegra_mc_icc_xlate, + .aggregate =3D tegra194_mc_icc_aggregate, + .get_bw =3D tegra194_mc_icc_get_init_bw, + .set =3D tegra194_mc_icc_set, +}; + const struct tegra_mc_soc tegra194_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra194_mc_clients), .clients =3D tegra194_mc_clients, @@ -1355,7 +1412,7 @@ const struct tegra_mc_soc tegra194_mc_soc =3D { MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .has_addr_hi_reg =3D true, .ops =3D &tegra186_mc_ops, - .icc_ops =3D &tegra_mc_icc_ops, + .icc_ops =3D &tegra194_mc_icc_ops, .ch_intmask =3D 0x00000f00, .global_intstatus_channel_shift =3D 8, }; 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Tue, 9 Sep 2025 06:21:34 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Tue, 09 Sep 2025 01:21:35 -0500 Subject: [PATCH v2 7/8] arm64: tegra: Add CPU OPP tables for Tegra186 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-tegra186-icc-v2-7-09413724e781@gmail.com> References: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> In-Reply-To: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , "Rafael J. Wysocki" , Viresh Kumar , Krzysztof Kozlowski Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757398893; l=9142; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=uZssU7heZXFbFMQlclW4XJXqxgp1LYUFan3iXKZGfg4=; b=QOq9Zgi2/T7xFuJ+D0DnP09EbkrRocXBH6KVeWk744qYlO8ThdXt414mNA025fl+bGNDyLD/W aZq+hfbaI3pAzNvBxgpIGxPViOCql2GI1YS0XCl4wuzWdpmd/nztv8r X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add OPP table and interconnects property to scale DDR frequency with CPU frequency for better performance. Each operating point entry of the OPP table has CPU freq to per MC channel bandwidth mapping. One table is added for each cluster because the different cpu types have different scaling curves. Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 317 +++++++++++++++++++++++++++= ++++ 1 file changed, 317 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts= /nvidia/tegra186.dtsi index 5778c93af3e6e72f5f14a9fcee1e7abf80d2d2c5..d3f6a938a9b019a043ce2de7ec1= 7bd00155b3eb2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1943,6 +1943,8 @@ cpus { denver_0: cpu@0 { compatible =3D "nvidia,tegra186-denver"; device_type =3D "cpu"; + operating-points-v2 =3D <&dnv_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; i-cache-size =3D <0x20000>; i-cache-line-size =3D <64>; i-cache-sets =3D <512>; @@ -1956,6 +1958,8 @@ denver_0: cpu@0 { denver_1: cpu@1 { compatible =3D "nvidia,tegra186-denver"; device_type =3D "cpu"; + operating-points-v2 =3D <&dnv_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; i-cache-size =3D <0x20000>; i-cache-line-size =3D <64>; i-cache-sets =3D <512>; @@ -1969,6 +1973,8 @@ denver_1: cpu@1 { ca57_0: cpu@2 { compatible =3D "arm,cortex-a57"; device_type =3D "cpu"; + operating-points-v2 =3D <&a57_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; i-cache-size =3D <0xC000>; i-cache-line-size =3D <64>; i-cache-sets =3D <256>; @@ -1982,6 +1988,8 @@ ca57_0: cpu@2 { ca57_1: cpu@3 { compatible =3D "arm,cortex-a57"; device_type =3D "cpu"; + operating-points-v2 =3D <&a57_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; i-cache-size =3D <0xC000>; i-cache-line-size =3D <64>; i-cache-sets =3D <256>; @@ -1995,6 +2003,8 @@ ca57_1: cpu@3 { ca57_2: cpu@4 { compatible =3D "arm,cortex-a57"; device_type =3D "cpu"; + operating-points-v2 =3D <&a57_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; i-cache-size =3D <0xC000>; i-cache-line-size =3D <64>; i-cache-sets =3D <256>; @@ -2008,6 +2018,8 @@ ca57_2: cpu@4 { ca57_3: cpu@5 { compatible =3D "arm,cortex-a57"; device_type =3D "cpu"; + operating-points-v2 =3D <&a57_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; i-cache-size =3D <0xC000>; i-cache-line-size =3D <64>; i-cache-sets =3D <256>; @@ -2182,4 +2194,309 @@ timer { interrupt-parent =3D <&gic>; always-on; }; + + dnv_opp_tbl: opp-table-cluster0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1036800000 { + opp-hz =3D /bits/ 64 <1036800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1075200000 { + opp-hz =3D /bits/ 64 <1075200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1152000000 { + opp-hz =3D /bits/ 64 <1152000000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1190400000 { + opp-hz =3D /bits/ 64 <1190400000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1267200000 { + opp-hz =3D /bits/ 64 <1267200000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1305600000 { + opp-hz =3D /bits/ 64 <1305600000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1382400000 { + opp-hz =3D /bits/ 64 <1382400000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1420800000 { + opp-hz =3D /bits/ 64 <1420800000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1459200000 { + opp-hz =3D /bits/ 64 <1459200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1497600000 { + opp-hz =3D /bits/ 64 <1497600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1536000000 { + opp-hz =3D /bits/ 64 <1536000000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1574400000 { + opp-hz =3D /bits/ 64 <1574400000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1612800000 { + opp-hz =3D /bits/ 64 <1612800000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1689600000 { + opp-hz =3D /bits/ 64 <1689600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1728000000 { + opp-hz =3D /bits/ 64 <1728000000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1766400000 { + opp-hz =3D /bits/ 64 <1766400000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1804800000 { + opp-hz =3D /bits/ 64 <1804800000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1843200000 { + opp-hz =3D /bits/ 64 <1843200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1881600000 { + opp-hz =3D /bits/ 64 <1881600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1920000000 { + opp-hz =3D /bits/ 64 <1920000000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1958400000 { + opp-hz =3D /bits/ 64 <1958400000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1996800000 { + opp-hz =3D /bits/ 64 <1996800000>; + opp-peak-kBps =3D <3732000>; + }; + + opp-2035200000 { + opp-hz =3D /bits/ 64 <2035200000>; + opp-peak-kBps =3D <3732000>; + }; + }; + + a57_opp_tbl: opp-table-cluster1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-883200000 { + opp-hz =3D /bits/ 64 <883200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-921600000 { + opp-hz =3D /bits/ 64 <921600000>; + opp-peak-kBps =3D <816000>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1036800000 { + opp-hz =3D /bits/ 64 <1036800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1075200000 { + opp-hz =3D /bits/ 64 <1075200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1152000000 { + opp-hz =3D /bits/ 64 <1152000000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1190400000 { + opp-hz =3D /bits/ 64 <1190400000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1267200000 { + opp-hz =3D /bits/ 64 <1267200000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1305600000 { + opp-hz =3D /bits/ 64 <1305600000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1382400000 { + opp-hz =3D /bits/ 64 <1382400000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1420800000 { + opp-hz =3D /bits/ 64 <1420800000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1459200000 { + opp-hz =3D /bits/ 64 <1459200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1497600000 { + opp-hz =3D /bits/ 64 <1497600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1536000000 { + opp-hz =3D /bits/ 64 <1536000000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1574400000 { + opp-hz =3D /bits/ 64 <1574400000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1612800000 { + opp-hz =3D /bits/ 64 <1612800000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1689600000 { + opp-hz =3D /bits/ 64 <1689600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1728000000 { + opp-hz =3D /bits/ 64 <1728000000>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-tegra186-icc-v2-8-09413724e781@gmail.com> References: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> In-Reply-To: <20250909-tegra186-icc-v2-0-09413724e781@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , "Rafael J. Wysocki" , Viresh Kumar , Krzysztof Kozlowski Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757398893; l=16615; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=/lyxFq4FtwqFWSe2Uad7pZP8fOmf4A1pwq5iQ+AYobQ=; b=F7gjzA7IEvgdvcFXJrpiq1/KJBEAhaKm50bSUKroobfRr4vU7zdpZA50jEGOJMuhxfY5aMwo+ XiEqNkkCWlND4N+YnCt67StsI3gDshWES/1DM4Hj7HTMzQ88jdo6/J/ X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add OPP table and interconnects property to scale DDR frequency with CPU frequency for better performance. Each operating point entry of the OPP table has CPU freq to per MC channel bandwidth mapping. One table is added for each cluster even though the table data is same because the bandwidth request is per cluster. This is done because the OPP framework creates a single icc path and hence single bandwidth request if the table is marked as 'opp-shared' and shared among all clusters. For us, the OPP table data is same but the MC Client ID argument to interconnects property is different for each cluster. So, having per cluster tables makes different icc paths for each cluster and helps to make per cluster BW requests. Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 636 +++++++++++++++++++++++++++= ++++ 1 file changed, 636 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts= /nvidia/tegra194.dtsi index 1399342f23e1c4f73b278adc66dfb948fc30d326..a6c4c6c73707354f62f778bbea5= afaec3fdbe22d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2890,6 +2890,8 @@ cpu0_0: cpu@0 { device_type =3D "cpu"; reg =3D <0x000>; enable-method =3D "psci"; + operating-points-v2 =3D <&cl0_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; i-cache-size =3D <131072>; i-cache-line-size =3D <64>; i-cache-sets =3D <512>; @@ -2904,6 +2906,8 @@ cpu0_1: cpu@1 { device_type =3D "cpu"; reg =3D <0x001>; enable-method =3D "psci"; + operating-points-v2 =3D <&cl0_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; i-cache-size =3D <131072>; i-cache-line-size =3D <64>; i-cache-sets =3D <512>; @@ -2918,6 +2922,8 @@ cpu1_0: cpu@100 { device_type =3D "cpu"; reg =3D <0x100>; enable-method =3D "psci"; + operating-points-v2 =3D <&cl1_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; i-cache-size =3D <131072>; i-cache-line-size =3D <64>; i-cache-sets =3D <512>; @@ -2932,6 +2938,8 @@ cpu1_1: cpu@101 { device_type =3D "cpu"; reg =3D <0x101>; enable-method =3D "psci"; + operating-points-v2 =3D <&cl1_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; i-cache-size =3D <131072>; i-cache-line-size =3D <64>; i-cache-sets =3D <512>; @@ -2946,6 +2954,8 @@ cpu2_0: cpu@200 { device_type =3D "cpu"; reg =3D <0x200>; enable-method =3D "psci"; + operating-points-v2 =3D <&cl2_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; i-cache-size =3D <131072>; i-cache-line-size =3D <64>; i-cache-sets =3D <512>; @@ -2960,6 +2970,8 @@ cpu2_1: cpu@201 { device_type =3D "cpu"; reg =3D <0x201>; enable-method =3D "psci"; + operating-points-v2 =3D <&cl2_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; i-cache-size =3D <131072>; i-cache-line-size =3D <64>; i-cache-sets =3D <512>; @@ -2974,6 +2986,8 @@ cpu3_0: cpu@300 { device_type =3D "cpu"; reg =3D <0x300>; enable-method =3D "psci"; + operating-points-v2 =3D <&cl3_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER3 &emc>; i-cache-size =3D <131072>; i-cache-line-size =3D <64>; i-cache-sets =3D <512>; @@ -2988,6 +3002,8 @@ cpu3_1: cpu@301 { device_type =3D "cpu"; reg =3D <0x301>; enable-method =3D "psci"; + operating-points-v2 =3D <&cl3_opp_tbl>; + interconnects =3D <&mc TEGRA_ICC_MC_CPU_CLUSTER3 &emc>; i-cache-size =3D <131072>; i-cache-line-size =3D <64>; i-cache-sets =3D <512>; @@ -3181,4 +3197,624 @@ timer { interrupt-parent =3D <&gic>; always-on; }; + + cl0_opp_tbl: opp-table-cluster0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-115200000 { + opp-hz =3D /bits/ 64 <115200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-268800000 { + opp-hz =3D /bits/ 64 <268800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-345600000 { + opp-hz =3D /bits/ 64 <345600000>; + opp-peak-kBps =3D <816000>; + }; + + opp-422400000 { + opp-hz =3D /bits/ 64 <422400000>; + opp-peak-kBps =3D <816000>; + }; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-576000000 { + opp-hz =3D /bits/ 64 <576000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-652800000 { + opp-hz =3D /bits/ 64 <652800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-729600000 { + opp-hz =3D /bits/ 64 <729600000>; + opp-peak-kBps =3D <816000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + opp-peak-kBps =3D <816000>; + }; + + opp-883200000 { + opp-hz =3D /bits/ 64 <883200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1036800000 { + opp-hz =3D /bits/ 64 <1036800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1190400000 { + opp-hz =3D /bits/ 64 <1190400000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1267200000 { + opp-hz =3D /bits/ 64 <1267200000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1420800000 { + opp-hz =3D /bits/ 64 <1420800000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1497600000 { + opp-hz =3D /bits/ 64 <1497600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1574400000 { + opp-hz =3D /bits/ 64 <1574400000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1728000000 { + opp-hz =3D /bits/ 64 <1728000000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1804800000 { + opp-hz =3D /bits/ 64 <1804800000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1881600000 { + opp-hz =3D /bits/ 64 <1881600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1907200000 { + opp-hz =3D /bits/ 64 <1907200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1958400000 { + opp-hz =3D /bits/ 64 <1958400000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-2035200000 { + opp-hz =3D /bits/ 64 <2035200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-2112000000 { + opp-hz =3D /bits/ 64 <2112000000>; + opp-peak-kBps =3D <4266000>; + }; + + opp-2188800000 { + opp-hz =3D /bits/ 64 <2188800000>; + opp-peak-kBps =3D <4266000>; + }; + + opp-2265600000 { + opp-hz =3D /bits/ 64 <2265600000>; + opp-peak-kBps =3D <4266000>; + }; + }; + + cl1_opp_tbl: opp-table-cluster1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-115200000 { + opp-hz =3D /bits/ 64 <115200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-268800000 { + opp-hz =3D /bits/ 64 <268800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-345600000 { + opp-hz =3D /bits/ 64 <345600000>; + opp-peak-kBps =3D <816000>; + }; + + opp-422400000 { + opp-hz =3D /bits/ 64 <422400000>; + opp-peak-kBps =3D <816000>; + }; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-576000000 { + opp-hz =3D /bits/ 64 <576000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-652800000 { + opp-hz =3D /bits/ 64 <652800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-729600000 { + opp-hz =3D /bits/ 64 <729600000>; + opp-peak-kBps =3D <816000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + opp-peak-kBps =3D <816000>; + }; + + opp-883200000 { + opp-hz =3D /bits/ 64 <883200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1036800000 { + opp-hz =3D /bits/ 64 <1036800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1190400000 { + opp-hz =3D /bits/ 64 <1190400000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1267200000 { + opp-hz =3D /bits/ 64 <1267200000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1420800000 { + opp-hz =3D /bits/ 64 <1420800000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1497600000 { + opp-hz =3D /bits/ 64 <1497600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1574400000 { + opp-hz =3D /bits/ 64 <1574400000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1728000000 { + opp-hz =3D /bits/ 64 <1728000000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1804800000 { + opp-hz =3D /bits/ 64 <1804800000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1881600000 { + opp-hz =3D /bits/ 64 <1881600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1907200000 { + opp-hz =3D /bits/ 64 <1907200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1958400000 { + opp-hz =3D /bits/ 64 <1958400000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-2035200000 { + opp-hz =3D /bits/ 64 <2035200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-2112000000 { + opp-hz =3D /bits/ 64 <2112000000>; + opp-peak-kBps =3D <4266000>; + }; + + opp-2188800000 { + opp-hz =3D /bits/ 64 <2188800000>; + opp-peak-kBps =3D <4266000>; + }; + + opp-2265600000 { + opp-hz =3D /bits/ 64 <2265600000>; + opp-peak-kBps =3D <4266000>; + }; + }; + + cl2_opp_tbl: opp-table-cluster2 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-115200000 { + opp-hz =3D /bits/ 64 <115200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-268800000 { + opp-hz =3D /bits/ 64 <268800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-345600000 { + opp-hz =3D /bits/ 64 <345600000>; + opp-peak-kBps =3D <816000>; + }; + + opp-422400000 { + opp-hz =3D /bits/ 64 <422400000>; + opp-peak-kBps =3D <816000>; + }; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-576000000 { + opp-hz =3D /bits/ 64 <576000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-652800000 { + opp-hz =3D /bits/ 64 <652800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-729600000 { + opp-hz =3D /bits/ 64 <729600000>; + opp-peak-kBps =3D <816000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + opp-peak-kBps =3D <816000>; + }; + + opp-883200000 { + opp-hz =3D /bits/ 64 <883200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1036800000 { + opp-hz =3D /bits/ 64 <1036800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1190400000 { + opp-hz =3D /bits/ 64 <1190400000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1267200000 { + opp-hz =3D /bits/ 64 <1267200000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1420800000 { + opp-hz =3D /bits/ 64 <1420800000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1497600000 { + opp-hz =3D /bits/ 64 <1497600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1574400000 { + opp-hz =3D /bits/ 64 <1574400000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1728000000 { + opp-hz =3D /bits/ 64 <1728000000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1804800000 { + opp-hz =3D /bits/ 64 <1804800000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1881600000 { + opp-hz =3D /bits/ 64 <1881600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1907200000 { + opp-hz =3D /bits/ 64 <1907200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1958400000 { + opp-hz =3D /bits/ 64 <1958400000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-2035200000 { + opp-hz =3D /bits/ 64 <2035200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-2112000000 { + opp-hz =3D /bits/ 64 <2112000000>; + opp-peak-kBps =3D <4266000>; + }; + + opp-2188800000 { + opp-hz =3D /bits/ 64 <2188800000>; + opp-peak-kBps =3D <4266000>; + }; + + opp-2265600000 { + opp-hz =3D /bits/ 64 <2265600000>; + opp-peak-kBps =3D <4266000>; + }; + }; + + cl3_opp_tbl: opp-table-cluster3 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-115200000 { + opp-hz =3D /bits/ 64 <115200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-268800000 { + opp-hz =3D /bits/ 64 <268800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-345600000 { + opp-hz =3D /bits/ 64 <345600000>; + opp-peak-kBps =3D <816000>; + }; + + opp-422400000 { + opp-hz =3D /bits/ 64 <422400000>; + opp-peak-kBps =3D <816000>; + }; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-576000000 { + opp-hz =3D /bits/ 64 <576000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-652800000 { + opp-hz =3D /bits/ 64 <652800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-729600000 { + opp-hz =3D /bits/ 64 <729600000>; + opp-peak-kBps =3D <816000>; + }; + + opp-806400000 { + opp-hz =3D /bits/ 64 <806400000>; + opp-peak-kBps =3D <816000>; + }; + + opp-883200000 { + opp-hz =3D /bits/ 64 <883200000>; + opp-peak-kBps =3D <816000>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1036800000 { + opp-hz =3D /bits/ 64 <1036800000>; + opp-peak-kBps =3D <816000>; + }; + + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1190400000 { + opp-hz =3D /bits/ 64 <1190400000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1267200000 { + opp-hz =3D /bits/ 64 <1267200000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1420800000 { + opp-hz =3D /bits/ 64 <1420800000>; + opp-peak-kBps =3D <1600000>; + }; + + opp-1497600000 { + opp-hz =3D /bits/ 64 <1497600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1574400000 { + opp-hz =3D /bits/ 64 <1574400000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1728000000 { + opp-hz =3D /bits/ 64 <1728000000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1804800000 { + opp-hz =3D /bits/ 64 <1804800000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1881600000 { + opp-hz =3D /bits/ 64 <1881600000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1907200000 { + opp-hz =3D /bits/ 64 <1907200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-1958400000 { + opp-hz =3D /bits/ 64 <1958400000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-2035200000 { + opp-hz =3D /bits/ 64 <2035200000>; + opp-peak-kBps =3D <3200000>; + }; + + opp-2112000000 { + opp-hz =3D /bits/ 64 <2112000000>; + opp-peak-kBps =3D <4266000>; + }; + + opp-2188800000 { + opp-hz =3D /bits/ 64 <2188800000>; + opp-peak-kBps =3D <4266000>; + }; + + opp-2265600000 { + opp-hz =3D /bits/ 64 <2265600000>; + opp-peak-kBps =3D <4266000>; + }; + }; }; --=20 2.50.1