From nobody Fri Oct 3 01:08:49 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC7DC221F26; Tue, 9 Sep 2025 05:13:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757394809; cv=none; b=QhoIBMS2fU+kY/uyKIZYsB4ka/hIH9NKWLeO3TKlVve5ahuoJM1FmaRv1/kFaz7//93pQ86y9P14Q7Ad6fm4WNOuWBipipXHsbAX/A4PiodcWklzT84VBK/r9wVImNOn2Gh8Ey3FPIRubmzbcWmleFIoTgMZEu7t3Y9UD5qFzlE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757394809; c=relaxed/simple; bh=9kBKm/gBv1uCgD5lsyQqPzoNEJYvhKjrD6QZgPZrqv8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=K2L6fJWlCD2BhtPUORJGvT78rRxXPGvILpGI79T6aIhcPmtXHnNLpbgqXwnDmwlgw91KQhCmPi5NU0AyWIresTuOz6pdx+OdtQAxFJXzE0z5pKmCtmaHyYF6bctwKp5jHU3wO3OShGBHqeEmO8CzddHMBI3tjr8s27QGR3kEFwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EHYqroyV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EHYqroyV" Received: by smtp.kernel.org (Postfix) with ESMTPS id 80F17C4CEF5; Tue, 9 Sep 2025 05:13:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757394808; bh=9kBKm/gBv1uCgD5lsyQqPzoNEJYvhKjrD6QZgPZrqv8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=EHYqroyVUqlSXUHC5DMAnXI8w3eMP8ESLu4LVO12cvXJXtWPsfLH3ap4NVBt9ywJR pc0trpja3Su3ZLPdQGl1Cl1NJojxdQ0BP6riGnKBDAeAdfIHuE8y/6QQPB/rCCugMY Sap+VbUnXq8n2dBNSpsoKBB9tZKMF55V5EzX+KMwoyC+3ybO2ZsK5I/M+t8ttxLRvi dE1U0+PUCII/QENDJ18lX7UBpCt+jhrk9cur668CZdqnJASjol77iZHZZLRCe/r1t6 qpf/3VnrZb8indDNdL4rt4wCSUw13t0eLZP6jNe6umUSd4m5nGIdypB6qSsLqTfjnD jZtmBAp8VFtPQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 705F2CA0FED; Tue, 9 Sep 2025 05:13:28 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Tue, 09 Sep 2025 13:13:25 +0800 Subject: [PATCH v5 1/3] spi: dt-bindings: add Amlogic A113L2 SFC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-spifc-v5-1-962bc147d17f@amlogic.com> References: <20250909-spifc-v5-0-962bc147d17f@amlogic.com> In-Reply-To: <20250909-spifc-v5-0-962bc147d17f@amlogic.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liang Yang , Feng Chen Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, Xianwei Zhao , Conor Dooley X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757394806; l=2921; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=IJXxGvCCcnhjW/q7lyLw0FtfCEtHZHIRbIAcYUb/Pz0=; b=WkIoqR7Yb1rXj19ROKSuuoGH0/JBxnw7qN79PR5AiweWblD6d221N4iXfYFmzOuEsWZwC13Ox /xH/qzzgFGvCxUkHo4GUxt3FQaBaApv+HK1DUsr+vvpSrL3trsStraJ X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Feng Chen The Flash Controller is derived by adding an SPI path to the original raw NAND controller. This controller supports two modes: raw mode and SPI mode. The raw mode has already been implemented in the community, and the SPI mode is described here. Add bindings for Amlogic A113L2 SPI Flash Controller. Signed-off-by: Feng Chen Reviewed-by: Conor Dooley Signed-off-by: Xianwei Zhao --- .../devicetree/bindings/spi/amlogic,a4-spifc.yaml | 82 ++++++++++++++++++= ++++ 1 file changed, 82 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml b/= Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml new file mode 100644 index 000000000000..b4cef838bcd4 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/amlogic,a4-spifc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPI flash controller for Amlogic ARM SoCs + +maintainers: + - Liang Yang + - Feng Chen + - Xianwei Zhao + +description: + The Amlogic SPI flash controller is an extended version of the Amlogic N= AND + flash controller. It supports SPI Nor Flash and SPI NAND Flash(where the= Host + ECC HW engine could be enabled). + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: amlogic,a4-spifc + + reg: + maxItems: 1 + + clocks: + items: + - description: clock apb gate + - description: clock used for the controller + + clock-names: + items: + - const: gate + - const: core + + interrupts: + maxItems: 1 + + amlogic,rx-adj: + description: + Number of clock cycles by which sampling is delayed. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + sfc0: spi@fe08d000 { + compatible =3D "amlogic,a4-spifc"; + reg =3D <0xfe08d000 0x800>; + clocks =3D <&clkc_periphs 31>, + <&clkc_periphs 102>; + clock-names =3D "gate", "core"; + + pinctrl-0 =3D <&spiflash_default>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + flash@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nand-ecc-engine =3D <&sfc0>; + nand-ecc-strength =3D <8>; + nand-ecc-step-size =3D <512>; + }; + }; --=20 2.37.1