From nobody Fri Oct 3 01:09:31 2025 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 190F3309DCC for ; Tue, 9 Sep 2025 09:15:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757409362; cv=none; b=MZqTWZzwR8J+KShK4+1XNMM2xayo3U2WnAkCPamMrN+g44gq3X0VGCob1GXEklJM4/eOkdFnwi3KAUFka8Eg5AtkIlYEMUIKsnfAq+GhlMaUcyY74QeuTB946STQNaqQn/chXOM9jeIgOkUmGEXCTIWLRAZBaR3O+GnYuCTU7QU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757409362; c=relaxed/simple; bh=1FEcQAUswumhuSrIfLEzKyEKnEkv//ILIT58TzKEylA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i5MFzoHkMRFkJzCRQNa3sVDBjeyVl+LDgV86QR5Jgxpc7yC39lXTKcUq+losH71a67qycKR3TCELR8uFBDcaKnwxCJA7L63zmPlP3hNnXoHop1BCkUsPhzMf2qGkKfhwkusw7edaUE06AgEfUsCb4JugiuSJbJN8nvGJw4MUzOU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=bgdev.pl; spf=none smtp.mailfrom=bgdev.pl; dkim=pass (2048-bit key) header.d=bgdev-pl.20230601.gappssmtp.com header.i=@bgdev-pl.20230601.gappssmtp.com header.b=FOdwJ9Nm; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=bgdev.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bgdev-pl.20230601.gappssmtp.com header.i=@bgdev-pl.20230601.gappssmtp.com header.b="FOdwJ9Nm" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-3c68ac7e18aso3372966f8f.2 for ; Tue, 09 Sep 2025 02:15:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20230601.gappssmtp.com; s=20230601; t=1757409358; x=1758014158; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=imvYh5lR/dHX9OHCZw7SQaMxZ7ezZGMquKjwxXrqu/k=; b=FOdwJ9Nm3infU61sOR3jK0/8Ifb8O0QmEAy3wNpfwfZbIpoFmadwo7lXEZXuwWKjmJ aqPnZsjmNLjr0GbsFNaRxFuFdFuKcUVJqwMU00Z7eHCKOY1iQzsKeVBGTgnYCOY6dWgI eZcfc/7mIWeKINxQwfvfg3/bQ1d/VuXMHG7HEiBD/4bwMMrRb9j0/ZkVZYGbQAUsu6sq GWmtikHtLii4bzA5CYZJs4OdZzHVyIk9pVIO/V3wOYrKR9dJGSK1fcQx78x0EXrEBk3d U4FnNhgPjH61gxu3titlot7VLdhFgqAMdHon9LvzqUmKZ2DNEY4Z1DIC0rkQQvV8OHZR 3eQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757409358; x=1758014158; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=imvYh5lR/dHX9OHCZw7SQaMxZ7ezZGMquKjwxXrqu/k=; b=fPAWo1n232lj7eESf2OhwTQq2DrQLmQmfaL019MeAi53aTaS26PTo+ZMIYKAd/lIvp ghNg03Yqt3hUydweWAncXgd8begGxkHhaxv7Sih2xVoZ3zSY3LzXCzDZhKFxSlCHXUPt lvrcVE4+pSwpzQUssIjffe1l6KBWwMlgNv4WYyTKAcpB144WPyXsKzYygEeNChaJwWpH nptb+gZnmC6wnr1sp1rdDCf4x53d4RUjFaQNT0t19BmRcO+AiZ+LLNs7KIqFB8X/RYkn 8Tjyyno4cyH+JpjVJYuSjLSbLq2G5ybcAyVpd00q9HGlliBAF7HGjY8nnQ92TKvy37KP L9DQ== X-Forwarded-Encrypted: i=1; AJvYcCXe0O9IjVRvP0J8wsL/ETIRDgFIrypxh3imKDMeoQ10DWvjMyAOHWUmgdtLay/YwkMB8uE/2qiSzeZq6Q0=@vger.kernel.org X-Gm-Message-State: AOJu0YwPzmJARjTT9U4wxNpQxEKT79KigSay3deE+gll2GDQ6Y5yPB1n 1JyoUJ63xYfFDdaC2e9VFgyqUjuT9R8wzR33X+N9f2WWUWsEetn+jPfoqtY4Vbl7hPk= X-Gm-Gg: ASbGncu3eu1E/UkWfsC6XiCy0YGJHkHAOgxdlZBDJQfN+vTMDA/Z22tjfIETJi7yeBK EvHA+VLWL8qx3MvSvTWJay5scPeSkxUsowSMWZfmOUMMB7Ah6OkNjeZ48RNrrWhLy1zAkm+YztG FH/bHFv86YqPCRMXzHzzMeIV3skY3hFNl9swzlu+DacGXK88PAkUjo7wg/ayYatpLEYFar1WLv3 +mbCCQnwAVzqgerXrOs6fBGOg8LJuMEGG4O02MlVWx6az+XWSLYgHk5UHj0aJzl7qFTa/go97bH oayfvN5+S01O3nkRDwRs0/34VzOPODT/9Kjf7elvuqYX6IbI4bkU/JqFI4HuYP0INUoamo5F0Fb MaxGW3eut67dTzjU89g== X-Google-Smtp-Source: AGHT+IFXdZbV4+FiR+g1iDJ8jJCYsBpu7n34tdX+VbMu0cFX2kWCDQk+M9AJM+qd4ppleGeZ928X+w== X-Received: by 2002:a05:6000:2f86:b0:3da:484a:3109 with SMTP id ffacd0b85a97d-3e6462581b8mr10915610f8f.38.1757409358327; Tue, 09 Sep 2025 02:15:58 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:c1ee:7be9:3ebb:6cc0]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e7521c9caasm1900039f8f.19.2025.09.09.02.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Sep 2025 02:15:56 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 09 Sep 2025 11:15:35 +0200 Subject: [PATCH 08/15] gpio: mt7621: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-gpio-mmio-gpio-conv-part4-v1-8-9f723dc3524a@linaro.org> References: <20250909-gpio-mmio-gpio-conv-part4-v1-0-9f723dc3524a@linaro.org> In-Reply-To: <20250909-gpio-mmio-gpio-conv-part4-v1-0-9f723dc3524a@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Keguang Zhang , Alban Bedel , Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Matthias Brugger , AngeloGioacchino Del Regno , Paul Walmsley , Samuel Holland , Yixun Lan , Andy Shevchenko Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4763; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=M1OC3OhNMgxsP5tAU1lwG6NLBHcwqFdL7D8NR7XeUHg=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBov/A4aZdax70K5uQfOmnaoQXt7HkrYee5gxJRb 6C6qpw21tGJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaL/wOAAKCRARpy6gFHHX crGMEACO4tQW9r/dZEd11av+YA6qbWLWsdG+wUB7P/ckV/W+L99g0jDIZ8ZxwasnJyqD7RyZ00E 2DEUCCF/TkBEvZF7s7iZfVuIKwjGb27+59KWDM0loRrPE0MNZSmAB1lxSKe9LglSlOINSmKRTXw cRa4kQ/Df8O9mz3y7wSQ41HUnv62dRhoaPmREqSENbZMGTSumq463FnVOI60KiaL5I1eICCWVd/ uPU3dDiBTgtU9/QSsR2NEXM0jV8X4U86r+jVKCTkP30c13kD5l2fQq6XQe5YCWE9Ltd9meCLkFK laYeyO1mk6xHPgr9mik32wx/m9wbwoSgyyRotGrxmOgZCWMrk86iSx9nilpAFuSW2KBcaGpWEQo AZ0hPY2YNCR3BivREbh9xKPwPn0e5MxKFJLGzHnSnVFCw1J87ALf7Djs1Eh+HWDd9LF2rg+Vjo4 8VXPgfe37EZHRKPe1Bw6mosIGM0U4CpTYk6VY+HYU6rM7lJios/x3nfhWnOFj526OHEdDCooA0f m/W8+zKBpULtaJbckno/1b1OdvacZ/zfYHxVMjlL7ihR1hCRkFvw7sCzJIE3pDfPQuMv2u3cc+o 4kVW5zkUcdATe1gdK8LcNb1p4slcV1povBGAcHVdWCWUYcyLHMknJ7ZOgvxFCP4hDT2g9MO5N5u v0s8Kkc0/dHTi4w== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Sergio Paracuellos --- drivers/gpio/gpio-mt7621.c | 51 +++++++++++++++++++++++++++++-------------= ---- 1 file changed, 32 insertions(+), 19 deletions(-) diff --git a/drivers/gpio/gpio-mt7621.c b/drivers/gpio/gpio-mt7621.c index 93facbebb80efadbdd3fb4500e0db14936287f1a..ed444cc8bc7c2b921be6588ce85= 0027a2e3088b4 100644 --- a/drivers/gpio/gpio-mt7621.c +++ b/drivers/gpio/gpio-mt7621.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include #include #include @@ -30,7 +31,7 @@ =20 struct mtk_gc { struct irq_chip irq_chip; - struct gpio_chip chip; + struct gpio_generic_chip chip; spinlock_t lock; int bank; u32 rising; @@ -59,27 +60,29 @@ struct mtk { static inline struct mtk_gc * to_mediatek_gpio(struct gpio_chip *chip) { - return container_of(chip, struct mtk_gc, chip); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(chip); + + return container_of(gen_gc, struct mtk_gc, chip); } =20 static inline void mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val) { - struct gpio_chip *gc =3D &rg->chip; + struct gpio_chip *gc =3D &rg->chip.gc; struct mtk *mtk =3D gpiochip_get_data(gc); =20 offset =3D (rg->bank * GPIO_BANK_STRIDE) + offset; - gc->write_reg(mtk->base + offset, val); + gpio_generic_write_reg(&rg->chip, mtk->base + offset, val); } =20 static inline u32 mtk_gpio_r32(struct mtk_gc *rg, u32 offset) { - struct gpio_chip *gc =3D &rg->chip; + struct gpio_chip *gc =3D &rg->chip.gc; struct mtk *mtk =3D gpiochip_get_data(gc); =20 offset =3D (rg->bank * GPIO_BANK_STRIDE) + offset; - return gc->read_reg(mtk->base + offset); + return gpio_generic_read_reg(&rg->chip, mtk->base + offset); } =20 static irqreturn_t @@ -220,6 +223,7 @@ static const struct irq_chip mt7621_irq_chip =3D { static int mediatek_gpio_bank_probe(struct device *dev, int bank) { + struct gpio_generic_chip_config config; struct mtk *mtk =3D dev_get_drvdata(dev); struct mtk_gc *rg; void __iomem *dat, *set, *ctrl, *diro; @@ -236,21 +240,30 @@ mediatek_gpio_bank_probe(struct device *dev, int bank) ctrl =3D mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE); diro =3D mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE); =20 - ret =3D bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL, - BGPIOF_NO_SET_ON_INPUT); + config =3D (typeof(config)){ + .dev =3D dev, + .sz =3D 4, + .dat =3D dat, + .set =3D set, + .clr =3D ctrl, + .dirout =3D diro, + .flags =3D BGPIOF_NO_SET_ON_INPUT, + }; + + ret =3D gpio_generic_chip_init(&rg->chip, &config); if (ret) { - dev_err(dev, "bgpio_init() failed\n"); + dev_err(dev, "failed to initialize generic GPIO chip\n"); return ret; } =20 - rg->chip.of_gpio_n_cells =3D 2; - rg->chip.of_xlate =3D mediatek_gpio_xlate; - rg->chip.label =3D devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d", + rg->chip.gc.of_gpio_n_cells =3D 2; + rg->chip.gc.of_xlate =3D mediatek_gpio_xlate; + rg->chip.gc.label =3D devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d", dev_name(dev), bank); - if (!rg->chip.label) + if (!rg->chip.gc.label) return -ENOMEM; =20 - rg->chip.offset =3D bank * MTK_BANK_WIDTH; + rg->chip.gc.offset =3D bank * MTK_BANK_WIDTH; =20 if (mtk->gpio_irq) { struct gpio_irq_chip *girq; @@ -261,7 +274,7 @@ mediatek_gpio_bank_probe(struct device *dev, int bank) */ ret =3D devm_request_irq(dev, mtk->gpio_irq, mediatek_gpio_irq_handler, IRQF_SHARED, - rg->chip.label, &rg->chip); + rg->chip.gc.label, &rg->chip.gc); =20 if (ret) { dev_err(dev, "Error requesting IRQ %d: %d\n", @@ -269,7 +282,7 @@ mediatek_gpio_bank_probe(struct device *dev, int bank) return ret; } =20 - girq =3D &rg->chip.irq; + girq =3D &rg->chip.gc.irq; gpio_irq_chip_set_chip(girq, &mt7621_irq_chip); /* This will let us handle the parent IRQ in the driver */ girq->parent_handler =3D NULL; @@ -279,17 +292,17 @@ mediatek_gpio_bank_probe(struct device *dev, int bank) girq->handler =3D handle_simple_irq; } =20 - ret =3D devm_gpiochip_add_data(dev, &rg->chip, mtk); + ret =3D devm_gpiochip_add_data(dev, &rg->chip.gc, mtk); if (ret < 0) { dev_err(dev, "Could not register gpio %d, ret=3D%d\n", - rg->chip.ngpio, ret); + rg->chip.gc.ngpio, ret); return ret; } =20 /* set polarity to low for all gpios */ mtk_gpio_w32(rg, GPIO_REG_POL, 0); =20 - dev_info(dev, "registering %d gpios\n", rg->chip.ngpio); + dev_info(dev, "registering %d gpios\n", rg->chip.gc.ngpio); =20 return 0; } --=20 2.48.1