From nobody Fri Oct 3 00:55:40 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CDE431AF1D; Tue, 9 Sep 2025 10:12:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757412748; cv=none; b=TLtemVA51u32tpZ/g+4hq12Ybwuvwyy7hP97pdPHN+TToSDLETgRc6HA1CorL3zgm4y8mYjH6kN/eByYwSoZMBldM6ADn36xxTf635V810GcZ8aHixCOt/sf2tx4QoOZ+ewzsVS9HurYdfqEcTq6zq9wrvG81PYS+Z8nlUq17hA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757412748; c=relaxed/simple; bh=ciJyOR3eGK2gidrZT8YeI5fy6dg+FxklvW19mrX4w1c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=haZb0d0g9UIorE1mXpbbVNlXiw1GSc+e14zXN+eEw39QivNK2EbBy4kjUs7WYv5749jYlsvlFEUoYOI+XGLc0894JrcA6gq9Zfviy2z7W4kO7UwwXyRtjbWYTkSlp2sIKMXfj36J4b/rQrupwPD1bZ8/M6AJQXxTRl7TGs7OaqI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Mpas5YKI; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Mpas5YKI" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-45decc9e83dso4663315e9.0; Tue, 09 Sep 2025 03:12:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757412744; x=1758017544; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=LPzMl9444DyFsyhIlxZU2alp+KEUomV9x8N6sGCMpt4=; b=Mpas5YKI5ekTCXdsyJkl0AtfBk0M61NJJnbLvddhF4wYZCp7CWeLojC66Vgu1HkEk7 nGpmS8hWEJ+fnwUK++fpnevU4Z3lxMD/8odjUSZy6gEO65YWxUhQaRlAsrMh7+vFb7NA IvGdUw2p9royABxiuPW1xvXCvSgGi+6PRh/D+/+uvzgNCqoOm2jYOnvIHuSgHk8zLZ71 h40YNmZ7OA4p2L7yvvvOnlcngrxPNr06HUQvf1tOP1ugwozX1QOwhUJCCAoubcgbDf0e QyxN1DmKZR3XdUKGAkItse3mpYtiAhNwtXYkf6b6EKXTpFBGKkh7mer+QegBUEhm1vV+ bjqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757412744; x=1758017544; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LPzMl9444DyFsyhIlxZU2alp+KEUomV9x8N6sGCMpt4=; b=YvUtErNI1AZzt+HYy3KDO37ZG58scfG8Ez5wXFHI+CuCvvBrPHUrth1XeWU3uKBzlE JUSfSWIeutE4upOFDqzLifKdx8gUyFsaIQJ6VKR4O5JEnIEXIrDB+UvDzI7h/btpSOMm PyeyUW27CeCSgtPyIR4sSiApRUHmNVc60+TNiKAGici0RtJ//cKI9NLT3A+lWA3dB2pG 8DeXEjNHX0d2v16QYAyzU7rH+NUPq/KirTn8IHZscSgFFGLIbGzL2b17TWS32VJWRXNs DDuWZJD8Dcpa1mHzeUfGlwSRAsStVj5N/WWlkqy7hNWkRkhFMHxqgMVzvOMcX/ZMvF+w wplQ== X-Forwarded-Encrypted: i=1; AJvYcCUc/9i0inBAkPjv/MtxHYr9DwFbsG6pKlSGACQZtGbgYCodPkINiJTTl0nzmiD8daUbvehCsPi+Aq6i@vger.kernel.org, AJvYcCVloEzdgy/KslrKA/cR8o3aVGPVZQavgqIgXSXTWbXx1YHPllD6VZotPj3X9oVNiNL1DcelEgpu19yK@vger.kernel.org, AJvYcCVr0LWi1gAYS9ASdI4fuEYRIgk3IFOIWXHRo7OswkDctUr+s1QyTUbqFtD0ygQYh39d0nBXb7Ula2c/u6mOEy7zsA==@vger.kernel.org, AJvYcCWn0joCqjzjhGcQQr6mWY/IgB4v8h8/U6B52dxYMu60WL950BKaPCYsGtCQGojh6ZAxBzAO47rJWDcP@vger.kernel.org, AJvYcCWy/0Qac0evaXonJkQuIqu+WRAvy3X9Ucu2IxByn1lZke1rezaZJtrszpExwqP21kwvR35LPHDPshFc0som@vger.kernel.org X-Gm-Message-State: AOJu0YyjHzCJtTjFuVLAAFzXvdSDpPhmZ6YRETohu/J+VbP3jS8ADzzx lryBNyhVBsW6kGqI8tBP8bGbRkfD+jzBAanzNTaY1u4njpyiiLXdaJ8k X-Gm-Gg: ASbGncv9geR2UUCsy61+jNSwr7Yl+Z18CHeapeunh3X7aOsZXrt9rK4ymLy9UD97TOU JgiLJ6YQDdJhxPwSxrKpbXzlsa8SZuYDxb7p1BM7LqjSYk0bJ/JcbyTFntQ/iYeJoiwm10Avg1L lhQPV+iwUY2LKhA7dcFF479zsSM2AeCgp+FRRHX1W9IonWCnkXjEMGM8+ExQ35ZCnEGIEePBI7R 2dAaD+OZMMi+7rTIfg7rNwrA1X2uhQIrnt8q/cdWTMhPkJOeR/fxdE8+0kvfSqGcmf0LQkpuGxb pdh4LfLUJg8bBB3Ppf+EoBnyyE4gneI9hgc1RhIkU0zKEyvfK7SYr4nwZtldVH3vpUNmy2msTgn hWpmMhMwcg2xcIHeDigpiPm34awhRdo9mok+E1Usjr94LyhzTyGQxtDh0c0SHU1mp9pP5yDkKVz B7ZnRNLOA0FmFr/NGCjnQ0DMc6bg== X-Google-Smtp-Source: AGHT+IGPh09/AgyRGnk3hh/JVjy55HRoX4WeFY5HxCNx6I/w3RAwA6apcDwreywzBjxWgSeV51SF/Q== X-Received: by 2002:a05:600c:4587:b0:45d:d94b:a8fc with SMTP id 5b1f17b1804b1-45ddde8c757mr122875745e9.16.1757412744214; Tue, 09 Sep 2025 03:12:24 -0700 (PDT) Received: from localhost (2a02-8440-7136-74e7-5ebf-4282-0e1a-b885.rev.sfr.net. [2a02:8440:7136:74e7:5ebf:4282:e1a:b885]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45df2cb1d77sm9627225e9.3.2025.09.09.03.12.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Sep 2025 03:12:23 -0700 (PDT) From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 09 Sep 2025 12:12:10 +0200 Subject: [PATCH v6 03/20] clk: stm32mp25: add firewall grant_access ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-b4-ddrperfm-upstream-v6-3-ce082cc801b5@gmail.com> References: <20250909-b4-ddrperfm-upstream-v6-0-ce082cc801b5@gmail.com> In-Reply-To: <20250909-b4-ddrperfm-upstream-v6-0-ce082cc801b5@gmail.com> To: Gatien Chevallier , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Gabriel Fernandez , Krzysztof Kozlowski , Julius Werner , Will Deacon , Mark Rutland , Philipp Zabel , Jonathan Corbet Cc: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-dfb17 From: Cl=C3=A9ment Le Goffic On STM32MP25, the RCC peripheral manages the secure level of resources that are used by other devices such as clocks. Declare this peripheral as a firewall controller. Signed-off-by: Cl=C3=A9ment Le Goffic Signed-off-by: Cl=C3=A9ment Le Goffic --- drivers/clk/stm32/clk-stm32mp25.c | 40 +++++++++++++++++++++++++++++++++++= +++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm3= 2mp25.c index 52f0e8a12926..af4bc06d703a 100644 --- a/drivers/clk/stm32/clk-stm32mp25.c +++ b/drivers/clk/stm32/clk-stm32mp25.c @@ -4,8 +4,10 @@ * Author: Gabriel Fernandez for STMicroel= ectronics. */ =20 +#include #include #include +#include #include #include =20 @@ -1602,6 +1604,11 @@ static int stm32_rcc_get_access(void __iomem *base, = u32 index) return 0; } =20 +static int stm32mp25_rcc_grant_access(struct stm32_firewall_controller *ct= rl, u32 firewall_id) +{ + return stm32_rcc_get_access(ctrl->mmio, firewall_id); +} + static int stm32mp25_check_security(struct device_node *np, void __iomem *= base, const struct clock_config *cfg) { @@ -1970,6 +1977,7 @@ MODULE_DEVICE_TABLE(of, stm32mp25_match_data); =20 static int stm32mp25_rcc_clocks_probe(struct platform_device *pdev) { + struct stm32_firewall_controller *rcc_controller; struct device *dev =3D &pdev->dev; void __iomem *base; int ret; @@ -1982,7 +1990,36 @@ static int stm32mp25_rcc_clocks_probe(struct platfor= m_device *pdev) if (ret) return ret; =20 - return stm32_rcc_init(dev, stm32mp25_match_data, base); + ret =3D stm32_rcc_init(dev, stm32mp25_match_data, base); + if (ret) + return ret; + + rcc_controller =3D devm_kzalloc(&pdev->dev, sizeof(*rcc_controller), GFP_= KERNEL); + if (!rcc_controller) + return -ENOMEM; + + rcc_controller->dev =3D dev; + rcc_controller->mmio =3D base; + rcc_controller->name =3D dev_driver_string(dev); + rcc_controller->type =3D STM32_PERIPHERAL_FIREWALL; + rcc_controller->grant_access =3D stm32mp25_rcc_grant_access; + + platform_set_drvdata(pdev, rcc_controller); + + ret =3D stm32_firewall_controller_register(rcc_controller); + if (ret) { + dev_err(dev, "Couldn't register as a firewall controller: %d\n", ret); + return ret; + } + + return 0; +} + +static void stm32mp25_rcc_clocks_remove(struct platform_device *pdev) +{ + struct stm32_firewall_controller *rcc_controller =3D platform_get_drvdata= (pdev); + + stm32_firewall_controller_unregister(rcc_controller); } =20 static struct platform_driver stm32mp25_rcc_clocks_driver =3D { @@ -1991,6 +2028,7 @@ static struct platform_driver stm32mp25_rcc_clocks_dr= iver =3D { .of_match_table =3D stm32mp25_match_data, }, .probe =3D stm32mp25_rcc_clocks_probe, + .remove =3D stm32mp25_rcc_clocks_remove, }; =20 static int __init stm32mp25_clocks_init(void) --=20 2.43.0