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[2a02:8440:7136:74e7:5ebf:4282:e1a:b885]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e75223f3e2sm2041352f8f.44.2025.09.09.03.12.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Sep 2025 03:12:41 -0700 (PDT) From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Tue, 09 Sep 2025 12:12:21 +0200 Subject: [PATCH v6 14/20] Documentation: perf: stm32: add ddrperfm support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-b4-ddrperfm-upstream-v6-14-ce082cc801b5@gmail.com> References: <20250909-b4-ddrperfm-upstream-v6-0-ce082cc801b5@gmail.com> In-Reply-To: <20250909-b4-ddrperfm-upstream-v6-0-ce082cc801b5@gmail.com> To: Gatien Chevallier , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Gabriel Fernandez , Krzysztof Kozlowski , Julius Werner , Will Deacon , Mark Rutland , Philipp Zabel , Jonathan Corbet Cc: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-dfb17 From: Cl=C3=A9ment Le Goffic The DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC. This documentation introduces the DDRPERFM, the stm32-ddr-pmu driver supporting it and how to use it with the perf tool. Signed-off-by: Cl=C3=A9ment Le Goffic Signed-off-by: Cl=C3=A9ment Le Goffic --- Documentation/admin-guide/perf/index.rst | 1 + Documentation/admin-guide/perf/stm32-ddr-pmu.rst | 86 ++++++++++++++++++++= ++++ 2 files changed, 87 insertions(+) diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index 072b510385c4..33aedc4ee5c3 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -29,3 +29,4 @@ Performance monitor support cxl ampere_cspmu mrvl-pem-pmu + stm32-ddr-pmu diff --git a/Documentation/admin-guide/perf/stm32-ddr-pmu.rst b/Documentati= on/admin-guide/perf/stm32-ddr-pmu.rst new file mode 100644 index 000000000000..5b02bf44dd7a --- /dev/null +++ b/Documentation/admin-guide/perf/stm32-ddr-pmu.rst @@ -0,0 +1,86 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +STM32 DDR Performance Monitor (DDRPERFM) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC. +The DDR controller provides events to DDRPERFM, once selected they are cou= nted in the DDRPERFM +peripheral. + +In MP1 family, the DDRPERFM is able to count 4 different events at the sam= e time. +However, the 4 events must belong to the same set. +One hardware counter is dedicated to the time counter, `time_cnt`. + +In MP2 family, the DDRPERFM is able to select between 44 different DDR eve= nts. +As for MP1, there is a dedicated hardware counter for the time. +It is incremented every 4 DDR clock cycles. +All the other counters can be freely allocated to count any other DDR even= t. + +The stm32-ddr-pmu driver relies on the perf PMU framework to expose the co= unters via sysfs: + +On MP1: + + .. code-block:: bash + + $ ls /sys/bus/event_source/devices/stm32_ddr_pmu/events/ + cactive_ddrc perf_lpr_req_with_no_credit perf_op_= is_wr + ctl_idle perf_lpr_xact_when_critical perf_sel= fresh_mode + dfi_lp_req perf_op_is_activate perf_wr_= xact_when_critical + dfi_lp_req_cpy perf_op_is_enter_powerdown time_cnt + perf_hpr_req_with_no_credit perf_op_is_rd + perf_hpr_xact_when_critical perf_op_is_refresh + +On MP2: + + .. code-block:: bash + + $ ls /sys/bus/event_source/devices/stm32_ddr_pmu/events/ + dfi_is_act perf_hpr_req_with_nocredit perf_op_is_spec_ref + dfi_is_mpc perf_hpr_xact_when_critical perf_op_is_wr + dfi_is_mrr perf_lpr_req_with_nocredit perf_op_is_zqcal + dfi_is_mrw perf_lpr_xact_when_critical perf_rank + dfi_is_mwr perf_op_is_act perf_raw_hazard + dfi_is_mwra perf_op_is_crit_ref perf_rdwr_transitions + dfi_is_preab perf_op_is_enter_powdn perf_read_bypass + dfi_is_prepb perf_op_is_enter_selfref perf_war_hazard + dfi_is_rd perf_op_is_mwr perf_waw_hazard + dfi_is_rda perf_op_is_pre perf_window_limit_re= ached_rd + dfi_is_refab perf_op_is_pre_for_others perf_window_limit_re= ached_wr + dfi_is_refpb perf_op_is_pre_for_rdwr perf_wr_xact_when_cr= itical + dfi_is_wr perf_op_is_rd time_cnt + dfi_is_wra perf_op_is_rd_activate + perf_act_bypass perf_op_is_ref + + +The perf PMU framework is usually invoked via the 'perf stat' tool. + + +Example: + + .. code-block:: bash + + $ perf stat --timeout 60000 -e stm32_ddr_pmu/dfi_is_act/,\ + > stm32_ddr_pmu/dfi_is_rd/,\ + > stm32_ddr_pmu/dfi_is_wr/,\ + > stm32_ddr_pmu/dfi_is_refab/,\ + > stm32_ddr_pmu/dfi_is_mrw/,\ + > stm32_ddr_pmu/dfi_is_rda/,\ + > stm32_ddr_pmu/dfi_is_wra/,\ + > stm32_ddr_pmu/dfi_is_mrr/,\ + > stm32_ddr_pmu/time_cnt/ \ + > -a sleep 5 + + Performance counter stats for 'system wide': + + 481025 stm32_ddr_pmu/dfi_is_act/ + 732166 stm32_ddr_pmu/dfi_is_rd/ + 144926 stm32_ddr_pmu/dfi_is_wr/ + 644154 stm32_ddr_pmu/dfi_is_refab/ + 0 stm32_ddr_pmu/dfi_is_mrw/ + 0 stm32_ddr_pmu/dfi_is_rda/ + 0 stm32_ddr_pmu/dfi_is_wra/ + 0 stm32_ddr_pmu/dfi_is_mrr/ + 752347686 stm32_ddr_pmu/time_cnt/ + + 5.014910750 seconds time elapsed --=20 2.43.0