From nobody Wed Sep 10 05:48:27 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B397220687; Tue, 9 Sep 2025 07:29:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757402978; cv=none; b=ujH5AEin3o6eH0HyNxrrWSWTeKhLB43NvIGIsVJ3vVrqFiEZdKxRx6PvjkGqGQukll8Ys5qWUsAzesWpzxIT21fdMRlZzW77TRFHOvppw79m6OKBaBtQUdfHiB0FGRJrJfYxmBPDW7H8Fz2NG38+uSF7WUaN7ZUN+Fc9tU9+REU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757402978; c=relaxed/simple; bh=eOXxHeTvjKv0CA0uVr+x06ld7tUBMbROfdkDUJSVBdo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pNY7abd9pyffJg3MQ8CgVICWOd5PJv+f2f7qGFpjyMn1OrA95TK2A67BSTFsjE81VgfCc5F4Ux7vU4V/PnKuLn/dwfZFUi1pmHVvAF7Uk8Nb1HRdr2p2fe3uNbFQ+gvSBVTPptCHlO+URgqGvk7GmYxoWgRI8+BzpIke03on3Ec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DyCQOyQd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DyCQOyQd" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2D885C4CEF5; Tue, 9 Sep 2025 07:29:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757402978; bh=eOXxHeTvjKv0CA0uVr+x06ld7tUBMbROfdkDUJSVBdo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DyCQOyQdgsfjremiekroOGSRGrhElKd4Eb+dOYVWHJWksUVENk5Ls1We+oiFf322A OcJWAT2wpMuQ04inVppIlnVKFalJ/Xidfb6VSep6jLzQeMgCSYOIbN6ctQNRY0SIhw 4RDPbPkDx4G3OANvQ+4h46J4TTmRCFTAQ9QmbcdcLDhfxRmmPzstOJrkSGDon5TLse rgepuBQrDXVHdt+5DmoIyotRLZzx8Pz77QuuMafDWjhFrLbyx3JiGoTucM81M/zPny 7aFHJcallOiobwa9E6TorH2VjK4bBOtFgoM1NViGjG2/w2ReEHaRY9vLNcSQ+xDiLA pKY2KMB5FCQpg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B13CCAC58C; Tue, 9 Sep 2025 07:29:38 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Tue, 09 Sep 2025 15:29:12 +0800 Subject: [PATCH v4 2/2] clk: amlogic: add video-related clocks for S4 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250909-add_video_clk-v4-2-5e0c01d47aa8@amlogic.com> References: <20250909-add_video_clk-v4-0-5e0c01d47aa8@amlogic.com> In-Reply-To: <20250909-add_video_clk-v4-0-5e0c01d47aa8@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757402973; l=7142; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=hxUpNyutlY08PsI4fM0HrJ0LK2pJdLtd3LRl8Z/JKsE=; b=piwS9s3BANi/UZtaoaH1gL63mepZecjIs8aHH2ZVulh6L1UjpvphHMnahn9RD2L5IdzFjEE8R dX40+D+rm0PDe1Lc1vgs0FK/In/kobGJO5Z4b7rNF2DMHEKHKNXFz9z X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add video encoder, demodulator and CVBS clocks. Signed-off-by: Chuan Liu --- drivers/clk/meson/s4-peripherals.c | 203 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 203 insertions(+) diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index 6d69b132d1e1..b855e8f1fc04 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -44,6 +44,7 @@ #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 #define CLKCTRL_VAPBCLK_CTRL 0x0fc #define CLKCTRL_HDCP22_CTRL 0x100 +#define CLKCTRL_CDAC_CLK_CTRL 0x108 #define CLKCTRL_VDEC_CLK_CTRL 0x140 #define CLKCTRL_VDEC2_CLK_CTRL 0x144 #define CLKCTRL_VDEC3_CLK_CTRL 0x148 @@ -1126,6 +1127,22 @@ static struct clk_regmap s4_cts_encp_sel =3D { }, }; =20 +static struct clk_regmap s4_cts_encl_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_VIID_CLK_DIV, + .mask =3D 0xf, + .shift =3D 12, + .table =3D s4_cts_parents_val_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cts_encl_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D s4_cts_parents, + .num_parents =3D ARRAY_SIZE(s4_cts_parents), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap s4_cts_vdac_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VIID_CLK_DIV, @@ -1205,6 +1222,22 @@ static struct clk_regmap s4_cts_encp =3D { }, }; =20 +static struct clk_regmap s4_cts_encl =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_VID_CLK_CTRL2, + .bit_idx =3D 3, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cts_encl", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cts_encl_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap s4_cts_vdac =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_VID_CLK_CTRL2, @@ -2735,6 +2768,165 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 +/* CVBS DAC */ +static struct clk_regmap s4_cdac_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 16, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fclk_div5" }, + }, + .num_parents =3D 2, + }, +}; + +static struct clk_regmap s4_cdac_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .shift =3D 0, + .width =3D 16, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cdac_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_cdac =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .bit_idx =3D 20, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cdac_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_demod_core_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal" }, + { .fw_name =3D "fclk_div7" }, + { .fw_name =3D "fclk_div4" } + }, + .num_parents =3D 3, + }, +}; + +static struct clk_regmap s4_demod_core_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_demod_core_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_demod_core =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .bit_idx =3D 8 + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_demod_core_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* CVBS ADC */ +static struct clk_regmap s4_adc_extclk_in_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal" }, + { .fw_name =3D "fclk_div4" }, + { .fw_name =3D "fclk_div3" }, + { .fw_name =3D "fclk_div5" }, + { .fw_name =3D "fclk_div7" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "gp0_pll" }, + { .fw_name =3D "hifi_pll" } + }, + .num_parents =3D 8, + }, +}; + +static struct clk_regmap s4_adc_extclk_in_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_adc_extclk_in_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_adc_extclk_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .bit_idx =3D 24 + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_adc_extclk_in_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static const struct clk_parent_data s4_pclk_parents =3D { .hw =3D &s4_sys_= clk.hw }; =20 #define S4_PCLK(_name, _reg, _bit, _flags) \ @@ -3028,6 +3220,17 @@ static struct clk_hw *s4_peripherals_hw_clks[] =3D { [CLKID_HDCP22_SKPCLK_SEL] =3D &s4_hdcp22_skpclk_sel.hw, [CLKID_HDCP22_SKPCLK_DIV] =3D &s4_hdcp22_skpclk_div.hw, [CLKID_HDCP22_SKPCLK] =3D &s4_hdcp22_skpclk.hw, + [CLKID_CTS_ENCL_SEL] =3D &s4_cts_encl_sel.hw, + [CLKID_CTS_ENCL] =3D &s4_cts_encl.hw, + [CLKID_CDAC_SEL] =3D &s4_cdac_sel.hw, + [CLKID_CDAC_DIV] =3D &s4_cdac_div.hw, + [CLKID_CDAC] =3D &s4_cdac.hw, + [CLKID_DEMOD_CORE_SEL] =3D &s4_demod_core_sel.hw, + [CLKID_DEMOD_CORE_DIV] =3D &s4_demod_core_div.hw, + [CLKID_DEMOD_CORE] =3D &s4_demod_core.hw, + [CLKID_ADC_EXTCLK_IN_SEL] =3D &s4_adc_extclk_in_sel.hw, + [CLKID_ADC_EXTCLK_IN_DIV] =3D &s4_adc_extclk_in_div.hw, + [CLKID_ADC_EXTCLK_IN] =3D &s4_adc_extclk_in.hw, }; =20 static const struct meson_clkc_data s4_peripherals_clkc_data =3D { --=20 2.42.0