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Also, add the speedbin qfprom node and wire it up with GPU node. Signed-off-by: Puranam V G Tejaswi Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/lemans.dtsi | 119 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index 8ceb59742a9fc6562b2c38731ddabe3a549f7f35..52c2533383920fdf34dc1eba11e= 5ec01209f4e8a 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -1097,6 +1097,18 @@ ipcc: mailbox@408000 { #mbox-cells =3D <2>; }; =20 + qfprom: efuse@784000 { + compatible =3D "qcom,sa8775p-qfprom", "qcom,qfprom"; + reg =3D <0x0 0x00784000 0x0 0x2410>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + gpu_speed_bin: gpu_speed_bin@240c { + reg =3D <0x240c 0x1>; + bits =3D <0 8>; + }; + }; + gpi_dma2: dma-controller@800000 { compatible =3D "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; reg =3D <0x0 0x00800000 0x0 0x60000>; @@ -4093,6 +4105,113 @@ tcsr: syscon@1fc0000 { reg =3D <0x0 0x1fc0000 0x0 0x30000>; }; =20 + gpu: gpu@3d00000 { + compatible =3D "qcom,adreno-663.0", "qcom,adreno"; + reg =3D <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names =3D "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts =3D ; + iommus =3D <&adreno_smmu 0 0xc00>, + <&adreno_smmu 1 0xc00>; + operating-points-v2 =3D <&gpu_opp_table>; + qcom,gmu =3D <&gmu>; + interconnects =3D <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "gfx-mem"; + #cooling-cells =3D <2>; + + nvmem-cells =3D <&gpu_speed_bin>; + nvmem-cell-names =3D "speed_bin"; + + status =3D "disabled"; + + gpu_zap_shader: zap-shader { + memory-region =3D <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-405000000 { + opp-hz =3D /bits/ 64 <405000000>; + opp-level =3D ; + opp-peak-kBps =3D <5285156>; + opp-supported-hw =3D <0x3>; + }; + + opp-530000000 { + opp-hz =3D /bits/ 64 <530000000>; + opp-level =3D ; + opp-peak-kBps =3D <12484375>; + opp-supported-hw =3D <0x2>; + }; + + opp-676000000 { + opp-hz =3D /bits/ 64 <676000000>; + opp-level =3D ; + opp-peak-kBps =3D <8171875>; + opp-supported-hw =3D <0x1>; + }; + + opp-778000000 { + opp-hz =3D /bits/ 64 <778000000>; + opp-level =3D ; + opp-peak-kBps =3D <10687500>; + opp-supported-hw =3D <0x1>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-level =3D ; + opp-peak-kBps =3D <12484375>; + opp-supported-hw =3D <0x1>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible =3D "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; + reg =3D <0x0 0x03d6a000 0x0 0x34000>, + <0x0 0x03de0000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names =3D "gmu", "rscc", "gmu_pdc"; + interrupts =3D , + ; + interrupt-names =3D "hfi", "gmu"; + clocks =3D <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names =3D "cx", + "gx"; + iommus =3D <&adreno_smmu 5 0xc00>; + operating-points-v2 =3D <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-level =3D ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible =3D "qcom,sa8775p-gpucc"; reg =3D <0x0 0x03d90000 0x0 0xa000>; --=20 2.50.1