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Mon, 8 Sep 2025 21:03:34 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9F89B20040; Mon, 8 Sep 2025 21:03:34 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C080820049; Mon, 8 Sep 2025 21:03:26 +0000 (GMT) Received: from li-e1dea04c-3555-11b2-a85c-f57333552245.ibm.com.com (unknown [9.39.29.251]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 21:03:26 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, deller@gmx.de, ldv@strace.io, macro@orcam.me.uk, charlie@rivosinc.com, akpm@linux-foundation.org, bigeasy@linutronix.de, ankur.a.arora@oracle.com, sshegde@linux.ibm.com, naveen@kernel.org, thomas.weissschuh@linutronix.de, Jason@zx2c4.com, peterz@infradead.org, tglx@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, oliver.upton@linux.dev, mark.barnett@arm.com, atrajeev@linux.vnet.ibm.com, rppt@kernel.org, coltonlewis@google.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [RFC V2 1/8] powerpc: rename arch_irq_disabled_regs Date: Tue, 9 Sep 2025 02:32:29 +0530 Message-ID: <20250908210235.137300-3-mchauras@linux.ibm.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250908210235.137300-2-mchauras@linux.ibm.com> References: <20250908210235.137300-2-mchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 5pLbNry8nW0-OX01XJbnUhyjktixOS9h X-Proofpoint-GUID: JBFYkRnzM7nOfj4G31_970P1CusF0Jia X-Authority-Analysis: v=2.4 cv=EYDIQOmC c=1 sm=1 tr=0 ts=68bf44ad cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=8txWmKPpaVdEF_iBmVcA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAyMCBTYWx0ZWRfX3W6qPUp92bDi wjJISJITvFP6DBsaejXfMCg5NZ6dX6xmHlBt/+fRX043JeqNHTtBIGFpxO2gdAq26a3kEx6gupe 9sevyEE1bFeoTiJTs0kuqbygm0lMUsbFfFhmwWuWfvFl1LtLpWqYQEpv4dLpyMcELSJzBfgnA6m 8i8Lp5ZUtw+3SPywAJaMX/Eo51V6OhTZo63ns8QKP1XJmSxxQyuoScYjNkBtnE6SCp5B1qjrmpT KOBYh1LS2MS0OLNtDhCUZKRaRFGDP2hT7nuX3kCM24FyUc3CRXvH+jKaIvSdZq+SR7G2OMJYTcP 2ber6S7iN97SsxHYXwoV6nyTAmbvOkymn5VKBNGXqVROebpwO23d6eTzVvnmzrOPcbrB3FG7mwU h2Z/QX8U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 impostorscore=0 priorityscore=1501 phishscore=0 clxscore=1011 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060020 Content-Type: text/plain; charset="utf-8" Renaming arch_irq_disabled_regs to regs_irqs_disabled to be used commonly in generic entry exit framework and ppc arch code. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/include/asm/hw_irq.h | 4 ++-- arch/powerpc/include/asm/interrupt.h | 12 ++++++------ arch/powerpc/kernel/interrupt.c | 4 ++-- arch/powerpc/kernel/syscall.c | 2 +- arch/powerpc/kernel/traps.c | 2 +- arch/powerpc/kernel/watchdog.c | 2 +- arch/powerpc/perf/core-book3s.c | 2 +- 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/h= w_irq.h index 569ac1165b069..2b9cf0380e0e9 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h @@ -393,7 +393,7 @@ static inline void do_hard_irq_enable(void) __hard_irq_enable(); } =20 -static inline bool arch_irq_disabled_regs(struct pt_regs *regs) +static inline bool regs_irqs_disabled(struct pt_regs *regs) { return (regs->softe & IRQS_DISABLED); } @@ -466,7 +466,7 @@ static inline bool arch_irqs_disabled(void) =20 #define hard_irq_disable() arch_local_irq_disable() =20 -static inline bool arch_irq_disabled_regs(struct pt_regs *regs) +static inline bool regs_irqs_disabled(struct pt_regs *regs) { return !(regs->msr & MSR_EE); } diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/as= m/interrupt.h index 23638d4e73ac0..56bc8113b8cde 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -172,7 +172,7 @@ static inline void interrupt_enter_prepare(struct pt_re= gs *regs) /* Enable MSR[RI] early, to support kernel SLB and hash faults */ #endif =20 - if (!arch_irq_disabled_regs(regs)) + if (!regs_irqs_disabled(regs)) trace_hardirqs_off(); =20 if (user_mode(regs)) { @@ -192,10 +192,10 @@ static inline void interrupt_enter_prepare(struct pt_= regs *regs) CT_WARN_ON(ct_state() !=3D CT_STATE_KERNEL && ct_state() !=3D CT_STATE_IDLE); INT_SOFT_MASK_BUG_ON(regs, is_implicit_soft_masked(regs)); - INT_SOFT_MASK_BUG_ON(regs, arch_irq_disabled_regs(regs) && + INT_SOFT_MASK_BUG_ON(regs, regs_irqs_disabled(regs) && search_kernel_restart_table(regs->nip)); } - INT_SOFT_MASK_BUG_ON(regs, !arch_irq_disabled_regs(regs) && + INT_SOFT_MASK_BUG_ON(regs, !regs_irqs_disabled(regs) && !(regs->msr & MSR_EE)); =20 booke_restore_dbcr0(); @@ -298,7 +298,7 @@ static inline void interrupt_nmi_enter_prepare(struct p= t_regs *regs, struct inte * Adjust regs->softe to be soft-masked if it had not been * reconcied (e.g., interrupt entry with MSR[EE]=3D0 but softe * not yet set disabled), or if it was in an implicit soft - * masked state. This makes arch_irq_disabled_regs(regs) + * masked state. This makes regs_irqs_disabled(regs) * behave as expected. */ regs->softe =3D IRQS_ALL_DISABLED; @@ -372,7 +372,7 @@ static inline void interrupt_nmi_exit_prepare(struct pt= _regs *regs, struct inter =20 #ifdef CONFIG_PPC64 #ifdef CONFIG_PPC_BOOK3S - if (arch_irq_disabled_regs(regs)) { + if (regs_irqs_disabled(regs)) { unsigned long rst =3D search_kernel_restart_table(regs->nip); if (rst) regs_set_return_ip(regs, rst); @@ -661,7 +661,7 @@ void replay_soft_interrupts(void); =20 static inline void interrupt_cond_local_irq_enable(struct pt_regs *regs) { - if (!arch_irq_disabled_regs(regs)) + if (!regs_irqs_disabled(regs)) local_irq_enable(); } =20 diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrup= t.c index e0c681d0b0763..0d8fd47049a19 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -347,7 +347,7 @@ notrace unsigned long interrupt_exit_user_prepare(struc= t pt_regs *regs) unsigned long ret; =20 BUG_ON(regs_is_unrecoverable(regs)); - BUG_ON(arch_irq_disabled_regs(regs)); + BUG_ON(regs_irqs_disabled(regs)); CT_WARN_ON(ct_state() =3D=3D CT_STATE_USER); =20 /* @@ -396,7 +396,7 @@ notrace unsigned long interrupt_exit_kernel_prepare(str= uct pt_regs *regs) =20 local_irq_disable(); =20 - if (!arch_irq_disabled_regs(regs)) { + if (!regs_irqs_disabled(regs)) { /* Returning to a kernel context with local irqs enabled. */ WARN_ON_ONCE(!(regs->msr & MSR_EE)); again: diff --git a/arch/powerpc/kernel/syscall.c b/arch/powerpc/kernel/syscall.c index be159ad4b77bd..9f03a6263fb41 100644 --- a/arch/powerpc/kernel/syscall.c +++ b/arch/powerpc/kernel/syscall.c @@ -32,7 +32,7 @@ notrace long system_call_exception(struct pt_regs *regs, = unsigned long r0) =20 BUG_ON(regs_is_unrecoverable(regs)); BUG_ON(!user_mode(regs)); - BUG_ON(arch_irq_disabled_regs(regs)); + BUG_ON(regs_irqs_disabled(regs)); =20 #ifdef CONFIG_PPC_PKEY if (mmu_has_feature(MMU_FTR_PKEY)) { diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index cb8e9357383e9..629f2a2d4780e 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -1956,7 +1956,7 @@ DEFINE_INTERRUPT_HANDLER_RAW(performance_monitor_exce= ption) * prevent hash faults on user addresses when reading callchains (and * looks better from an irq tracing perspective). */ - if (IS_ENABLED(CONFIG_PPC64) && unlikely(arch_irq_disabled_regs(regs))) + if (IS_ENABLED(CONFIG_PPC64) && unlikely(regs_irqs_disabled(regs))) performance_monitor_exception_nmi(regs); else performance_monitor_exception_async(regs); diff --git a/arch/powerpc/kernel/watchdog.c b/arch/powerpc/kernel/watchdog.c index 2429cb1c7baa7..6111cbbde069d 100644 --- a/arch/powerpc/kernel/watchdog.c +++ b/arch/powerpc/kernel/watchdog.c @@ -373,7 +373,7 @@ DEFINE_INTERRUPT_HANDLER_NMI(soft_nmi_interrupt) u64 tb; =20 /* should only arrive from kernel, with irqs disabled */ - WARN_ON_ONCE(!arch_irq_disabled_regs(regs)); + WARN_ON_ONCE(!regs_irqs_disabled(regs)); =20 if (!cpumask_test_cpu(cpu, &wd_cpus_enabled)) return 0; diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3= s.c index 8b0081441f85d..f7518b7e30554 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -2482,7 +2482,7 @@ static void __perf_event_interrupt(struct pt_regs *re= gs) * will trigger a PMI after waking up from idle. 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Mon, 8 Sep 2025 21:03:46 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, deller@gmx.de, ldv@strace.io, macro@orcam.me.uk, charlie@rivosinc.com, akpm@linux-foundation.org, bigeasy@linutronix.de, ankur.a.arora@oracle.com, sshegde@linux.ibm.com, naveen@kernel.org, thomas.weissschuh@linutronix.de, Jason@zx2c4.com, peterz@infradead.org, tglx@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, oliver.upton@linux.dev, mark.barnett@arm.com, atrajeev@linux.vnet.ibm.com, rppt@kernel.org, coltonlewis@google.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [RFC V2 2/8] powerpc: Prepare to build with generic entry/exit framework Date: Tue, 9 Sep 2025 02:32:30 +0530 Message-ID: <20250908210235.137300-4-mchauras@linux.ibm.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250908210235.137300-2-mchauras@linux.ibm.com> References: <20250908210235.137300-2-mchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 4wfgnDpBLph_jDuwm8Yrv5N-n4OHqDwO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDIzNSBTYWx0ZWRfX4WzA5c3Gvj4i TDmTnmbM7Q+Rr8X7UOo9eQZaq2Pxiu72v6lSmRyDgHhPyA7HPU2aNydeUbu5qbrVJLQgiCV/wca I0ruQFKFB51PA1phLsp/8A4AZLHGgFY1ffBX35SGQPYySP7dKpqDxUHlRandiRIEhw1eFPx9SWd yHOTDJQM6BwHa9+Em7AA5H3eqIVW4o6IVjwvcWl4lgdu0l7fRojdRCdDRii/xzua7CqbVbVj7ce PzGL+rx44GhuhJs3Gbs1Di0opjKHCFaqis5S2xd1/oopgNMuWXSAJvgJDKiFiBY2BlWKRB+qWC0 151VEBTivy08Z/D0C7kDaBpOE0MimowHEXkGfLK+I4AvgMXzeOO+B/rAGm0+dfth12PXVwC0R/V 0B8HOc1Q X-Proofpoint-GUID: kmjlrILui_QY0F368KmxE_h1tKHVoW0J X-Authority-Analysis: v=2.4 cv=F59XdrhN c=1 sm=1 tr=0 ts=68bf44c1 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=d-Ijs9cN_SKXjrDOqSQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1011 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060235 Enabling build with generic entry/exit framework for powerpc architecture requires few necessary steps. Introducing minor infrastructure updates to prepare for future generic framework handling: - Add syscall_work field to struct thread_info for SYSCALL_WORK_* flags. - Provide arch_syscall_is_vdso_sigreturn() stub, returning false. - Add on_thread_stack() helper to test whether the current stack pointer lies within the task=E2=80=99s kernel stack. No functional change is intended with this patch. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/include/asm/entry-common.h | 11 +++++++++++ arch/powerpc/include/asm/stacktrace.h | 8 ++++++++ arch/powerpc/include/asm/syscall.h | 5 +++++ arch/powerpc/include/asm/thread_info.h | 1 + 4 files changed, 25 insertions(+) create mode 100644 arch/powerpc/include/asm/entry-common.h diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h new file mode 100644 index 0000000000000..3af16d821d07e --- /dev/null +++ b/arch/powerpc/include/asm/entry-common.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_PPC_ENTRY_COMMON_H +#define _ASM_PPC_ENTRY_COMMON_H + +#ifdef CONFIG_GENERIC_IRQ_ENTRY + +#include + +#endif /* CONFIG_GENERIC_IRQ_ENTRY */ +#endif /* _ASM_PPC_ENTRY_COMMON_H */ diff --git a/arch/powerpc/include/asm/stacktrace.h b/arch/powerpc/include/a= sm/stacktrace.h index 6149b53b3bc8e..3f0a242468813 100644 --- a/arch/powerpc/include/asm/stacktrace.h +++ b/arch/powerpc/include/asm/stacktrace.h @@ -8,6 +8,14 @@ #ifndef _ASM_POWERPC_STACKTRACE_H #define _ASM_POWERPC_STACKTRACE_H =20 +#include + void show_user_instructions(struct pt_regs *regs); =20 +static inline bool on_thread_stack(void) +{ + return !(((unsigned long)(current->stack) ^ current_stack_pointer) + & ~(THREAD_SIZE -1)); +} + #endif /* _ASM_POWERPC_STACKTRACE_H */ diff --git a/arch/powerpc/include/asm/syscall.h b/arch/powerpc/include/asm/= syscall.h index 4b3c52ed6e9d2..834fcc4f7b543 100644 --- a/arch/powerpc/include/asm/syscall.h +++ b/arch/powerpc/include/asm/syscall.h @@ -139,4 +139,9 @@ static inline int syscall_get_arch(struct task_struct *= task) else return AUDIT_ARCH_PPC64; } + +static inline bool arch_syscall_is_vdso_sigreturn(struct pt_regs *regs) +{ + return false; +} #endif /* _ASM_SYSCALL_H */ diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/= asm/thread_info.h index 2785c7462ebf7..d0e87c9bae0b0 100644 --- a/arch/powerpc/include/asm/thread_info.h +++ b/arch/powerpc/include/asm/thread_info.h @@ -54,6 +54,7 @@ struct thread_info { int preempt_count; /* 0 =3D> preemptable, <0 =3D> BUG */ + unsigned long syscall_work; /* SYSCALL_WORK_ flags */ #ifdef CONFIG_SMP unsigned int cpu; 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Mon, 8 Sep 2025 21:04:14 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B9F4A20049; Mon, 8 Sep 2025 21:04:14 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E338420040; Mon, 8 Sep 2025 21:04:06 +0000 (GMT) Received: from li-e1dea04c-3555-11b2-a85c-f57333552245.ibm.com.com (unknown [9.39.29.251]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 21:04:06 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, deller@gmx.de, ldv@strace.io, macro@orcam.me.uk, charlie@rivosinc.com, akpm@linux-foundation.org, bigeasy@linutronix.de, ankur.a.arora@oracle.com, sshegde@linux.ibm.com, naveen@kernel.org, thomas.weissschuh@linutronix.de, Jason@zx2c4.com, peterz@infradead.org, tglx@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, oliver.upton@linux.dev, mark.barnett@arm.com, atrajeev@linux.vnet.ibm.com, rppt@kernel.org, coltonlewis@google.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [RFC V2 3/8] powerpc: introduce arch_enter_from_user_mode Date: Tue, 9 Sep 2025 02:32:31 +0530 Message-ID: <20250908210235.137300-5-mchauras@linux.ibm.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250908210235.137300-2-mchauras@linux.ibm.com> References: <20250908210235.137300-2-mchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAxMCBTYWx0ZWRfX/okvS8um5doc f6ex77ml23LL3HK2/kO8Z4Ii6t2aE7E0TK4mhNKWw+l3jUIWL93NijhSlkxa8EIdGgFAoN4/zjc Foy74kmhDs+G9JOzmMunqSxMhgqQDAno+pLDjVUccXmMMq13iLD2rc1JN5XZtexJlviTFw+2xnk PQjb6j17TI5vf0PrvZWJqFHU5nNs5WaUYj1C9YkJi1/HdOf/avhB5Q+NfkEipqFJc1hqFo2u+Vd 9zYSLyTld7CCl69HRvjAqaY7E0C/iOKi6V52c7ZtKoNmB3zuMO5unPB15grln7B29u2vT0gXRAM 6EX7kx0O1kV1dI62dnM6CX82W4HIRaTxgaedKYvCY5SjjhhHnBWhDajFh1A6EVs3sbA7ZRbBeO8 s6GgMJPD X-Authority-Analysis: v=2.4 cv=SKNCVPvH c=1 sm=1 tr=0 ts=68bf44d4 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=_bLvTq7iIsdV134y72cA:9 X-Proofpoint-GUID: sl51tC8nna07i3ZnbQptd-o3AIfEGb7a X-Proofpoint-ORIG-GUID: Khy0z-eh1A2eIlIonVaNbcHPHmo4L6Wj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 adultscore=0 suspectscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060010 Content-Type: text/plain; charset="utf-8" - Implement the hook arch_enter_from_user_mode for syscall entry. - Move booke_load_dbcr0 from interrupt.c to interrupt.h No functional change intended. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/include/asm/entry-common.h | 96 +++++++++++++++++++++++++ arch/powerpc/include/asm/interrupt.h | 23 ++++++ arch/powerpc/kernel/interrupt.c | 22 ------ 3 files changed, 119 insertions(+), 22 deletions(-) diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h index 3af16d821d07e..49607292bf5a5 100644 --- a/arch/powerpc/include/asm/entry-common.h +++ b/arch/powerpc/include/asm/entry-common.h @@ -5,7 +5,103 @@ =20 #ifdef CONFIG_GENERIC_IRQ_ENTRY =20 +#include +#include #include +#include + +static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) +{ + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) + BUG_ON(irq_soft_mask_return() !=3D IRQS_ALL_DISABLED); + + BUG_ON(regs_is_unrecoverable(regs)); + BUG_ON(!user_mode(regs)); + BUG_ON(regs_irqs_disabled(regs)); + +#ifdef CONFIG_PPC_PKEY + if (mmu_has_feature(MMU_FTR_PKEY)) { + unsigned long amr, iamr; + bool flush_needed =3D false; + /* + * When entering from userspace we mostly have the AMR/IAMR + * different from kernel default values. Hence don't compare. + */ + amr =3D mfspr(SPRN_AMR); + iamr =3D mfspr(SPRN_IAMR); + regs->amr =3D amr; + regs->iamr =3D iamr; + if (mmu_has_feature(MMU_FTR_KUAP)) { + mtspr(SPRN_AMR, AMR_KUAP_BLOCKED); + flush_needed =3D true; + } + if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) { + mtspr(SPRN_IAMR, AMR_KUEP_BLOCKED); + flush_needed =3D true; + } + if (flush_needed) + isync(); + } else +#endif + kuap_assert_locked(); + + booke_restore_dbcr0(); + + account_cpu_user_entry(); + + account_stolen_time(); + + /* + * This is not required for the syscall exit path, but makes the + * stack frame look nicer. If this was initialised in the first stack + * frame, or if the unwinder was taught the first stack frame always + * returns to user with IRQS_ENABLED, this store could be avoided! + */ + irq_soft_mask_regs_set_state(regs, IRQS_ENABLED); + + /* + * If system call is called with TM active, set _TIF_RESTOREALL to + * prevent RFSCV being used to return to userspace, because POWER9 + * TM implementation has problems with this instruction returning to + * transactional state. Final register values are not relevant because + * the transaction will be aborted upon return anyway. Or in the case + * of unsupported_scv SIGILL fault, the return state does not much + * matter because it's an edge case. + */ + if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && + unlikely(MSR_TM_TRANSACTIONAL(regs->msr))) + set_bits(_TIF_RESTOREALL, ¤t_thread_info()->flags); + + /* + * If the system call was made with a transaction active, doom it and + * return without performing the system call. Unless it was an + * unsupported scv vector, in which case it's treated like an illegal + * instruction. + */ +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + if (unlikely(MSR_TM_TRANSACTIONAL(regs->msr)) && + !trap_is_unsupported_scv(regs)) { + /* Enable TM in the kernel, and disable EE (for scv) */ + hard_irq_disable(); + mtmsr(mfmsr() | MSR_TM); + + /* tabort, this dooms the transaction, nothing else */ + asm volatile(".long 0x7c00071d | ((%0) << 16)" + :: "r"(TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)); + + /* + * Userspace will never see the return value. Execution will + * resume after the tbegin. of the aborted transaction with the + * checkpointed register state. A context switch could occur + * or signal delivered to the process before resuming the + * doomed transaction context, but that should all be handled + * as expected. + */ + return; + } +#endif // CONFIG_PPC_TRANSACTIONAL_MEM +} +#define arch_enter_from_user_mode arch_enter_from_user_mode =20 #endif /* CONFIG_GENERIC_IRQ_ENTRY */ #endif /* _ASM_PPC_ENTRY_COMMON_H */ diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/as= m/interrupt.h index 56bc8113b8cde..6edf064a0fea2 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -138,6 +138,29 @@ static inline void nap_adjust_return(struct pt_regs *r= egs) #endif } =20 +static inline void booke_load_dbcr0(void) +{ +#ifdef CONFIG_PPC_ADV_DEBUG_REGS + unsigned long dbcr0 =3D current->thread.debug.dbcr0; + + if (likely(!(dbcr0 & DBCR0_IDM))) + return; + + /* + * Check to see if the dbcr0 register is set up to debug. + * Use the internal debug mode bit to do this. + */ + mtmsr(mfmsr() & ~MSR_DE); + if (IS_ENABLED(CONFIG_PPC32)) { + isync(); + global_dbcr0[smp_processor_id()] =3D mfspr(SPRN_DBCR0); + } + mtspr(SPRN_DBCR0, dbcr0); + mtspr(SPRN_DBSR, -1); +#endif +} + + static inline void booke_restore_dbcr0(void) { #ifdef CONFIG_PPC_ADV_DEBUG_REGS diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrup= t.c index 0d8fd47049a19..2a09ac5dabd62 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -78,28 +78,6 @@ static notrace __always_inline bool prep_irq_for_enabled= _exit(bool restartable) return true; } =20 -static notrace void booke_load_dbcr0(void) -{ -#ifdef CONFIG_PPC_ADV_DEBUG_REGS - unsigned long dbcr0 =3D current->thread.debug.dbcr0; - - if (likely(!(dbcr0 & DBCR0_IDM))) - return; - - /* - * Check to see if the dbcr0 register is set up to debug. - * Use the internal debug mode bit to do this. - */ - mtmsr(mfmsr() & ~MSR_DE); - if (IS_ENABLED(CONFIG_PPC32)) { - isync(); - global_dbcr0[smp_processor_id()] =3D mfspr(SPRN_DBCR0); - } - mtspr(SPRN_DBCR0, dbcr0); - mtspr(SPRN_DBSR, -1); -#endif -} - static notrace void check_return_regs_valid(struct pt_regs *regs) { #ifdef CONFIG_PPC_BOOK3S_64 --=20 2.51.0 From nobody Wed Sep 10 01:55:30 2025 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F403F1E500C for ; Mon, 8 Sep 2025 21:05:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757365516; cv=none; b=cnwDgjloSq+mu9DBQ36UPmsUBLijcChrYrqANi6cSZjfxATYAcqmb3LEXOcpMAw80rE/KNoTgr/svmaR6bXE3EJTwTkC8GzX/tQAltIAot7E8BqGVwBMmwsNKtQJXK/dJAgLTiu9/GgzfR+k0SmfB2VV0KZPFAZAaXLJmHBqVOs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757365516; c=relaxed/simple; bh=WSuAv0FKT2XFS/Gcq1N0uVU1uFjx7nNI3LTbacLH360=; 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Mon, 8 Sep 2025 21:04:25 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, deller@gmx.de, ldv@strace.io, macro@orcam.me.uk, charlie@rivosinc.com, akpm@linux-foundation.org, bigeasy@linutronix.de, ankur.a.arora@oracle.com, sshegde@linux.ibm.com, naveen@kernel.org, thomas.weissschuh@linutronix.de, Jason@zx2c4.com, peterz@infradead.org, tglx@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, oliver.upton@linux.dev, mark.barnett@arm.com, atrajeev@linux.vnet.ibm.com, rppt@kernel.org, coltonlewis@google.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [RFC V2 4/8] powerpc: Introduce syscall exit arch functions Date: Tue, 9 Sep 2025 02:32:32 +0530 Message-ID: <20250908210235.137300-6-mchauras@linux.ibm.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250908210235.137300-2-mchauras@linux.ibm.com> References: <20250908210235.137300-2-mchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 4Bj-9TghBmUhfEHrdvtFk5HtcJNUiDJw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDIzNSBTYWx0ZWRfX9Lga+NETD4/k +Ttnrl13KtsiDlDSoCxDE5MPl15Ywt4DAwxRdiHzhHlqocs6F/OnUmFf12sBa+mmQygRPF+bZLG dX+O6thbuaEF6+jyO18FlIHKgb9m1viZvE/k4MmHHLKw61WPGxlo0mPOxqPDV10RhVw3ljICzIo 2wuO4T1OnIlj/I8gANcYt6MCm/S9xjrcA3irZHY5EUctNAK3aQ04OpthkpsoOA4lXRCRuQRvCS/ JHZxPX/BtpSC5reLHzBNcx3Nktxnbq3l97p5W9GaRTgiy8fQloXqwm5KOM0XtZ+2EkCSQxWrYbi 8/wxLfEPC4DmqC6dRYbXmq2Cl/DU8LjBSxc+rO2PD28ahlEeGXBA7HxYTKOO/R4piM2JO2nMGi/ JZCMxxHN X-Proofpoint-GUID: _IvYmWnV2d2YD5dXPf3gkNtGR0n2yTDz X-Authority-Analysis: v=2.4 cv=F59XdrhN c=1 sm=1 tr=0 ts=68bf44e7 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=azVfos6laG1Ide8r4ucA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1011 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060235 Content-Type: text/plain; charset="utf-8" Introducing following functions for syscall exit - arch_exit_to_user_mode_work - arch_exit_to_user_mode_work_prepare Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/include/asm/entry-common.h | 46 ++++++++++++++ arch/powerpc/include/asm/interrupt.h | 82 +++++++++++++++++++++++++ arch/powerpc/kernel/interrupt.c | 81 ------------------------ arch/powerpc/kernel/signal.c | 14 +++++ 4 files changed, 142 insertions(+), 81 deletions(-) diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h index 49607292bf5a5..adea093274279 100644 --- a/arch/powerpc/include/asm/entry-common.h +++ b/arch/powerpc/include/asm/entry-common.h @@ -8,6 +8,7 @@ #include #include #include +#include #include =20 static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) @@ -101,7 +102,52 @@ static __always_inline void arch_enter_from_user_mode(= struct pt_regs *regs) } #endif // CONFIG_PPC_TRANSACTIONAL_MEM } + #define arch_enter_from_user_mode arch_enter_from_user_mode =20 +static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, + unsigned long ti_work) +{ + unsigned long mathflags; + + if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && IS_ENABLED(CONFIG_PPC_FPU)) { + if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && + unlikely((ti_work & _TIF_RESTORE_TM))) { + restore_tm_state(regs); + } else { + mathflags =3D MSR_FP; + + if (cpu_has_feature(CPU_FTR_VSX)) + mathflags |=3D MSR_VEC | MSR_VSX; + else if (cpu_has_feature(CPU_FTR_ALTIVEC)) + mathflags |=3D MSR_VEC; + + /* + * If userspace MSR has all available FP bits set, + * then they are live and no need to restore. If not, + * it means the regs were given up and restore_math + * may decide to restore them (to avoid taking an FP + * fault). + */ + if ((regs->msr & mathflags) !=3D mathflags) + restore_math(regs); + } + } + + check_return_regs_valid(regs); +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + local_paca->tm_scratch =3D regs->msr; +#endif +} +#define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare + +static __always_inline void arch_exit_to_user_mode(void) +{ + booke_load_dbcr0(); + + account_cpu_user_exit(); +} +#define arch_exit_to_user_mode arch_exit_to_user_mode + #endif /* CONFIG_GENERIC_IRQ_ENTRY */ #endif /* _ASM_PPC_ENTRY_COMMON_H */ diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/as= m/interrupt.h index 6edf064a0fea2..c6ab286a723f2 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -68,6 +68,8 @@ =20 #include #include +#include /* for show_regs */ + #include #include #include @@ -173,6 +175,86 @@ static inline void booke_restore_dbcr0(void) #endif } =20 +static inline void check_return_regs_valid(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC_BOOK3S_64 + unsigned long trap, srr0, srr1; + static bool warned; + u8 *validp; + char *h; + + if (trap_is_scv(regs)) + return; + + trap =3D TRAP(regs); + // EE in HV mode sets HSRRs like 0xea0 + if (cpu_has_feature(CPU_FTR_HVMODE) && trap =3D=3D INTERRUPT_EXTERNAL) + trap =3D 0xea0; + + switch (trap) { + case 0x980: + case INTERRUPT_H_DATA_STORAGE: + case 0xe20: + case 0xe40: + case INTERRUPT_HMI: + case 0xe80: + case 0xea0: + case INTERRUPT_H_FAC_UNAVAIL: + case 0x1200: + case 0x1500: + case 0x1600: + case 0x1800: + validp =3D &local_paca->hsrr_valid; + if (!READ_ONCE(*validp)) + return; + + srr0 =3D mfspr(SPRN_HSRR0); + srr1 =3D mfspr(SPRN_HSRR1); + h =3D "H"; + + break; + default: + validp =3D &local_paca->srr_valid; + if (!READ_ONCE(*validp)) + return; + + srr0 =3D mfspr(SPRN_SRR0); + srr1 =3D mfspr(SPRN_SRR1); + h =3D ""; + break; + } + + if (srr0 =3D=3D regs->nip && srr1 =3D=3D regs->msr) + return; + + /* + * A NMI / soft-NMI interrupt may have come in after we found + * srr_valid and before the SRRs are loaded. The interrupt then + * comes in and clobbers SRRs and clears srr_valid. Then we load + * the SRRs here and test them above and find they don't match. + * + * Test validity again after that, to catch such false positives. + * + * This test in general will have some window for false negatives + * and may not catch and fix all such cases if an NMI comes in + * later and clobbers SRRs without clearing srr_valid, but hopefully + * such things will get caught most of the time, statistically + * enough to be able to get a warning out. + */ + if (!READ_ONCE(*validp)) + return; + + if (!data_race(warned)) { + data_race(warned =3D true); + printk("%sSRR0 was: %lx should be: %lx\n", h, srr0, regs->nip); + printk("%sSRR1 was: %lx should be: %lx\n", h, srr1, regs->msr); + show_regs(regs); + } + + WRITE_ONCE(*validp, 0); /* fixup */ +#endif +} + static inline void interrupt_enter_prepare(struct pt_regs *regs) { #ifdef CONFIG_PPC64 diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrup= t.c index 2a09ac5dabd62..f53d432f60870 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -4,7 +4,6 @@ #include #include #include -#include /* for show_regs */ =20 #include #include @@ -78,86 +77,6 @@ static notrace __always_inline bool prep_irq_for_enabled= _exit(bool restartable) return true; } =20 -static notrace void check_return_regs_valid(struct pt_regs *regs) -{ -#ifdef CONFIG_PPC_BOOK3S_64 - unsigned long trap, srr0, srr1; - static bool warned; - u8 *validp; - char *h; - - if (trap_is_scv(regs)) - return; - - trap =3D TRAP(regs); - // EE in HV mode sets HSRRs like 0xea0 - if (cpu_has_feature(CPU_FTR_HVMODE) && trap =3D=3D INTERRUPT_EXTERNAL) - trap =3D 0xea0; - - switch (trap) { - case 0x980: - case INTERRUPT_H_DATA_STORAGE: - case 0xe20: - case 0xe40: - case INTERRUPT_HMI: - case 0xe80: - case 0xea0: - case INTERRUPT_H_FAC_UNAVAIL: - case 0x1200: - case 0x1500: - case 0x1600: - case 0x1800: - validp =3D &local_paca->hsrr_valid; - if (!READ_ONCE(*validp)) - return; - - srr0 =3D mfspr(SPRN_HSRR0); - srr1 =3D mfspr(SPRN_HSRR1); - h =3D "H"; - - break; - default: - validp =3D &local_paca->srr_valid; - if (!READ_ONCE(*validp)) - return; - - srr0 =3D mfspr(SPRN_SRR0); - srr1 =3D mfspr(SPRN_SRR1); - h =3D ""; - break; - } - - if (srr0 =3D=3D regs->nip && srr1 =3D=3D regs->msr) - return; - - /* - * A NMI / soft-NMI interrupt may have come in after we found - * srr_valid and before the SRRs are loaded. The interrupt then - * comes in and clobbers SRRs and clears srr_valid. Then we load - * the SRRs here and test them above and find they don't match. - * - * Test validity again after that, to catch such false positives. - * - * This test in general will have some window for false negatives - * and may not catch and fix all such cases if an NMI comes in - * later and clobbers SRRs without clearing srr_valid, but hopefully - * such things will get caught most of the time, statistically - * enough to be able to get a warning out. - */ - if (!READ_ONCE(*validp)) - return; - - if (!data_race(warned)) { - data_race(warned =3D true); - printk("%sSRR0 was: %lx should be: %lx\n", h, srr0, regs->nip); - printk("%sSRR1 was: %lx should be: %lx\n", h, srr1, regs->msr); - show_regs(regs); - } - - WRITE_ONCE(*validp, 0); /* fixup */ -#endif -} - static notrace unsigned long interrupt_exit_user_prepare_main(unsigned long ret, struct pt_regs *regs) { diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c index aa17e62f37547..719930cf4ae1f 100644 --- a/arch/powerpc/kernel/signal.c +++ b/arch/powerpc/kernel/signal.c @@ -22,6 +22,11 @@ =20 #include "signal.h" =20 +/* This will be removed */ +#ifdef CONFIG_GENERIC_ENTRY +#include +#endif /* CONFIG_GENERIC_ENTRY */ + #ifdef CONFIG_VSX unsigned long copy_fpr_to_user(void __user *to, struct task_struct *task) @@ -368,3 +373,12 @@ void signal_fault(struct task_struct *tsk, struct pt_r= egs *regs, printk_ratelimited(regs->msr & MSR_64BIT ? fm64 : fm32, tsk->comm, task_pid_nr(tsk), where, ptr, regs->nip, regs->link); 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Mon, 8 Sep 2025 21:04:48 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, deller@gmx.de, ldv@strace.io, macro@orcam.me.uk, charlie@rivosinc.com, akpm@linux-foundation.org, bigeasy@linutronix.de, ankur.a.arora@oracle.com, sshegde@linux.ibm.com, naveen@kernel.org, thomas.weissschuh@linutronix.de, Jason@zx2c4.com, peterz@infradead.org, tglx@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, oliver.upton@linux.dev, mark.barnett@arm.com, atrajeev@linux.vnet.ibm.com, rppt@kernel.org, coltonlewis@google.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [RFC V2 5/8] powerpc: add exit_flags field in pt_regs Date: Tue, 9 Sep 2025 02:32:34 +0530 Message-ID: <20250908210235.137300-8-mchauras@linux.ibm.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250908210235.137300-2-mchauras@linux.ibm.com> References: <20250908210235.137300-2-mchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: jkKsyjvGir4z3RvpuBQnKCDKtgLl8i39 X-Proofpoint-ORIG-GUID: 9-e9VtYvjpNZQogMLAfnK9TfNvGzeux8 X-Authority-Analysis: v=2.4 cv=J52q7BnS c=1 sm=1 tr=0 ts=68bf44fe cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=0jsHHNn5x11Jhr2ultEA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAyNSBTYWx0ZWRfX8e8yUUev7/Cm KTB1Db+mhPUq0frlBlYjIpp1dguyxvyjKvDQWbnOGFQ/qCJSC5tqjvHNBSlYXxBRQaClKF0oL1U yZ8b5NUYEG5pUUd8GcJ7gck4q/xX0tE+mKaGkhMbDcPO1xGtuz/eA+eFVaC3P/WZiHRlS5l5uPn KP4+yLvRGwkeE1I+KKkV2hag3CFGJzIfEW1ebRiU+DaCJ81S/gNUEogxOCwLP2uMG7/We6M09Se /sSp4GB67gisNkAl2yg1hEFeieofrI/m70tfgDa8CnoYN16nfTXm+JF3hLnvRaYy5/HizllYHTG 9kCqJHOzPd3N2szGHdLxZbN781awyxSiV9O7iU4Sgd1EAqxHfL+86AsltXCYRhl4QbSnkJ/iUeG ZlroJ+Cs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060025 Content-Type: text/plain; charset="utf-8" Add field exit_flags in the pt_regs. This will hold the flags while executing interrupt or syscall which is required during exit to user. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/include/asm/ptrace.h | 2 ++ arch/powerpc/include/uapi/asm/ptrace.h | 14 +++++++++----- arch/powerpc/kernel/asm-offsets.c | 1 + arch/powerpc/kernel/ptrace/ptrace.c | 1 + 4 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/p= trace.h index 7b9350756875a..1b0ad5088f60d 100644 --- a/arch/powerpc/include/asm/ptrace.h +++ b/arch/powerpc/include/asm/ptrace.h @@ -53,6 +53,8 @@ struct pt_regs unsigned long esr; }; unsigned long result; + unsigned long exit_flags; + unsigned long __pt_regs_pad[1]; /* Maintain 16 byte interrupt stack ali= gnment */ }; }; #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_KUAP) diff --git a/arch/powerpc/include/uapi/asm/ptrace.h b/arch/powerpc/include/= uapi/asm/ptrace.h index 7004cfea3f5ff..4de612e2e40ac 100644 --- a/arch/powerpc/include/uapi/asm/ptrace.h +++ b/arch/powerpc/include/uapi/asm/ptrace.h @@ -55,6 +55,8 @@ struct pt_regs unsigned long dar; /* Fault registers */ unsigned long dsisr; /* on 4xx/Book-E used for ESR */ unsigned long result; /* Result of a system call */ + unsigned long exit_flags; /* System call exit flags */ + unsigned long __pt_regs_pad[1]; /* Maintain 16 byte interrupt stack align= ment */ }; =20 #endif /* __ASSEMBLY__ */ @@ -114,10 +116,12 @@ struct pt_regs #define PT_DAR 41 #define PT_DSISR 42 #define PT_RESULT 43 -#define PT_DSCR 44 -#define PT_REGS_COUNT 44 +#define PT_EXIT_FLAGS 44 +#define PT_PAD 45 +#define PT_DSCR 46 +#define PT_REGS_COUNT 46 =20 -#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR0 (PT_REGS_COUNT + 4) /* each FP reg occupies 2 slots in thi= s space */ =20 #ifndef __powerpc64__ =20 @@ -129,7 +133,7 @@ struct pt_regs #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit s= pace */ =20 =20 -#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */ +#define PT_VR0 (PT_FPSCR + 2) /* <82> each Vector reg occupies 2 slots in = 64-bit */ #define PT_VSCR (PT_VR0 + 32*2 + 1) #define PT_VRSAVE (PT_VR0 + 33*2) =20 @@ -137,7 +141,7 @@ struct pt_regs /* * Only store first 32 VSRs here. The second 32 VSRs in VR0-31 */ -#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */ +#define PT_VSR0 (PT_VRSAVE + 2) /* each VSR reg occupies 2 slots in 64-bit= */ #define PT_VSR31 (PT_VSR0 + 2*31) #endif /* __powerpc64__ */ =20 diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-of= fsets.c index b3048f6d3822c..4d4e880e3c616 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -291,6 +291,7 @@ int main(void) STACK_PT_REGS_OFFSET(_ESR, esr); STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3); STACK_PT_REGS_OFFSET(RESULT, result); + STACK_PT_REGS_OFFSET(EXIT_FLAGS, exit_flags); STACK_PT_REGS_OFFSET(_TRAP, trap); #ifdef CONFIG_PPC64 STACK_PT_REGS_OFFSET(SOFTE, softe); diff --git a/arch/powerpc/kernel/ptrace/ptrace.c b/arch/powerpc/kernel/ptra= ce/ptrace.c index c6997df632873..2134b6d155ff6 100644 --- a/arch/powerpc/kernel/ptrace/ptrace.c +++ b/arch/powerpc/kernel/ptrace/ptrace.c @@ -432,6 +432,7 @@ void __init pt_regs_check(void) CHECK_REG(PT_DAR, dar); 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Mon, 8 Sep 2025 21:04:59 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, deller@gmx.de, ldv@strace.io, macro@orcam.me.uk, charlie@rivosinc.com, akpm@linux-foundation.org, bigeasy@linutronix.de, ankur.a.arora@oracle.com, sshegde@linux.ibm.com, naveen@kernel.org, thomas.weissschuh@linutronix.de, Jason@zx2c4.com, peterz@infradead.org, tglx@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, oliver.upton@linux.dev, mark.barnett@arm.com, atrajeev@linux.vnet.ibm.com, rppt@kernel.org, coltonlewis@google.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [RFC V2 6/8] powerpc: Prepare for IRQ entry exit Date: Tue, 9 Sep 2025 02:32:35 +0530 Message-ID: <20250908210235.137300-9-mchauras@linux.ibm.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250908210235.137300-2-mchauras@linux.ibm.com> References: <20250908210235.137300-2-mchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDE5NSBTYWx0ZWRfXwi3HvJWb5EUT HBNFeVlexgdD32cDdr9z8rUTjciriwolbak8MamQJn9kNbZR9LaMMjZwxqnZAPboUBdyBDb6XOF fDyKhQ163XgFwjTNaUqJl2qMTN843luejx+wKAI/IQzEliphpt0RgXuCNYv32S2aJGOHy+5ct2Q YxyrmIkPs2LI2VFpiSXpCtOLYYwAr+Ura3+hDrUNAXTF6s1WCIxeG+/gEBJEUE+8kVm4pFnkDE4 EnwpKjePqIlBBOWS6swPY2zgRj7NZ8wdVe1gREi+jfrnq/XfInCQ3KzoR81gUFZpBZsT7iOJOmt HEvo3GZQKfqnN1qauSCXmQyYffBg2s5CLIZ8J9kxZrQ6nn2a19Ec799dA9rfDCQEc8S9fGqPobi oSOXKQbU X-Proofpoint-ORIG-GUID: Z5XV8RqqUiLkGd6TiKpalA8uJ8S_wV2_ X-Proofpoint-GUID: zcO2hPjJ8W-2X_7xpBojaARW7nRxdaDv X-Authority-Analysis: v=2.4 cv=StCQ6OO0 c=1 sm=1 tr=0 ts=68bf450a cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=QKOP9i3fA86Xk_0DPdgA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060195 Content-Type: text/plain; charset="utf-8" Copy all the functions from interrupt.h to arch specific entry-common.h file as it will be a part of common now. No functional change intended here. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/include/asm/entry-common.h | 420 ++++++++++++++++++++++++ 1 file changed, 420 insertions(+) diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h index adea093274279..28a96a84e83b5 100644 --- a/arch/powerpc/include/asm/entry-common.h +++ b/arch/powerpc/include/asm/entry-common.h @@ -7,10 +7,430 @@ =20 #include #include +#include #include #include #include =20 +#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG +/* + * WARN/BUG is handled with a program interrupt so minimise checks here to + * avoid recursion and maximise the chance of getting the first oops handl= ed. + */ +#define INT_SOFT_MASK_BUG_ON(regs, cond) \ +do { \ + if ((user_mode(regs) || (TRAP(regs) !=3D INTERRUPT_PROGRAM))) \ + BUG_ON(cond); \ +} while (0) +#else +#define INT_SOFT_MASK_BUG_ON(regs, cond) +#endif + +#ifdef CONFIG_PPC_BOOK3S_64 +extern char __end_soft_masked[]; +bool search_kernel_soft_mask_table(unsigned long addr); +unsigned long search_kernel_restart_table(unsigned long addr); + +DECLARE_STATIC_KEY_FALSE(interrupt_exit_not_reentrant); + +static inline bool is_implicit_soft_masked(struct pt_regs *regs) +{ + if (user_mode(regs)) + return false; + + if (regs->nip >=3D (unsigned long)__end_soft_masked) + return false; + + return search_kernel_soft_mask_table(regs->nip); +} + +static inline void srr_regs_clobbered(void) +{ + local_paca->srr_valid =3D 0; + local_paca->hsrr_valid =3D 0; +} +#else +static inline unsigned long search_kernel_restart_table(unsigned long addr) +{ + return 0; +} + +static inline bool is_implicit_soft_masked(struct pt_regs *regs) +{ + return false; +} + +static inline void srr_regs_clobbered(void) +{ +} +#endif + +static inline void nap_adjust_return(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC_970_NAP + if (unlikely(test_thread_local_flags(_TLF_NAPPING))) { + /* Can avoid a test-and-clear because NMIs do not call this */ + clear_thread_local_flags(_TLF_NAPPING); + regs_set_return_ip(regs, (unsigned long)power4_idle_nap_return); + } +#endif +} + +static inline void booke_load_dbcr0(void) +{ +#ifdef CONFIG_PPC_ADV_DEBUG_REGS + unsigned long dbcr0 =3D current->thread.debug.dbcr0; + + if (likely(!(dbcr0 & DBCR0_IDM))) + return; + + /* + * Check to see if the dbcr0 register is set up to debug. + * Use the internal debug mode bit to do this. + */ + mtmsr(mfmsr() & ~MSR_DE); + if (IS_ENABLED(CONFIG_PPC32)) { + isync(); + global_dbcr0[smp_processor_id()] =3D mfspr(SPRN_DBCR0); + } + mtspr(SPRN_DBCR0, dbcr0); + mtspr(SPRN_DBSR, -1); +#endif +} + + +static inline void booke_restore_dbcr0(void) +{ +#ifdef CONFIG_PPC_ADV_DEBUG_REGS + unsigned long dbcr0 =3D current->thread.debug.dbcr0; + + if (IS_ENABLED(CONFIG_PPC32) && unlikely(dbcr0 & DBCR0_IDM)) { + mtspr(SPRN_DBSR, -1); + mtspr(SPRN_DBCR0, global_dbcr0[smp_processor_id()]); + } +#endif +} + +static inline void check_return_regs_valid(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC_BOOK3S_64 + unsigned long trap, srr0, srr1; + static bool warned; + u8 *validp; + char *h; + + if (trap_is_scv(regs)) + return; + + trap =3D TRAP(regs); + // EE in HV mode sets HSRRs like 0xea0 + if (cpu_has_feature(CPU_FTR_HVMODE) && trap =3D=3D INTERRUPT_EXTERNAL) + trap =3D 0xea0; + + switch (trap) { + case 0x980: + case INTERRUPT_H_DATA_STORAGE: + case 0xe20: + case 0xe40: + case INTERRUPT_HMI: + case 0xe80: + case 0xea0: + case INTERRUPT_H_FAC_UNAVAIL: + case 0x1200: + case 0x1500: + case 0x1600: + case 0x1800: + validp =3D &local_paca->hsrr_valid; + if (!READ_ONCE(*validp)) + return; + + srr0 =3D mfspr(SPRN_HSRR0); + srr1 =3D mfspr(SPRN_HSRR1); + h =3D "H"; + + break; + default: + validp =3D &local_paca->srr_valid; + if (!READ_ONCE(*validp)) + return; + + srr0 =3D mfspr(SPRN_SRR0); + srr1 =3D mfspr(SPRN_SRR1); + h =3D ""; + break; + } + + if (srr0 =3D=3D regs->nip && srr1 =3D=3D regs->msr) + return; + + /* + * A NMI / soft-NMI interrupt may have come in after we found + * srr_valid and before the SRRs are loaded. The interrupt then + * comes in and clobbers SRRs and clears srr_valid. Then we load + * the SRRs here and test them above and find they don't match. + * + * Test validity again after that, to catch such false positives. + * + * This test in general will have some window for false negatives + * and may not catch and fix all such cases if an NMI comes in + * later and clobbers SRRs without clearing srr_valid, but hopefully + * such things will get caught most of the time, statistically + * enough to be able to get a warning out. + */ + if (!READ_ONCE(*validp)) + return; + + if (!data_race(warned)) { + data_race(warned =3D true); + printk("%sSRR0 was: %lx should be: %lx\n", h, srr0, regs->nip); + printk("%sSRR1 was: %lx should be: %lx\n", h, srr1, regs->msr); + show_regs(regs); + } + + WRITE_ONCE(*validp, 0); /* fixup */ +#endif +} + +static inline void interrupt_enter_prepare(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC64 + irq_soft_mask_set(IRQS_ALL_DISABLED); + + /* + * If the interrupt was taken with HARD_DIS clear, then enable MSR[EE]. + * Asynchronous interrupts get here with HARD_DIS set (see below), so + * this enables MSR[EE] for synchronous interrupts. IRQs remain + * soft-masked. The interrupt handler may later call + * interrupt_cond_local_irq_enable() to achieve a regular process + * context. + */ + if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) { + INT_SOFT_MASK_BUG_ON(regs, !(regs->msr & MSR_EE)); + __hard_irq_enable(); + } else { + __hard_RI_enable(); + } + /* Enable MSR[RI] early, to support kernel SLB and hash faults */ +#endif + + if (!regs_irqs_disabled(regs)) + trace_hardirqs_off(); + + if (user_mode(regs)) { + kuap_lock(); + CT_WARN_ON(ct_state() !=3D CT_STATE_USER); + user_exit_irqoff(); + + account_cpu_user_entry(); + account_stolen_time(); + } else { + kuap_save_and_lock(regs); + /* + * CT_WARN_ON comes here via program_check_exception, + * so avoid recursion. + */ + if (TRAP(regs) !=3D INTERRUPT_PROGRAM) + CT_WARN_ON(ct_state() !=3D CT_STATE_KERNEL && + ct_state() !=3D CT_STATE_IDLE); + INT_SOFT_MASK_BUG_ON(regs, is_implicit_soft_masked(regs)); + INT_SOFT_MASK_BUG_ON(regs, regs_irqs_disabled(regs) && + search_kernel_restart_table(regs->nip)); + } + INT_SOFT_MASK_BUG_ON(regs, !regs_irqs_disabled(regs) && + !(regs->msr & MSR_EE)); + + booke_restore_dbcr0(); +} + +/* + * Care should be taken to note that interrupt_exit_prepare and + * interrupt_async_exit_prepare do not necessarily return immediately to + * regs context (e.g., if regs is usermode, we don't necessarily return to + * user mode). Other interrupts might be taken between here and return, + * context switch / preemption may occur in the exit path after this, or a + * signal may be delivered, etc. + * + * The real interrupt exit code is platform specific, e.g., + * interrupt_exit_user_prepare / interrupt_exit_kernel_prepare for 64s. + * + * However interrupt_nmi_exit_prepare does return directly to regs, because + * NMIs do not do "exit work" or replay soft-masked interrupts. + */ +static inline void interrupt_exit_prepare(struct pt_regs *regs) +{ +} + +static inline void interrupt_async_enter_prepare(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC64 + /* Ensure interrupt_enter_prepare does not enable MSR[EE] */ + local_paca->irq_happened |=3D PACA_IRQ_HARD_DIS; +#endif + interrupt_enter_prepare(regs); +#ifdef CONFIG_PPC_BOOK3S_64 + /* + * RI=3D1 is set by interrupt_enter_prepare, so this thread flags access + * has to come afterward (it can cause SLB faults). + */ + if (cpu_has_feature(CPU_FTR_CTRL) && + !test_thread_local_flags(_TLF_RUNLATCH)) + __ppc64_runlatch_on(); +#endif + irq_enter(); +} + +static inline void interrupt_async_exit_prepare(struct pt_regs *regs) +{ + /* + * Adjust at exit so the main handler sees the true NIA. This must + * come before irq_exit() because irq_exit can enable interrupts, and + * if another interrupt is taken before nap_adjust_return has run + * here, then that interrupt would return directly to idle nap return. + */ + nap_adjust_return(regs); + + irq_exit(); + interrupt_exit_prepare(regs); +} + +struct interrupt_nmi_state { +#ifdef CONFIG_PPC64 + u8 irq_soft_mask; + u8 irq_happened; + u8 ftrace_enabled; + u64 softe; +#endif +}; + +static inline bool nmi_disables_ftrace(struct pt_regs *regs) +{ + /* Allow DEC and PMI to be traced when they are soft-NMI */ + if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) { + if (TRAP(regs) =3D=3D INTERRUPT_DECREMENTER) + return false; + if (TRAP(regs) =3D=3D INTERRUPT_PERFMON) + return false; + } + if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) { + if (TRAP(regs) =3D=3D INTERRUPT_PERFMON) + return false; + } + + return true; +} + +static inline void interrupt_nmi_enter_prepare(struct pt_regs *regs, struc= t interrupt_nmi_state *state) +{ +#ifdef CONFIG_PPC64 + state->irq_soft_mask =3D local_paca->irq_soft_mask; + state->irq_happened =3D local_paca->irq_happened; + state->softe =3D regs->softe; + + /* + * Set IRQS_ALL_DISABLED unconditionally so irqs_disabled() does + * the right thing, and set IRQ_HARD_DIS. We do not want to reconcile + * because that goes through irq tracing which we don't want in NMI. + */ + local_paca->irq_soft_mask =3D IRQS_ALL_DISABLED; + local_paca->irq_happened |=3D PACA_IRQ_HARD_DIS; + + if (!(regs->msr & MSR_EE) || is_implicit_soft_masked(regs)) { + /* + * Adjust regs->softe to be soft-masked if it had not been + * reconcied (e.g., interrupt entry with MSR[EE]=3D0 but softe + * not yet set disabled), or if it was in an implicit soft + * masked state. This makes regs_irqs_disabled(regs) + * behave as expected. + */ + regs->softe =3D IRQS_ALL_DISABLED; + } + + __hard_RI_enable(); + + /* Don't do any per-CPU operations until interrupt state is fixed */ + + if (nmi_disables_ftrace(regs)) { + state->ftrace_enabled =3D this_cpu_get_ftrace_enabled(); + this_cpu_set_ftrace_enabled(0); + } +#endif + + /* If data relocations are enabled, it's safe to use nmi_enter() */ + if (mfmsr() & MSR_DR) { + nmi_enter(); + return; + } + + /* + * But do not use nmi_enter() for pseries hash guest taking a real-mode + * NMI because not everything it touches is within the RMA limit. + */ + if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && + firmware_has_feature(FW_FEATURE_LPAR) && + !radix_enabled()) + return; + + /* + * Likewise, don't use it if we have some form of instrumentation (like + * KASAN shadow) that is not safe to access in real mode (even on radix) + */ + if (IS_ENABLED(CONFIG_KASAN)) + return; + + /* + * Likewise, do not use it in real mode if percpu first chunk is not + * embedded. With CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK enabled there + * are chances where percpu allocation can come from vmalloc area. + */ + if (percpu_first_chunk_is_paged) + return; + + /* Otherwise, it should be safe to call it */ + nmi_enter(); +} + +static inline void interrupt_nmi_exit_prepare(struct pt_regs *regs, struct= interrupt_nmi_state *state) +{ + if (mfmsr() & MSR_DR) { + // nmi_exit if relocations are on + nmi_exit(); + } else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && + firmware_has_feature(FW_FEATURE_LPAR) && + !radix_enabled()) { + // no nmi_exit for a pseries hash guest taking a real mode exception + } else if (IS_ENABLED(CONFIG_KASAN)) { + // no nmi_exit for KASAN in real mode + } else if (percpu_first_chunk_is_paged) { + // no nmi_exit if percpu first chunk is not embedded + } else { + nmi_exit(); + } + + /* + * nmi does not call nap_adjust_return because nmi should not create + * new work to do (must use irq_work for that). + */ + +#ifdef CONFIG_PPC64 +#ifdef CONFIG_PPC_BOOK3S + if (regs_irqs_disabled(regs)) { + unsigned long rst =3D search_kernel_restart_table(regs->nip); + if (rst) + regs_set_return_ip(regs, rst); + } +#endif + + if (nmi_disables_ftrace(regs)) + this_cpu_set_ftrace_enabled(state->ftrace_enabled); + + /* Check we didn't change the pending interrupt mask. */ + WARN_ON_ONCE((state->irq_happened | PACA_IRQ_HARD_DIS) !=3D local_paca->i= rq_happened); + regs->softe =3D state->softe; + local_paca->irq_happened =3D state->irq_happened; + local_paca->irq_soft_mask =3D state->irq_soft_mask; +#endif +} + static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) { if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) --=20 2.51.0 From nobody Wed Sep 10 01:55:30 2025 Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7796F21FF39 for ; Mon, 8 Sep 2025 21:06:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.158.5 ARC-Seal: i=1; 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Mon, 8 Sep 2025 21:05:19 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AEEC220049; Mon, 8 Sep 2025 21:05:19 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9F5F320040; Mon, 8 Sep 2025 21:05:11 +0000 (GMT) Received: from li-e1dea04c-3555-11b2-a85c-f57333552245.ibm.com.com (unknown [9.39.29.251]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 21:05:11 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, deller@gmx.de, ldv@strace.io, macro@orcam.me.uk, charlie@rivosinc.com, akpm@linux-foundation.org, bigeasy@linutronix.de, ankur.a.arora@oracle.com, sshegde@linux.ibm.com, naveen@kernel.org, thomas.weissschuh@linutronix.de, Jason@zx2c4.com, peterz@infradead.org, tglx@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, oliver.upton@linux.dev, mark.barnett@arm.com, atrajeev@linux.vnet.ibm.com, rppt@kernel.org, coltonlewis@google.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [RFC V2 7/8] powerpc: Enable IRQ generic entry/exit path. Date: Tue, 9 Sep 2025 02:32:36 +0530 Message-ID: <20250908210235.137300-10-mchauras@linux.ibm.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250908210235.137300-2-mchauras@linux.ibm.com> References: <20250908210235.137300-2-mchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDE5NSBTYWx0ZWRfX0xH1ARbXEtZP 0KCC5jo6YXfJXGcB7ipSc7sXt6Kac5VR0Wy5ggwIj/G4tmxPGUUr23adWQEYiZJvAG9wfjLXMpT 3sLT/5t/p4I+rp7YOVX9LKTRX6gqIKzym28nAEGWTSvnXO6BY6+Gviae4Bpo8Bqv/RmeWxOwkCG oQqspGC2ZYs5oaXUPjIoJi5uS/+73cITlmSSKJhwtvR9wCzopXoioaXRhdHa5nMIKHMVmXSGvxT CDR7NW3kW/rFtn9JsXv8NfNjTiNWkwufDdB0UOFFYezKdmhXbuJj4ujbQSQiMfFrhEWPAn37qiw 1RxsobRdpVmGhB3NTyCMC+9lguurOBhjfYPSiWV4C87rLOYug5KSqJ7hZKVIn0d9NCxYRP7MUzM oyphw9ag X-Proofpoint-ORIG-GUID: O5MoX6BzNqBebHZVZ5OUmSYp7HtknToE X-Proofpoint-GUID: r2Tp1_pfBH_MEW7O3U3cRM6F0AE4feZP X-Authority-Analysis: v=2.4 cv=StCQ6OO0 c=1 sm=1 tr=0 ts=68bf4515 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=npW8mXSpbv23cfmksNgA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1011 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060195 Content-Type: text/plain; charset="utf-8" Enable generic entry/exit path for ppc irq. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/Kconfig | 1 + arch/powerpc/include/asm/entry-common.h | 93 ++--- arch/powerpc/include/asm/interrupt.h | 492 +++--------------------- arch/powerpc/kernel/interrupt.c | 9 +- arch/powerpc/kernel/interrupt_64.S | 2 - 5 files changed, 92 insertions(+), 505 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 93402a1d9c9fc..e0c51d7b5638d 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -202,6 +202,7 @@ config PPC select GENERIC_GETTIMEOFDAY select GENERIC_IDLE_POLL_SETUP select GENERIC_IOREMAP + select GENERIC_IRQ_ENTRY select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW_LEVEL select GENERIC_PCI_IOMAP if PCI diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h index 28a96a84e83b5..d3f4a12aeafca 100644 --- a/arch/powerpc/include/asm/entry-common.h +++ b/arch/powerpc/include/asm/entry-common.h @@ -191,6 +191,32 @@ static inline void check_return_regs_valid(struct pt_r= egs *regs) #endif } =20 +static inline void arch_interrupt_enter_prepare(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC64 + irq_soft_mask_set(IRQS_ALL_DISABLED); + + /* + * If the interrupt was taken with HARD_DIS clear, then enable MSR[EE]. + * Asynchronous interrupts get here with HARD_DIS set (see below), so + * this enables MSR[EE] for synchronous interrupts. IRQs remain + * soft-masked. The interrupt handler may later call + * interrupt_cond_local_irq_enable() to achieve a regular process + * context. + */ + if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) { + INT_SOFT_MASK_BUG_ON(regs, !(regs->msr & MSR_EE)); + __hard_irq_enable(); + } else { + __hard_RI_enable(); + } + /* Enable MSR[RI] early, to support kernel SLB and hash faults */ +#endif + + if (!regs_irqs_disabled(regs)) + trace_hardirqs_off(); +} + static inline void interrupt_enter_prepare(struct pt_regs *regs) { #ifdef CONFIG_PPC64 @@ -266,7 +292,7 @@ static inline void interrupt_async_enter_prepare(struct= pt_regs *regs) /* Ensure interrupt_enter_prepare does not enable MSR[EE] */ local_paca->irq_happened |=3D PACA_IRQ_HARD_DIS; #endif - interrupt_enter_prepare(regs); + arch_interrupt_enter_prepare(regs); #ifdef CONFIG_PPC_BOOK3S_64 /* * RI=3D1 is set by interrupt_enter_prepare, so this thread flags access @@ -276,7 +302,6 @@ static inline void interrupt_async_enter_prepare(struct= pt_regs *regs) !test_thread_local_flags(_TLF_RUNLATCH)) __ppc64_runlatch_on(); #endif - irq_enter(); } =20 static inline void interrupt_async_exit_prepare(struct pt_regs *regs) @@ -288,8 +313,6 @@ static inline void interrupt_async_exit_prepare(struct = pt_regs *regs) * here, then that interrupt would return directly to idle nap return. */ nap_adjust_return(regs); - - irq_exit(); interrupt_exit_prepare(regs); } =20 @@ -319,7 +342,8 @@ static inline bool nmi_disables_ftrace(struct pt_regs *= regs) return true; } =20 -static inline void interrupt_nmi_enter_prepare(struct pt_regs *regs, struc= t interrupt_nmi_state *state) +static inline void interrupt_nmi_enter_prepare(struct pt_regs *regs, + struct interrupt_nmi_state *state) { #ifdef CONFIG_PPC64 state->irq_soft_mask =3D local_paca->irq_soft_mask; @@ -354,58 +378,11 @@ static inline void interrupt_nmi_enter_prepare(struct= pt_regs *regs, struct inte this_cpu_set_ftrace_enabled(0); } #endif - - /* If data relocations are enabled, it's safe to use nmi_enter() */ - if (mfmsr() & MSR_DR) { - nmi_enter(); - return; - } - - /* - * But do not use nmi_enter() for pseries hash guest taking a real-mode - * NMI because not everything it touches is within the RMA limit. - */ - if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && - firmware_has_feature(FW_FEATURE_LPAR) && - !radix_enabled()) - return; - - /* - * Likewise, don't use it if we have some form of instrumentation (like - * KASAN shadow) that is not safe to access in real mode (even on radix) - */ - if (IS_ENABLED(CONFIG_KASAN)) - return; - - /* - * Likewise, do not use it in real mode if percpu first chunk is not - * embedded. With CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK enabled there - * are chances where percpu allocation can come from vmalloc area. - */ - if (percpu_first_chunk_is_paged) - return; - - /* Otherwise, it should be safe to call it */ - nmi_enter(); } =20 -static inline void interrupt_nmi_exit_prepare(struct pt_regs *regs, struct= interrupt_nmi_state *state) +static inline void interrupt_nmi_exit_prepare(struct pt_regs *regs, + struct interrupt_nmi_state *state) { - if (mfmsr() & MSR_DR) { - // nmi_exit if relocations are on - nmi_exit(); - } else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && - firmware_has_feature(FW_FEATURE_LPAR) && - !radix_enabled()) { - // no nmi_exit for a pseries hash guest taking a real mode exception - } else if (IS_ENABLED(CONFIG_KASAN)) { - // no nmi_exit for KASAN in real mode - } else if (percpu_first_chunk_is_paged) { - // no nmi_exit if percpu first chunk is not embedded - } else { - nmi_exit(); - } - /* * nmi does not call nap_adjust_return because nmi should not create * new work to do (must use irq_work for that). @@ -433,8 +410,11 @@ static inline void interrupt_nmi_exit_prepare(struct p= t_regs *regs, struct inter =20 static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) { - if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) + kuap_lock(); + + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) { BUG_ON(irq_soft_mask_return() !=3D IRQS_ALL_DISABLED); + } =20 BUG_ON(regs_is_unrecoverable(regs)); BUG_ON(!user_mode(regs)); @@ -465,11 +445,8 @@ static __always_inline void arch_enter_from_user_mode(= struct pt_regs *regs) } else #endif kuap_assert_locked(); - booke_restore_dbcr0(); - account_cpu_user_entry(); - account_stolen_time(); =20 /* diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/as= m/interrupt.h index c6ab286a723f2..830501bc1d4aa 100644 --- a/arch/powerpc/include/asm/interrupt.h +++ b/arch/powerpc/include/asm/interrupt.h @@ -66,434 +66,10 @@ =20 #ifndef __ASSEMBLY__ =20 -#include -#include #include /* for show_regs */ +#include =20 -#include -#include -#include #include -#include - -#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG -/* - * WARN/BUG is handled with a program interrupt so minimise checks here to - * avoid recursion and maximise the chance of getting the first oops handl= ed. - */ -#define INT_SOFT_MASK_BUG_ON(regs, cond) \ -do { \ - if ((user_mode(regs) || (TRAP(regs) !=3D INTERRUPT_PROGRAM))) \ - BUG_ON(cond); \ -} while (0) -#else -#define INT_SOFT_MASK_BUG_ON(regs, cond) -#endif - -#ifdef CONFIG_PPC_BOOK3S_64 -extern char __end_soft_masked[]; -bool search_kernel_soft_mask_table(unsigned long addr); -unsigned long search_kernel_restart_table(unsigned long addr); - -DECLARE_STATIC_KEY_FALSE(interrupt_exit_not_reentrant); - -static inline bool is_implicit_soft_masked(struct pt_regs *regs) -{ - if (user_mode(regs)) - return false; - - if (regs->nip >=3D (unsigned long)__end_soft_masked) - return false; - - return search_kernel_soft_mask_table(regs->nip); -} - -static inline void srr_regs_clobbered(void) -{ - local_paca->srr_valid =3D 0; - local_paca->hsrr_valid =3D 0; -} -#else -static inline unsigned long search_kernel_restart_table(unsigned long addr) -{ - return 0; -} - -static inline bool is_implicit_soft_masked(struct pt_regs *regs) -{ - return false; -} - -static inline void srr_regs_clobbered(void) -{ -} -#endif - -static inline void nap_adjust_return(struct pt_regs *regs) -{ -#ifdef CONFIG_PPC_970_NAP - if (unlikely(test_thread_local_flags(_TLF_NAPPING))) { - /* Can avoid a test-and-clear because NMIs do not call this */ - clear_thread_local_flags(_TLF_NAPPING); - regs_set_return_ip(regs, (unsigned long)power4_idle_nap_return); - } -#endif -} - -static inline void booke_load_dbcr0(void) -{ -#ifdef CONFIG_PPC_ADV_DEBUG_REGS - unsigned long dbcr0 =3D current->thread.debug.dbcr0; - - if (likely(!(dbcr0 & DBCR0_IDM))) - return; - - /* - * Check to see if the dbcr0 register is set up to debug. - * Use the internal debug mode bit to do this. - */ - mtmsr(mfmsr() & ~MSR_DE); - if (IS_ENABLED(CONFIG_PPC32)) { - isync(); - global_dbcr0[smp_processor_id()] =3D mfspr(SPRN_DBCR0); - } - mtspr(SPRN_DBCR0, dbcr0); - mtspr(SPRN_DBSR, -1); -#endif -} - - -static inline void booke_restore_dbcr0(void) -{ -#ifdef CONFIG_PPC_ADV_DEBUG_REGS - unsigned long dbcr0 =3D current->thread.debug.dbcr0; - - if (IS_ENABLED(CONFIG_PPC32) && unlikely(dbcr0 & DBCR0_IDM)) { - mtspr(SPRN_DBSR, -1); - mtspr(SPRN_DBCR0, global_dbcr0[smp_processor_id()]); - } -#endif -} - -static inline void check_return_regs_valid(struct pt_regs *regs) -{ -#ifdef CONFIG_PPC_BOOK3S_64 - unsigned long trap, srr0, srr1; - static bool warned; - u8 *validp; - char *h; - - if (trap_is_scv(regs)) - return; - - trap =3D TRAP(regs); - // EE in HV mode sets HSRRs like 0xea0 - if (cpu_has_feature(CPU_FTR_HVMODE) && trap =3D=3D INTERRUPT_EXTERNAL) - trap =3D 0xea0; - - switch (trap) { - case 0x980: - case INTERRUPT_H_DATA_STORAGE: - case 0xe20: - case 0xe40: - case INTERRUPT_HMI: - case 0xe80: - case 0xea0: - case INTERRUPT_H_FAC_UNAVAIL: - case 0x1200: - case 0x1500: - case 0x1600: - case 0x1800: - validp =3D &local_paca->hsrr_valid; - if (!READ_ONCE(*validp)) - return; - - srr0 =3D mfspr(SPRN_HSRR0); - srr1 =3D mfspr(SPRN_HSRR1); - h =3D "H"; - - break; - default: - validp =3D &local_paca->srr_valid; - if (!READ_ONCE(*validp)) - return; - - srr0 =3D mfspr(SPRN_SRR0); - srr1 =3D mfspr(SPRN_SRR1); - h =3D ""; - break; - } - - if (srr0 =3D=3D regs->nip && srr1 =3D=3D regs->msr) - return; - - /* - * A NMI / soft-NMI interrupt may have come in after we found - * srr_valid and before the SRRs are loaded. The interrupt then - * comes in and clobbers SRRs and clears srr_valid. Then we load - * the SRRs here and test them above and find they don't match. - * - * Test validity again after that, to catch such false positives. - * - * This test in general will have some window for false negatives - * and may not catch and fix all such cases if an NMI comes in - * later and clobbers SRRs without clearing srr_valid, but hopefully - * such things will get caught most of the time, statistically - * enough to be able to get a warning out. - */ - if (!READ_ONCE(*validp)) - return; - - if (!data_race(warned)) { - data_race(warned =3D true); - printk("%sSRR0 was: %lx should be: %lx\n", h, srr0, regs->nip); - printk("%sSRR1 was: %lx should be: %lx\n", h, srr1, regs->msr); - show_regs(regs); - } - - WRITE_ONCE(*validp, 0); /* fixup */ -#endif -} - -static inline void interrupt_enter_prepare(struct pt_regs *regs) -{ -#ifdef CONFIG_PPC64 - irq_soft_mask_set(IRQS_ALL_DISABLED); - - /* - * If the interrupt was taken with HARD_DIS clear, then enable MSR[EE]. - * Asynchronous interrupts get here with HARD_DIS set (see below), so - * this enables MSR[EE] for synchronous interrupts. IRQs remain - * soft-masked. The interrupt handler may later call - * interrupt_cond_local_irq_enable() to achieve a regular process - * context. - */ - if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) { - INT_SOFT_MASK_BUG_ON(regs, !(regs->msr & MSR_EE)); - __hard_irq_enable(); - } else { - __hard_RI_enable(); - } - /* Enable MSR[RI] early, to support kernel SLB and hash faults */ -#endif - - if (!regs_irqs_disabled(regs)) - trace_hardirqs_off(); - - if (user_mode(regs)) { - kuap_lock(); - CT_WARN_ON(ct_state() !=3D CT_STATE_USER); - user_exit_irqoff(); - - account_cpu_user_entry(); - account_stolen_time(); - } else { - kuap_save_and_lock(regs); - /* - * CT_WARN_ON comes here via program_check_exception, - * so avoid recursion. - */ - if (TRAP(regs) !=3D INTERRUPT_PROGRAM) - CT_WARN_ON(ct_state() !=3D CT_STATE_KERNEL && - ct_state() !=3D CT_STATE_IDLE); - INT_SOFT_MASK_BUG_ON(regs, is_implicit_soft_masked(regs)); - INT_SOFT_MASK_BUG_ON(regs, regs_irqs_disabled(regs) && - search_kernel_restart_table(regs->nip)); - } - INT_SOFT_MASK_BUG_ON(regs, !regs_irqs_disabled(regs) && - !(regs->msr & MSR_EE)); - - booke_restore_dbcr0(); -} - -/* - * Care should be taken to note that interrupt_exit_prepare and - * interrupt_async_exit_prepare do not necessarily return immediately to - * regs context (e.g., if regs is usermode, we don't necessarily return to - * user mode). Other interrupts might be taken between here and return, - * context switch / preemption may occur in the exit path after this, or a - * signal may be delivered, etc. - * - * The real interrupt exit code is platform specific, e.g., - * interrupt_exit_user_prepare / interrupt_exit_kernel_prepare for 64s. - * - * However interrupt_nmi_exit_prepare does return directly to regs, because - * NMIs do not do "exit work" or replay soft-masked interrupts. - */ -static inline void interrupt_exit_prepare(struct pt_regs *regs) -{ -} - -static inline void interrupt_async_enter_prepare(struct pt_regs *regs) -{ -#ifdef CONFIG_PPC64 - /* Ensure interrupt_enter_prepare does not enable MSR[EE] */ - local_paca->irq_happened |=3D PACA_IRQ_HARD_DIS; -#endif - interrupt_enter_prepare(regs); -#ifdef CONFIG_PPC_BOOK3S_64 - /* - * RI=3D1 is set by interrupt_enter_prepare, so this thread flags access - * has to come afterward (it can cause SLB faults). - */ - if (cpu_has_feature(CPU_FTR_CTRL) && - !test_thread_local_flags(_TLF_RUNLATCH)) - __ppc64_runlatch_on(); -#endif - irq_enter(); -} - -static inline void interrupt_async_exit_prepare(struct pt_regs *regs) -{ - /* - * Adjust at exit so the main handler sees the true NIA. This must - * come before irq_exit() because irq_exit can enable interrupts, and - * if another interrupt is taken before nap_adjust_return has run - * here, then that interrupt would return directly to idle nap return. - */ - nap_adjust_return(regs); - - irq_exit(); - interrupt_exit_prepare(regs); -} - -struct interrupt_nmi_state { -#ifdef CONFIG_PPC64 - u8 irq_soft_mask; - u8 irq_happened; - u8 ftrace_enabled; - u64 softe; -#endif -}; - -static inline bool nmi_disables_ftrace(struct pt_regs *regs) -{ - /* Allow DEC and PMI to be traced when they are soft-NMI */ - if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) { - if (TRAP(regs) =3D=3D INTERRUPT_DECREMENTER) - return false; - if (TRAP(regs) =3D=3D INTERRUPT_PERFMON) - return false; - } - if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) { - if (TRAP(regs) =3D=3D INTERRUPT_PERFMON) - return false; - } - - return true; -} - -static inline void interrupt_nmi_enter_prepare(struct pt_regs *regs, struc= t interrupt_nmi_state *state) -{ -#ifdef CONFIG_PPC64 - state->irq_soft_mask =3D local_paca->irq_soft_mask; - state->irq_happened =3D local_paca->irq_happened; - state->softe =3D regs->softe; - - /* - * Set IRQS_ALL_DISABLED unconditionally so irqs_disabled() does - * the right thing, and set IRQ_HARD_DIS. We do not want to reconcile - * because that goes through irq tracing which we don't want in NMI. - */ - local_paca->irq_soft_mask =3D IRQS_ALL_DISABLED; - local_paca->irq_happened |=3D PACA_IRQ_HARD_DIS; - - if (!(regs->msr & MSR_EE) || is_implicit_soft_masked(regs)) { - /* - * Adjust regs->softe to be soft-masked if it had not been - * reconcied (e.g., interrupt entry with MSR[EE]=3D0 but softe - * not yet set disabled), or if it was in an implicit soft - * masked state. This makes regs_irqs_disabled(regs) - * behave as expected. - */ - regs->softe =3D IRQS_ALL_DISABLED; - } - - __hard_RI_enable(); - - /* Don't do any per-CPU operations until interrupt state is fixed */ - - if (nmi_disables_ftrace(regs)) { - state->ftrace_enabled =3D this_cpu_get_ftrace_enabled(); - this_cpu_set_ftrace_enabled(0); - } -#endif - - /* If data relocations are enabled, it's safe to use nmi_enter() */ - if (mfmsr() & MSR_DR) { - nmi_enter(); - return; - } - - /* - * But do not use nmi_enter() for pseries hash guest taking a real-mode - * NMI because not everything it touches is within the RMA limit. - */ - if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && - firmware_has_feature(FW_FEATURE_LPAR) && - !radix_enabled()) - return; - - /* - * Likewise, don't use it if we have some form of instrumentation (like - * KASAN shadow) that is not safe to access in real mode (even on radix) - */ - if (IS_ENABLED(CONFIG_KASAN)) - return; - - /* - * Likewise, do not use it in real mode if percpu first chunk is not - * embedded. With CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK enabled there - * are chances where percpu allocation can come from vmalloc area. - */ - if (percpu_first_chunk_is_paged) - return; - - /* Otherwise, it should be safe to call it */ - nmi_enter(); -} - -static inline void interrupt_nmi_exit_prepare(struct pt_regs *regs, struct= interrupt_nmi_state *state) -{ - if (mfmsr() & MSR_DR) { - // nmi_exit if relocations are on - nmi_exit(); - } else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && - firmware_has_feature(FW_FEATURE_LPAR) && - !radix_enabled()) { - // no nmi_exit for a pseries hash guest taking a real mode exception - } else if (IS_ENABLED(CONFIG_KASAN)) { - // no nmi_exit for KASAN in real mode - } else if (percpu_first_chunk_is_paged) { - // no nmi_exit if percpu first chunk is not embedded - } else { - nmi_exit(); - } - - /* - * nmi does not call nap_adjust_return because nmi should not create - * new work to do (must use irq_work for that). - */ - -#ifdef CONFIG_PPC64 -#ifdef CONFIG_PPC_BOOK3S - if (regs_irqs_disabled(regs)) { - unsigned long rst =3D search_kernel_restart_table(regs->nip); - if (rst) - regs_set_return_ip(regs, rst); - } -#endif - - if (nmi_disables_ftrace(regs)) - this_cpu_set_ftrace_enabled(state->ftrace_enabled); - - /* Check we didn't change the pending interrupt mask. */ - WARN_ON_ONCE((state->irq_happened | PACA_IRQ_HARD_DIS) !=3D local_paca->i= rq_happened); - regs->softe =3D state->softe; - local_paca->irq_happened =3D state->irq_happened; - local_paca->irq_soft_mask =3D state->irq_soft_mask; -#endif -} =20 /* * Don't use noinstr here like x86, but rather add NOKPROBE_SYMBOL to each @@ -575,10 +151,13 @@ static __always_inline void ____##func(struct pt_regs= *regs); \ \ interrupt_handler void func(struct pt_regs *regs) \ { \ - interrupt_enter_prepare(regs); \ - \ + irqentry_state_t state; \ + arch_interrupt_enter_prepare(regs); \ + state =3D irqentry_enter(regs); \ + instrumentation_begin(); \ ____##func (regs); \ - \ + instrumentation_end(); \ + irqentry_exit(regs, state); \ interrupt_exit_prepare(regs); \ } \ NOKPROBE_SYMBOL(func); \ @@ -609,11 +188,14 @@ static __always_inline long ____##func(struct pt_regs= *regs); \ interrupt_handler long func(struct pt_regs *regs) \ { \ long ret; \ + irqentry_state_t state; \ \ - interrupt_enter_prepare(regs); \ - \ + arch_interrupt_enter_prepare(regs); \ + state =3D irqentry_enter(regs); \ + instrumentation_begin(); \ ret =3D ____##func (regs); \ - \ + instrumentation_end(); \ + irqentry_exit(regs, state); \ interrupt_exit_prepare(regs); \ \ return ret; \ @@ -643,11 +225,16 @@ static __always_inline void ____##func(struct pt_regs= *regs); \ \ interrupt_handler void func(struct pt_regs *regs) \ { \ + irqentry_state_t state; \ interrupt_async_enter_prepare(regs); \ - \ + state =3D irqentry_enter(regs); \ + instrumentation_begin(); \ + irq_enter_rcu(); \ ____##func (regs); \ - \ + irq_exit_rcu(); \ + instrumentation_end(); \ interrupt_async_exit_prepare(regs); \ + irqentry_exit(regs, state); \ } \ NOKPROBE_SYMBOL(func); \ \ @@ -677,14 +264,43 @@ ____##func(struct pt_regs *regs); \ \ interrupt_handler long func(struct pt_regs *regs) \ { \ - struct interrupt_nmi_state state; \ + irqentry_state_t state; \ + struct interrupt_nmi_state nmi_state; \ long ret; \ \ - interrupt_nmi_enter_prepare(regs, &state); \ - \ + interrupt_nmi_enter_prepare(regs, &nmi_state); \ + if (mfmsr() & MSR_DR) { \ + /* nmi_entry if relocations are on */ \ + state =3D irqentry_nmi_enter(regs); \ + } else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && \ + firmware_has_feature(FW_FEATURE_LPAR) && \ + !radix_enabled()) { \ + /* no nmi_entry for a pseries hash guest \ + * taking a real mode exception */ \ + } else if (IS_ENABLED(CONFIG_KASAN)) { \ + /* no nmi_entry for KASAN in real mode */ \ + } else if (percpu_first_chunk_is_paged) { \ + /* no nmi_entry if percpu first chunk is not embedded */\ + } else { \ + state =3D irqentry_nmi_enter(regs); \ + } \ ret =3D ____##func (regs); \ - \ - interrupt_nmi_exit_prepare(regs, &state); \ + if (mfmsr() & MSR_DR) { \ + /* nmi_exit if relocations are on */ \ + irqentry_nmi_exit(regs, state); \ + } else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && \ + firmware_has_feature(FW_FEATURE_LPAR) && \ + !radix_enabled()) { \ + /* no nmi_exit for a pseries hash guest \ + * taking a real mode exception */ \ + } else if (IS_ENABLED(CONFIG_KASAN)) { \ + /* no nmi_exit for KASAN in real mode */ \ + } else if (percpu_first_chunk_is_paged) { \ + /* no nmi_exit if percpu first chunk is not embedded */ \ + } else { \ + irqentry_nmi_exit(regs, state); \ + } \ + interrupt_nmi_exit_prepare(regs,&nmi_state); \ \ return ret; \ } \ diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrup= t.c index f53d432f60870..7bb8a31b24ea7 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -297,13 +297,8 @@ notrace unsigned long interrupt_exit_kernel_prepare(st= ruct pt_regs *regs) /* Returning to a kernel context with local irqs enabled. */ WARN_ON_ONCE(!(regs->msr & MSR_EE)); again: - if (need_irq_preemption()) { - /* Return to preemptible kernel context */ - if (unlikely(read_thread_flags() & _TIF_NEED_RESCHED)) { - if (preempt_count() =3D=3D 0) - preempt_schedule_irq(); - } - } + if (need_irq_preemption()) + irqentry_exit_cond_resched(); =20 check_return_regs_valid(regs); =20 diff --git a/arch/powerpc/kernel/interrupt_64.S b/arch/powerpc/kernel/inter= rupt_64.S index 1ad059a9e2fef..6aa88fe91fb6a 100644 --- a/arch/powerpc/kernel/interrupt_64.S +++ b/arch/powerpc/kernel/interrupt_64.S @@ -418,8 +418,6 @@ _ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()) beq interrupt_return_\srr\()_kernel interrupt_return_\srr\()_user: /* make backtraces match the _kernel varian= t */ _ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_user) - addi r3,r1,STACK_INT_FRAME_REGS - bl CFUNC(interrupt_exit_user_prepare) #ifndef CONFIG_INTERRUPT_SANITIZE_REGISTERS cmpdi r3,0 bne- .Lrestore_nvgprs_\srr --=20 2.51.0 From nobody Wed Sep 10 01:55:30 2025 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49601210FB for ; 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Mon, 8 Sep 2025 21:05:30 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 437DA2004B; Mon, 8 Sep 2025 21:05:30 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6156C20040; Mon, 8 Sep 2025 21:05:22 +0000 (GMT) Received: from li-e1dea04c-3555-11b2-a85c-f57333552245.ibm.com.com (unknown [9.39.29.251]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Sep 2025 21:05:22 +0000 (GMT) From: Mukesh Kumar Chaurasiya To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, christophe.leroy@csgroup.eu, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, deller@gmx.de, ldv@strace.io, macro@orcam.me.uk, charlie@rivosinc.com, akpm@linux-foundation.org, bigeasy@linutronix.de, ankur.a.arora@oracle.com, sshegde@linux.ibm.com, naveen@kernel.org, thomas.weissschuh@linutronix.de, Jason@zx2c4.com, peterz@infradead.org, tglx@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, oliver.upton@linux.dev, mark.barnett@arm.com, atrajeev@linux.vnet.ibm.com, rppt@kernel.org, coltonlewis@google.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [RFC V2 8/8] powerpc: Enable Generic Entry/Exit for syscalls. Date: Tue, 9 Sep 2025 02:32:37 +0530 Message-ID: <20250908210235.137300-11-mchauras@linux.ibm.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250908210235.137300-2-mchauras@linux.ibm.com> References: <20250908210235.137300-2-mchauras@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: G0ElInjIF89fNGzVnaRJ8cJJ-euWYPPW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDIzNSBTYWx0ZWRfX0vhu7gRDNgYp PJ9ENisOyRAXzbpEWWH76V/tS77GX87oDCqx6SeuEEKH3HaVrZCQ02KdNdDIU3lOaqBnpswoM9p bj0kHPnyCxapCa0h0bQmJ91e61qHCj7OFcXIywtd7n1ov0KLLsh+5C5YT2RAh1S5/WDMs60gmFc w5rOvdk7Sg64GzKL/eplA+YduDMC5yWLTUJtt1XBtoI22pd7e86+S9HEJNuu2crlb/mD+cTkrjO S6viw/LNRHspnlwSaXdjCxLnRe9b7pXZ8BNZ3rZkuS8u2XtfFhfWSGcu1OxDmYq1pL6fPZsLjRq lqsEiCbPCXvzj98G1Hjn8+We5lr89In+lHhP4IExcZeo2+v9lvIFuBF7ujDqWHEzwVI1iMxfCcX ZYuTBk8v X-Proofpoint-GUID: vDuNYkURlWaFj7iFWr1pqjvUWTGjPBVh X-Authority-Analysis: v=2.4 cv=F59XdrhN c=1 sm=1 tr=0 ts=68bf4520 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=TVope2VSOmiRRkq04hEA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1011 impostorscore=0 bulkscore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060235 Content-Type: text/plain; charset="utf-8" Enable the syscall entry and exit path from generic framework. Signed-off-by: Mukesh Kumar Chaurasiya --- arch/powerpc/Kconfig | 1 + arch/powerpc/include/asm/entry-common.h | 2 +- arch/powerpc/kernel/interrupt.c | 135 +++++++---------------- arch/powerpc/kernel/ptrace/ptrace.c | 141 ------------------------ arch/powerpc/kernel/signal.c | 10 +- arch/powerpc/kernel/syscall.c | 119 +------------------- 6 files changed, 49 insertions(+), 359 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index e0c51d7b5638d..e67294a72e4d4 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -199,6 +199,7 @@ config PPC select GENERIC_CPU_AUTOPROBE select GENERIC_CPU_VULNERABILITIES if PPC_BARRIER_NOSPEC select GENERIC_EARLY_IOREMAP + select GENERIC_ENTRY select GENERIC_GETTIMEOFDAY select GENERIC_IDLE_POLL_SETUP select GENERIC_IOREMAP diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include= /asm/entry-common.h index d3f4a12aeafca..8fb74e6aa9560 100644 --- a/arch/powerpc/include/asm/entry-common.h +++ b/arch/powerpc/include/asm/entry-common.h @@ -3,7 +3,7 @@ #ifndef _ASM_PPC_ENTRY_COMMON_H #define _ASM_PPC_ENTRY_COMMON_H =20 -#ifdef CONFIG_GENERIC_IRQ_ENTRY +#ifdef CONFIG_GENERIC_ENTRY =20 #include #include diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrup= t.c index 7bb8a31b24ea7..642e22527f9dd 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later =20 #include +#include #include #include #include @@ -77,79 +78,6 @@ static notrace __always_inline bool prep_irq_for_enabled= _exit(bool restartable) return true; } =20 -static notrace unsigned long -interrupt_exit_user_prepare_main(unsigned long ret, struct pt_regs *regs) -{ - unsigned long ti_flags; - -again: - ti_flags =3D read_thread_flags(); - while (unlikely(ti_flags & (_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM))) { - local_irq_enable(); - if (ti_flags & (_TIF_NEED_RESCHED | _TIF_NEED_RESCHED_LAZY)) { - schedule(); - } else { - /* - * SIGPENDING must restore signal handler function - * argument GPRs, and some non-volatiles (e.g., r1). - * Restore all for now. This could be made lighter. - */ - if (ti_flags & _TIF_SIGPENDING) - ret |=3D _TIF_RESTOREALL; - do_notify_resume(regs, ti_flags); - } - local_irq_disable(); - ti_flags =3D read_thread_flags(); - } - - if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && IS_ENABLED(CONFIG_PPC_FPU)) { - if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && - unlikely((ti_flags & _TIF_RESTORE_TM))) { - restore_tm_state(regs); - } else { - unsigned long mathflags =3D MSR_FP; - - if (cpu_has_feature(CPU_FTR_VSX)) - mathflags |=3D MSR_VEC | MSR_VSX; - else if (cpu_has_feature(CPU_FTR_ALTIVEC)) - mathflags |=3D MSR_VEC; - - /* - * If userspace MSR has all available FP bits set, - * then they are live and no need to restore. If not, - * it means the regs were given up and restore_math - * may decide to restore them (to avoid taking an FP - * fault). - */ - if ((regs->msr & mathflags) !=3D mathflags) - restore_math(regs); - } - } - - check_return_regs_valid(regs); - - user_enter_irqoff(); - if (!prep_irq_for_enabled_exit(true)) { - user_exit_irqoff(); - local_irq_enable(); - local_irq_disable(); - goto again; - } - -#ifdef CONFIG_PPC_TRANSACTIONAL_MEM - local_paca->tm_scratch =3D regs->msr; -#endif - - booke_load_dbcr0(); - - account_cpu_user_exit(); - - /* Restore user access locks last */ - kuap_user_restore(regs); - - return ret; -} - /* * This should be called after a syscall returns, with r3 the return value * from the syscall. If this function returns non-zero, the system call @@ -164,17 +92,12 @@ notrace unsigned long syscall_exit_prepare(unsigned lo= ng r3, long scv) { unsigned long ti_flags; - unsigned long ret =3D 0; bool is_not_scv =3D !IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !scv; =20 - CT_WARN_ON(ct_state() =3D=3D CT_STATE_USER); - kuap_assert_locked(); =20 regs->result =3D r3; - - /* Check whether the syscall is issued inside a restartable sequence */ - rseq_syscall(regs); + regs->exit_flags =3D 0; =20 ti_flags =3D read_thread_flags(); =20 @@ -187,7 +110,7 @@ notrace unsigned long syscall_exit_prepare(unsigned lon= g r3, =20 if (unlikely(ti_flags & _TIF_PERSYSCALL_MASK)) { if (ti_flags & _TIF_RESTOREALL) - ret =3D _TIF_RESTOREALL; + regs->exit_flags =3D _TIF_RESTOREALL; else regs->gpr[3] =3D r3; clear_bits(_TIF_PERSYSCALL_MASK, ¤t_thread_info()->flags); @@ -196,18 +119,28 @@ notrace unsigned long syscall_exit_prepare(unsigned l= ong r3, } =20 if (unlikely(ti_flags & _TIF_SYSCALL_DOTRACE)) { - do_syscall_trace_leave(regs); - ret |=3D _TIF_RESTOREALL; + regs->exit_flags |=3D _TIF_RESTOREALL; } =20 - local_irq_disable(); - ret =3D interrupt_exit_user_prepare_main(ret, regs); +again: + syscall_exit_to_user_mode(regs); + + user_enter_irqoff(); + if (!prep_irq_for_enabled_exit(true)) { + user_exit_irqoff(); + local_irq_enable(); + local_irq_disable(); + goto again; + } + + /* Restore user access locks last */ + kuap_user_restore(regs); =20 #ifdef CONFIG_PPC64 - regs->exit_result =3D ret; + regs->exit_result =3D regs->exit_flags; #endif =20 - return ret; + return regs->exit_flags; } =20 #ifdef CONFIG_PPC64 @@ -226,14 +159,18 @@ notrace unsigned long syscall_exit_restart(unsigned l= ong r3, struct pt_regs *reg #ifdef CONFIG_PPC_BOOK3S_64 set_kuap(AMR_KUAP_BLOCKED); #endif +again: + syscall_exit_to_user_mode(regs); =20 - trace_hardirqs_off(); - user_exit_irqoff(); - account_cpu_user_entry(); - - BUG_ON(!user_mode(regs)); + user_enter_irqoff(); + if (!prep_irq_for_enabled_exit(true)) { + user_exit_irqoff(); + local_irq_enable(); + local_irq_disable(); + goto again; + } =20 - regs->exit_result =3D interrupt_exit_user_prepare_main(regs->exit_result,= regs); + regs->exit_result |=3D regs->exit_flags; =20 return regs->exit_result; } @@ -254,8 +191,20 @@ notrace unsigned long interrupt_exit_user_prepare(stru= ct pt_regs *regs) kuap_assert_locked(); =20 local_irq_disable(); + regs->exit_flags =3D 0; +again: + irqentry_exit_to_user_mode(regs); + check_return_regs_valid(regs); + + user_enter_irqoff(); + if (!prep_irq_for_enabled_exit(true)) { + user_exit_irqoff(); + local_irq_enable(); + local_irq_disable(); + goto again; + } =20 - ret =3D interrupt_exit_user_prepare_main(0, regs); + ret =3D regs->exit_flags; =20 #ifdef CONFIG_PPC64 regs->exit_result =3D ret; diff --git a/arch/powerpc/kernel/ptrace/ptrace.c b/arch/powerpc/kernel/ptra= ce/ptrace.c index 2134b6d155ff6..316d4f5ead8ed 100644 --- a/arch/powerpc/kernel/ptrace/ptrace.c +++ b/arch/powerpc/kernel/ptrace/ptrace.c @@ -21,9 +21,6 @@ #include #include =20 -#define CREATE_TRACE_POINTS -#include - #include "ptrace-decl.h" =20 /* @@ -195,144 +192,6 @@ long arch_ptrace(struct task_struct *child, long requ= est, return ret; } =20 -#ifdef CONFIG_SECCOMP -static int do_seccomp(struct pt_regs *regs) -{ - if (!test_thread_flag(TIF_SECCOMP)) - return 0; - - /* - * The ABI we present to seccomp tracers is that r3 contains - * the syscall return value and orig_gpr3 contains the first - * syscall parameter. This is different to the ptrace ABI where - * both r3 and orig_gpr3 contain the first syscall parameter. - */ - regs->gpr[3] =3D -ENOSYS; - - /* - * We use the __ version here because we have already checked - * TIF_SECCOMP. If this fails, there is nothing left to do, we - * have already loaded -ENOSYS into r3, or seccomp has put - * something else in r3 (via SECCOMP_RET_ERRNO/TRACE). - */ - if (__secure_computing()) - return -1; - - /* - * The syscall was allowed by seccomp, restore the register - * state to what audit expects. - * Note that we use orig_gpr3, which means a seccomp tracer can - * modify the first syscall parameter (in orig_gpr3) and also - * allow the syscall to proceed. - */ - regs->gpr[3] =3D regs->orig_gpr3; - - return 0; -} -#else -static inline int do_seccomp(struct pt_regs *regs) { return 0; } -#endif /* CONFIG_SECCOMP */ - -/** - * do_syscall_trace_enter() - Do syscall tracing on kernel entry. - * @regs: the pt_regs of the task to trace (current) - * - * Performs various types of tracing on syscall entry. This includes secco= mp, - * ptrace, syscall tracepoints and audit. - * - * The pt_regs are potentially visible to userspace via ptrace, so their - * contents is ABI. - * - * One or more of the tracers may modify the contents of pt_regs, in parti= cular - * to modify arguments or even the syscall number itself. - * - * It's also possible that a tracer can choose to reject the system call. = In - * that case this function will return an illegal syscall number, and will= put - * an appropriate return value in regs->r3. - * - * Return: the (possibly changed) syscall number. - */ -long do_syscall_trace_enter(struct pt_regs *regs) -{ - u32 flags; - - flags =3D read_thread_flags() & (_TIF_SYSCALL_EMU | _TIF_SYSCALL_TRACE); - - if (flags) { - int rc =3D ptrace_report_syscall_entry(regs); - - if (unlikely(flags & _TIF_SYSCALL_EMU)) { - /* - * A nonzero return code from - * ptrace_report_syscall_entry() tells us to prevent - * the syscall execution, but we are not going to - * execute it anyway. - * - * Returning -1 will skip the syscall execution. We want - * to avoid clobbering any registers, so we don't goto - * the skip label below. - */ - return -1; - } - - if (rc) { - /* - * The tracer decided to abort the syscall. Note that - * the tracer may also just change regs->gpr[0] to an - * invalid syscall number, that is handled below on the - * exit path. - */ - goto skip; - } - } - - /* Run seccomp after ptrace; allow it to set gpr[3]. */ - if (do_seccomp(regs)) - return -1; - - /* Avoid trace and audit when syscall is invalid. */ - if (regs->gpr[0] >=3D NR_syscalls) - goto skip; - - if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) - trace_sys_enter(regs, regs->gpr[0]); - - if (!is_32bit_task()) - audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4], - regs->gpr[5], regs->gpr[6]); - else - audit_syscall_entry(regs->gpr[0], - regs->gpr[3] & 0xffffffff, - regs->gpr[4] & 0xffffffff, - regs->gpr[5] & 0xffffffff, - regs->gpr[6] & 0xffffffff); - - /* Return the possibly modified but valid syscall number */ - return regs->gpr[0]; - -skip: - /* - * If we are aborting explicitly, or if the syscall number is - * now invalid, set the return value to -ENOSYS. - */ - regs->gpr[3] =3D -ENOSYS; - return -1; -} - -void do_syscall_trace_leave(struct pt_regs *regs) -{ - int step; - - audit_syscall_exit(regs); - - if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) - trace_sys_exit(regs, regs->result); - - step =3D test_thread_flag(TIF_SINGLESTEP); - if (step || test_thread_flag(TIF_SYSCALL_TRACE)) - ptrace_report_syscall_exit(regs, step); -} - void __init pt_regs_check(void); =20 /* diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c index 719930cf4ae1f..9f1847b4742e6 100644 --- a/arch/powerpc/kernel/signal.c +++ b/arch/powerpc/kernel/signal.c @@ -6,6 +6,7 @@ * Extracted from signal_32.c and signal_64.c */ =20 +#include #include #include #include @@ -22,11 +23,6 @@ =20 #include "signal.h" =20 -/* This will be removed */ -#ifdef CONFIG_GENERIC_ENTRY -#include -#endif /* CONFIG_GENERIC_ENTRY */ - #ifdef CONFIG_VSX unsigned long copy_fpr_to_user(void __user *to, struct task_struct *task) @@ -374,11 +370,9 @@ void signal_fault(struct task_struct *tsk, struct pt_r= egs *regs, task_pid_nr(tsk), where, ptr, regs->nip, regs->link); } =20 -#ifdef CONFIG_GENERIC_ENTRY void arch_do_signal_or_restart(struct pt_regs *regs) { BUG_ON(regs !=3D current->thread.regs); - local_paca->generic_fw_flags |=3D GFW_RESTORE_ALL; + regs->exit_flags |=3D _TIF_RESTOREALL; do_signal(current); } -#endif /* CONFIG_GENERIC_ENTRY */ diff --git a/arch/powerpc/kernel/syscall.c b/arch/powerpc/kernel/syscall.c index 9f03a6263fb41..df1c9a8d62bc6 100644 --- a/arch/powerpc/kernel/syscall.c +++ b/arch/powerpc/kernel/syscall.c @@ -3,6 +3,7 @@ #include #include #include +#include =20 #include #include @@ -18,124 +19,10 @@ notrace long system_call_exception(struct pt_regs *reg= s, unsigned long r0) long ret; syscall_fn f; =20 - kuap_lock(); - add_random_kstack_offset(); + r0 =3D syscall_enter_from_user_mode(regs, r0); =20 - if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) - BUG_ON(irq_soft_mask_return() !=3D IRQS_ALL_DISABLED); - - trace_hardirqs_off(); /* finish reconciling */ - - CT_WARN_ON(ct_state() =3D=3D CT_STATE_KERNEL); - user_exit_irqoff(); - - BUG_ON(regs_is_unrecoverable(regs)); - BUG_ON(!user_mode(regs)); - BUG_ON(regs_irqs_disabled(regs)); - -#ifdef CONFIG_PPC_PKEY - if (mmu_has_feature(MMU_FTR_PKEY)) { - unsigned long amr, iamr; - bool flush_needed =3D false; - /* - * When entering from userspace we mostly have the AMR/IAMR - * different from kernel default values. Hence don't compare. - */ - amr =3D mfspr(SPRN_AMR); - iamr =3D mfspr(SPRN_IAMR); - regs->amr =3D amr; - regs->iamr =3D iamr; - if (mmu_has_feature(MMU_FTR_KUAP)) { - mtspr(SPRN_AMR, AMR_KUAP_BLOCKED); - flush_needed =3D true; - } - if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) { - mtspr(SPRN_IAMR, AMR_KUEP_BLOCKED); - flush_needed =3D true; - } - if (flush_needed) - isync(); - } else -#endif - kuap_assert_locked(); - - booke_restore_dbcr0(); - - account_cpu_user_entry(); - - account_stolen_time(); - - /* - * This is not required for the syscall exit path, but makes the - * stack frame look nicer. If this was initialised in the first stack - * frame, or if the unwinder was taught the first stack frame always - * returns to user with IRQS_ENABLED, this store could be avoided! - */ - irq_soft_mask_regs_set_state(regs, IRQS_ENABLED); - - /* - * If system call is called with TM active, set _TIF_RESTOREALL to - * prevent RFSCV being used to return to userspace, because POWER9 - * TM implementation has problems with this instruction returning to - * transactional state. Final register values are not relevant because - * the transaction will be aborted upon return anyway. Or in the case - * of unsupported_scv SIGILL fault, the return state does not much - * matter because it's an edge case. - */ - if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && - unlikely(MSR_TM_TRANSACTIONAL(regs->msr))) - set_bits(_TIF_RESTOREALL, ¤t_thread_info()->flags); - - /* - * If the system call was made with a transaction active, doom it and - * return without performing the system call. Unless it was an - * unsupported scv vector, in which case it's treated like an illegal - * instruction. - */ -#ifdef CONFIG_PPC_TRANSACTIONAL_MEM - if (unlikely(MSR_TM_TRANSACTIONAL(regs->msr)) && - !trap_is_unsupported_scv(regs)) { - /* Enable TM in the kernel, and disable EE (for scv) */ - hard_irq_disable(); - mtmsr(mfmsr() | MSR_TM); - - /* tabort, this dooms the transaction, nothing else */ - asm volatile(".long 0x7c00071d | ((%0) << 16)" - :: "r"(TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)); - - /* - * Userspace will never see the return value. Execution will - * resume after the tbegin. of the aborted transaction with the - * checkpointed register state. A context switch could occur - * or signal delivered to the process before resuming the - * doomed transaction context, but that should all be handled - * as expected. - */ - return -ENOSYS; - } -#endif // CONFIG_PPC_TRANSACTIONAL_MEM - - local_irq_enable(); - - if (unlikely(read_thread_flags() & _TIF_SYSCALL_DOTRACE)) { - if (unlikely(trap_is_unsupported_scv(regs))) { - /* Unsupported scv vector */ - _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); - return regs->gpr[3]; - } - /* - * We use the return value of do_syscall_trace_enter() as the - * syscall number. If the syscall was rejected for any reason - * do_syscall_trace_enter() returns an invalid syscall number - * and the test against NR_syscalls will fail and the return - * value to be used is in regs->gpr[3]. - */ - r0 =3D do_syscall_trace_enter(regs); - if (unlikely(r0 >=3D NR_syscalls)) - return regs->gpr[3]; - - } else if (unlikely(r0 >=3D NR_syscalls)) { + if (unlikely(r0 >=3D NR_syscalls)) { if (unlikely(trap_is_unsupported_scv(regs))) { /* Unsupported scv vector */ _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); --=20 2.51.0