From nobody Wed Sep 10 05:37:00 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0F4731A059; Mon, 8 Sep 2025 18:11:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; cv=none; b=Wd6UOvkwqwKaR2NhmRi88klzKRqGyp993liH8SeMUgiYf2rNn0+Gy2IOAhD0VAJLLK3rvX0StJKAiz3uGRoq2R5EY/fzizzs5VOnwkuj05QW48bBHQRvsz9AYZaWb48k4xO+lmfeiKuTYrIBfQzbUaWF6Y1CXeYF0skEgDuYC8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; c=relaxed/simple; bh=1u87rs46+m5wL1Xw7aZOQ0O0nwgjPdStsou5RO+mPyc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ErAH5ro/DcvLnArjYAnCxcqaZciX+0nwO7UHYD0/bweHma5Q9r5VdtI2/WIyjSQ2NmFjRjUUcOdKi/q/6i6Eh1RboRPKIwYpazbljdY+dXMLzMUvcrY3pN2qcC15cRgHTzZga5V2mplnBAU5i7eL1KOvN69LuEP6o4WU0IaIq5o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FKZ6t9Ej; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FKZ6t9Ej" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7A1B3C4AF09; Mon, 8 Sep 2025 18:11:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757355074; bh=1u87rs46+m5wL1Xw7aZOQ0O0nwgjPdStsou5RO+mPyc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FKZ6t9EjeuFvlVYPdDV/X+7qVUk2cnIERi/G538DAyJOBxjxV6FcKDDgdgCatWZ4t lgRIzBxM+rRSlpqOBAII07Km0nbFQ630X3TBGwXLkLQsOg50eb8+0XhBfPamJE1h88 6h9Ji0RrmxPn+S7W+Ty86a0oPZGFc644RaF+6mPpG1tn9oyxHk8qIr8qdnhp83aZpL lHhxN5FMwq9kDSYlhk6iDTb27U346M+bFMDPzGbsPSce/CfKesb9rhLkZncD9dtFbw TJdY3SygngoKrc51mD8RkFSaxHG7SNzAnQbdHlY2cqsciQC5xft1+9NSaAidS6xHDy dQ1ldaaEfBuPQ== Received: by wens.tw (Postfix, from userid 1000) id 4E4555FF0D; Tue, 09 Sep 2025 02:11:09 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v4 07/10] arm64: dts: allwinner: a527: cubie-a5e: Enable second Ethernet port Date: Tue, 9 Sep 2025 02:10:56 +0800 Message-Id: <20250908181059.1785605-8-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250908181059.1785605-1-wens@kernel.org> References: <20250908181059.1785605-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Radxa Cubie A5E board, the second Ethernet controller, aka the GMAC200, is connected to a second external Maxio MAE0621A PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. An enable delay for the PHY supply regulator is added to make sure the PHY's internal regulators are fully powered and the PHY is operational. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Add PHY regulator delay --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index d4cee2222104..e96a419faf21 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -14,6 +14,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -76,7 +77,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_cldo3>; =20 allwinner,tx-delay-ps =3D <300>; @@ -85,13 +86,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <300>; + rx-internal-delay-ps =3D <400>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -100,6 +112,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ @@ -240,6 +262,8 @@ reg_cldo4: cldo4 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-name =3D "vcc-pj-phy"; + /* enough time for the PHY to fully power on */ + regulator-enable-ramp-delay =3D <150000>; }; =20 reg_cpusldo: cpusldo { --=20 2.39.5