From nobody Wed Sep 10 01:58:03 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4298531354C; Mon, 8 Sep 2025 18:11:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355072; cv=none; b=As/ZO/7Duhkw0AUHjpOjWGfQMa0H1Em6bv8HTp4lRxmvtEPnk/D8sADXtJj4p23R/02MEXJk4JXABD9GOzU+d+Bh6D3PofDVXygCWA0bPKGp5Nb/Hw7tCoHQUm/8kdizHi47dB5JVnZ0WTtPcJKgg8TBIr4HgCnX46d9OZVDZQk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355072; c=relaxed/simple; bh=cGn/A6pv5/QIRUIvcflPGOg7C3keUUcnpZ16rUvo3ZA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ksEjIXA7DYSFrdoPbNJbfOq7G+G3e48BRAgqjQKHy30z6fHyKdC1V1I9W0x0kVqOnG+6HP0RPAdcTHkY71NS5pFxECVjGY4+E58XY4B4895p1e9FG4acs0kHxpm2TW/QyQk4MR3RvaAO3B3VATb5f5YaqGjDpYxVlVolPsMsmnU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iTsHVkd/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iTsHVkd/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AC703C4CEFA; Mon, 8 Sep 2025 18:11:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757355071; bh=cGn/A6pv5/QIRUIvcflPGOg7C3keUUcnpZ16rUvo3ZA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iTsHVkd/xAiEInulAS4bF8zpVoN6XGPuDUUFQZs+hCL9rnxBu0i1DufqlYaUoKLNj coMaVH9dRdgwsChsdIcxE8M/khzYKa5FxCWQSuugEU8ef7+IzSCnkj87RBY6Ci9+hW bQv2RfAQbTjZkYO/9fOxruLgGOdpibOE9RhdkzVQ5VNHLKwiN87Zx3kthAWxV8zHIf pFuLhFnsh0uVhmdIYdt+KjKYt2TzMTaTVHncum15VAiZR9CJ6dybknY6M+R4DI3y8k NXcahZD56qhwzYqkDmP5ODqdS7KfUKYdYMXFPxavbpnnCA+zYMiT+FshtUgEThJDVg XeYTWddIzw3gA== Received: by wens.tw (Postfix, from userid 1000) id EBF2C5FAC5; Tue, 09 Sep 2025 02:11:08 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v4 01/10] dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible Date: Tue, 9 Sep 2025 02:10:50 +0800 Message-Id: <20250908181059.1785605-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250908181059.1785605-1-wens@kernel.org> References: <20250908181059.1785605-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a compatible string entry for it, and work in the requirements for a second clock and a power domain. Signed-off-by: Chen-Yu Tsai --- Changes since v2: - Added "select" to avoid matching against all dwmac entries Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../net/allwinner,sun8i-a83t-emac.yaml | 96 ++++++++++++++++++- 1 file changed, 94 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-ema= c.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.ya= ml index 2ac709a4c472..9d205c5d93ca 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -10,6 +10,21 @@ maintainers: - Chen-Yu Tsai - Maxime Ripard =20 +# We need a select here so we don't match all nodes with 'snps,dwmac' +select: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-emac + - allwinner,sun8i-h3-emac + - allwinner,sun8i-r40-gmac + - allwinner,sun8i-v3s-emac + - allwinner,sun50i-a64-emac + - allwinner,sun55i-a523-gmac200 + required: + - compatible + properties: compatible: oneOf: @@ -26,6 +41,9 @@ properties: - allwinner,sun50i-h616-emac0 - allwinner,sun55i-a523-gmac0 - const: allwinner,sun50i-a64-emac + - items: + - const: allwinner,sun55i-a523-gmac200 + - const: snps,dwmac-4.20a =20 reg: maxItems: 1 @@ -37,14 +55,19 @@ properties: const: macirq =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 clock-names: - const: stmmaceth + minItems: 1 + maxItems: 2 =20 phy-supply: description: PHY regulator =20 + power-domains: + maxItems: 1 + syscon: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -191,6 +214,45 @@ allOf: - mdio-parent-bus - mdio@1 =20 + - if: + properties: + compatible: + contains: + const: allwinner,sun55i-a523-gmac200 + then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: stmmaceth + - const: mbus + tx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 700 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + rx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 3100 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + required: + - power-domains + else: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: stmmaceth + power-domains: false + + unevaluatedProperties: false =20 examples: @@ -323,4 +385,34 @@ examples: }; }; =20 + - | + ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu 117>, <&ccu 79>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu 43>; + reset-names =3D "stmmaceth"; + interrupts =3D <0 47 4>; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 4>; + syscon =3D <&syscon>; + phy-handle =3D <&ext_rgmii_phy_1>; + phy-mode =3D "rgmii-id"; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ext_rgmii_phy_1: ethernet-phy@1 { + reg =3D <1>; + }; + }; + }; ... --=20 2.39.5 From nobody Wed Sep 10 01:58:03 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21E423126D2; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XzIpngx3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9CA7DC4CEF1; Mon, 8 Sep 2025 18:11:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757355071; bh=YUfJQuKeoyvq69CqM4HMv+h2j8i7bzCRaIDADuqZWZs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XzIpngx3IOurLr5u3CusrdxOtDADL4yG88U6FwaDbjsa2CQ7EOXVk3Qw0TE35hot6 8nWPoZB0WyK/zuOyZMMlW76DxQDYoppnYpUR8Xu8Tkzea+1h0SXf07HEYiUL9PTP8l eqG6URao5KK4rLnUcRbhHIgoR1eQ+Ps614o7I0tWGX379z7D4mFlBi9ZMjQIKfhpVs nGc05XCBL5pm7cyDz23wc2Z/VzZdwZ3P8D1xpmNdyfy+m4F5jW/2xsHjCty/JDzIOX TRc3bz/WI6p3DcpyV/OHrImsyxn0UHOlaXkaIBCP9jiGDXNmnfCX6BE4lAyslGDEUT nVtJAI6B5dvug== Received: by wens.tw (Postfix, from userid 1000) id 0CC6F5FC00; Tue, 09 Sep 2025 02:11:08 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v4 02/10] net: stmmac: Add support for Allwinner A523 GMAC200 Date: Tue, 9 Sep 2025 02:10:51 +0800 Message-Id: <20250908181059.1785605-3-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250908181059.1785605-1-wens@kernel.org> References: <20250908181059.1785605-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a new driver for this hardware supporting the integration layer. Signed-off-by: Chen-Yu Tsai --- Changes since v3: - Fixed printf format specifier warning Changes since v2 (all suggested by Russell King): - Include "ps" unit in "... must be multiple of ..." error message - Use FIELD_FIT to check if delay value is in range and FIELD_MAX to get the maximum value - Reword error message for delay value exceeding maximum - Drop MASK_TO_VAL Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Change dev_err() + return to dev_err_probe() - Check return value from syscon regmap write - Change driver name to match file name --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-sun55i.c | 159 ++++++++++++++++++ 3 files changed, 172 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 67fa879b1e52..38ce9a0cfb5b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -263,6 +263,18 @@ config DWMAC_SUN8I stmmac device driver. This driver is used for H3/A83T/A64 EMAC ethernet controller. =20 +config DWMAC_SUN55I + tristate "Allwinner sun55i GMAC200 support" + default ARCH_SUNXI + depends on OF && (ARCH_SUNXI || COMPILE_TEST) + select MDIO_BUS_MUX + help + Support for Allwinner A523/T527 GMAC200 ethernet controllers. + + This selects Allwinner SoC glue layer support for the + stmmac device driver. This driver is used for A523/T527 + GMAC200 ethernet controller. + config DWMAC_THEAD tristate "T-HEAD dwmac support" depends on OF && (ARCH_THEAD || COMPILE_TEST) diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index b591d93f8503..51e068e26ce4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_STI) +=3D dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) +=3D dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) +=3D dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUN8I) +=3D dwmac-sun8i.o +obj-$(CONFIG_DWMAC_SUN55I) +=3D dwmac-sun55i.o obj-$(CONFIG_DWMAC_THEAD) +=3D dwmac-thead.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) +=3D dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) +=3D dwmac-intel-plat.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c b/drivers/n= et/ethernet/stmicro/stmmac/dwmac-sun55i.c new file mode 100644 index 000000000000..b34da76ac344 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dwmac-sun55i.c - Allwinner sun55i GMAC200 specific glue layer + * + * Copyright (C) 2025 Chen-Yu Tsai + * + * syscon parts taken from dwmac-sun8i.c, which is + * + * Copyright (C) 2017 Corentin Labbe + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac.h" +#include "stmmac_platform.h" + +#define SYSCON_REG 0x34 + +/* RMII specific bits */ +#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ +/* Generic system control EMAC_CLK bits */ +#define SYSCON_ETXDC_MASK GENMASK(12, 10) +#define SYSCON_ERXDC_MASK GENMASK(9, 5) +/* EMAC PHY Interface Type */ +#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ +#define SYSCON_ETCS_MASK GENMASK(1, 0) +#define SYSCON_ETCS_MII 0x0 +#define SYSCON_ETCS_EXT_GMII 0x1 +#define SYSCON_ETCS_INT_GMII 0x2 + +static int sun55i_gmac200_set_syscon(struct device *dev, + struct plat_stmmacenet_data *plat) +{ + struct device_node *node =3D dev->of_node; + struct regmap *regmap; + u32 val, reg =3D 0; + int ret; + + regmap =3D syscon_regmap_lookup_by_phandle(node, "syscon"); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Unable to map syscon\n"); + + if (!of_property_read_u32(node, "tx-internal-delay-ps", &val)) { + if (val % 100) + return dev_err_probe(dev, -EINVAL, + "tx-delay must be a multiple of 100ps\n"); + val /=3D 100; + dev_dbg(dev, "set tx-delay to %x\n", val); + if (!FIELD_FIT(SYSCON_ETXDC_MASK, val)) + return dev_err_probe(dev, -EINVAL, + "TX clock delay exceeds maximum (%u00ps > %lu00ps)\n", + val, FIELD_MAX(SYSCON_ETXDC_MASK)); + + reg |=3D FIELD_PREP(SYSCON_ETXDC_MASK, val); + } + + if (!of_property_read_u32(node, "rx-internal-delay-ps", &val)) { + if (val % 100) + return dev_err_probe(dev, -EINVAL, + "rx-delay must be a multiple of 100ps\n"); + val /=3D 100; + dev_dbg(dev, "set rx-delay to %x\n", val); + if (!FIELD_FIT(SYSCON_ERXDC_MASK, val)) + return dev_err_probe(dev, -EINVAL, + "RX clock delay exceeds maximum (%u00ps > %lu00ps)\n", + val, FIELD_MAX(SYSCON_ERXDC_MASK)); + + reg |=3D FIELD_PREP(SYSCON_ERXDC_MASK, val); + } + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + /* default */ + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + reg |=3D SYSCON_EPIT | SYSCON_ETCS_INT_GMII; + break; + case PHY_INTERFACE_MODE_RMII: + reg |=3D SYSCON_RMII_EN; + break; + default: + return dev_err_probe(dev, -EINVAL, "Unsupported interface mode: %s", + phy_modes(plat->mac_interface)); + } + + ret =3D regmap_write(regmap, SYSCON_REG, reg); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to write to syscon\n"); + + return 0; +} + +static int sun55i_gmac200_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct device *dev =3D &pdev->dev; + struct clk *clk; + int ret; + + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + /* BSP disables it */ + plat_dat->flags |=3D STMMAC_FLAG_SPH_DISABLE; + plat_dat->host_dma_width =3D 32; + + ret =3D sun55i_gmac200_set_syscon(dev, plat_dat); + if (ret) + return ret; + + clk =3D devm_clk_get_enabled(dev, "mbus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get or enable MBUS clock\n"); + + ret =3D devm_regulator_get_enable_optional(dev, "phy"); + if (ret) + return dev_err_probe(dev, ret, "Failed to get or enable PHY supply\n"); + + return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); +} + +static const struct of_device_id sun55i_gmac200_match[] =3D { + { .compatible =3D "allwinner,sun55i-a523-gmac200" }, + { } +}; +MODULE_DEVICE_TABLE(of, sun55i_gmac200_match); + +static struct platform_driver sun55i_gmac200_driver =3D { + .probe =3D sun55i_gmac200_probe, + .driver =3D { + .name =3D "dwmac-sun55i", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D sun55i_gmac200_match, + }, +}; +module_platform_driver(sun55i_gmac200_driver); + +MODULE_AUTHOR("Chen-Yu Tsai "); +MODULE_DESCRIPTION("Allwinner sun55i GMAC200 specific glue layer"); +MODULE_LICENSE("GPL"); --=20 2.39.5 From nobody Wed Sep 10 01:58:03 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42A42313E14; Mon, 8 Sep 2025 18:11:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355072; cv=none; b=cDTAvEw4n4fTnC0p8E9j2zaWtmEJsQBlfaW7dzsov9WWXD2SN3HRumEiutHo5nLKVIeG/Kvi3C/PHKnxuWaThdVkiDiPhlE8MuOopAbHrxjJJsU9+0tYtjBQYloT7LkM5sUlYQMY/fF7jqAcCT5erHVT9ppCqbkFVsb1FVLbK/I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355072; c=relaxed/simple; bh=e0tQSO9pJI2jVvlvL9W4OBbAj83puHTjG+o0KV+3bdg=; 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Tue, 09 Sep 2025 02:11:08 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v4 03/10] soc: sunxi: sram: add entry for a523 Date: Tue, 9 Sep 2025 02:10:52 +0800 Message-Id: <20250908181059.1785605-4-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250908181059.1785605-1-wens@kernel.org> References: <20250908181059.1785605-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 has two Ethernet controllers. So in the system controller address space, there are two registers for Ethernet clock delays, one for each controller. Add a new entry for the A523 system controller that allows access to the second register. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- drivers/soc/sunxi/sunxi_sram.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 08e264ea0697..4f8d510b7e1e 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -320,6 +320,10 @@ static const struct sunxi_sramc_variant sun50i_h616_sr= amc_variant =3D { .has_ths_offset =3D true, }; =20 +static const struct sunxi_sramc_variant sun55i_a523_sramc_variant =3D { + .num_emac_clocks =3D 2, +}; + #define SUNXI_SRAM_THS_OFFSET_REG 0x0 #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30 #define SUNXI_SYS_LDO_CTRL_REG 0x150 @@ -440,6 +444,10 @@ static const struct of_device_id sunxi_sram_dt_match[]= =3D { .compatible =3D "allwinner,sun50i-h616-system-control", .data =3D &sun50i_h616_sramc_variant, }, + { + .compatible =3D "allwinner,sun55i-a523-system-control", + .data =3D &sun55i_a523_sramc_variant, + }, { }, }; MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match); --=20 2.39.5 From nobody Wed Sep 10 01:58:03 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 428EA31283B; Mon, 8 Sep 2025 18:11:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355072; cv=none; b=bWds5oYsiSr7NvZ9TgXl5ejMbpSzGzGrPCGOYTzWzXtoIUZ0SGFInIaEB9Ih45GmSvwReQaukiXU38feRDxkfu04PvMeleRZicGMW6iIifet8AOQuE7nmzK0gVsA9mI9QSM+W3E9ZO+bEgthUXxnEEQNAHsyd4KkNmSk3qBPVBY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355072; c=relaxed/simple; bh=lfdtXInB87tu2kO8lr4PclPJGDu1MGh0UniOZ5ZFUPg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=s7S4jX3rcKbfbrRZFvDAB4jj6/raXXNQOQfo02r1H2zFd45SN/TEmHojtVdwzLjyyYOnc4FsEIxjflG3AjGXW8Y9gk0HG3Ti/dNi/LJcEsZbfOnBcy0dbgxF8U/N6vw5Eqe7vWqhEgqXQoKZ+QmwFaDjezIrl8V19icotHxYI2g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SsJSXMDA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SsJSXMDA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A3BF2C4AF0B; Mon, 8 Sep 2025 18:11:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757355071; bh=lfdtXInB87tu2kO8lr4PclPJGDu1MGh0UniOZ5ZFUPg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SsJSXMDAgjrWt/CinApi/kfH/8IGCgQE9y6YylGIBATS7IcSBWWNry81z2gxcwVWB tM7RDdrsu+8LA94mFbNDO1MFtYTTIzlMBb2MGExtX0mkOfWrNM76q+d5ZXEgtaAoQL v6dPuMeNcBwaY8UzZiqj2blSBxgH/gBS6+jLsSDSXY1tdaa0m1JmpwlcMf9XtEfvvg h7L7tYWk0ld31Pi5kjxGMkOrVOH7uLPL9EE4/dk2dM1Elm/Fqhhq3OV7WohSU+MLMr RK9e7/6nvodl34f1VixxghUpbatZbmcdPbJnP4KOGfDWAl+RPVD0jbobHFISuYgtnq IawI8k8rQj62A== Received: by wens.tw (Postfix, from userid 1000) id 1BF805FEB3; Tue, 09 Sep 2025 02:11:09 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v4 04/10] soc: sunxi: sram: register regmap as syscon Date: Tue, 9 Sep 2025 02:10:53 +0800 Message-Id: <20250908181059.1785605-5-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250908181059.1785605-1-wens@kernel.org> References: <20250908181059.1785605-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai If the system controller had a ethernet controller glue layer control register, a limited access regmap would be registered and tied to the system controller struct device for the ethernet driver to use. Until now, for the ethernet driver to acquire this regmap, it had to do a of_parse_phandle() + find device + dev_get_regmap() sequence. Since the syscon framework allows a provider to register a custom regmap for its device node, and the ethernet driver already uses syscon for one platform, this provides a much more easier way to pass the regmap. Use of_syscon_register_regmap() to register our regmap with the syscon framework so that consumers can retrieve it that way. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Fix check on return value - Expand commit message --- drivers/soc/sunxi/sunxi_sram.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 4f8d510b7e1e..1837e1b5dce8 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -12,6 +12,7 @@ =20 #include #include +#include #include #include #include @@ -377,6 +378,7 @@ static int __init sunxi_sram_probe(struct platform_devi= ce *pdev) const struct sunxi_sramc_variant *variant; struct device *dev =3D &pdev->dev; struct regmap *regmap; + int ret; =20 sram_dev =3D &pdev->dev; =20 @@ -394,6 +396,10 @@ static int __init sunxi_sram_probe(struct platform_dev= ice *pdev) regmap =3D devm_regmap_init_mmio(dev, base, &sunxi_sram_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); + + ret =3D of_syscon_register_regmap(dev->of_node, regmap); + if (ret) + return ret; } =20 of_platform_populate(dev->of_node, NULL, NULL, dev); --=20 2.39.5 From nobody Wed Sep 10 01:58:03 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3359B3191B5; Mon, 8 Sep 2025 18:11:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; cv=none; b=KZjkju3MdPEYkX6jeI9hQ0mO9OYN/bW7peKw/cBCWt7kdKYutzMihl6m3ZiwDG5s7BVZ9zrWSujPZZYB4Qoi40LfBHx5bwu0FGHh8vZZaNmizHOh0696Bz6y5ts+Ila0w4GG+DLHvT6/EJgSrvQxDf3LFkdYnXodE9vRaUth/lQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; c=relaxed/simple; bh=k8chtkdd/C7iCwiNiHHjJu/kaYcxaJejVp0B1FUTyf8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IB5IyKMbAWl1MmCw5HUD471qJgpPfmHKKnS6arSy/3aCtiZe8vxiQoKgJ3qTPKUIfkQtr7k/ugo2C5ckQPXfgZBWVnv6V/nAsn8yMnH04NemOrs/0BGbuC5s+73ODNUeGLZzA3KSM+ldUNWoPmZ/PuVpodVBcGgLpsMLiL4JlB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EmF5915p; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EmF5915p" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B8BE0C4CEFD; Mon, 8 Sep 2025 18:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757355073; bh=k8chtkdd/C7iCwiNiHHjJu/kaYcxaJejVp0B1FUTyf8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EmF5915pOJJpFpE+UR7m98cA+rX3ZUu7sIygZoawTdNQUmpBUdDafOeNw3o8+HkJC eZTVP9s9jLltIlUmZXGivNM7hUEB532Rvgl75FU/fFXwxRCJpKOb3JC0ZPGha2qOen Jm6cYvM2TIyDsfDiJyZUb6CCmZ4JvMTEK3gR+hh0naIgFZSpgh70FxoZEjA44KXWeT AkAnxubDGLIjEqdTYi8W1ImW7j6NxnTWd1sPPlpz/QmVSHEGPw0cPCxrzREDs37oyz IToKIDUsUbJlwnhmYb6Po6xIyeI7MoPxsrG/sm8mM+BFovUxNBTWipxTj5FWThrADP JuTSX6L3f5fvw== Received: by wens.tw (Postfix, from userid 1000) id 4962F5FF44; Tue, 09 Sep 2025 02:11:09 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v4 05/10] arm64: dts: allwinner: a523: Add GMAC200 ethernet controller Date: Tue, 9 Sep 2025 02:10:54 +0800 Message-Id: <20250908181059.1785605-6-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250908181059.1785605-1-wens@kernel.org> References: <20250908181059.1785605-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 SoC family has a second ethernet controller, called the GMAC200. It is not exposed on all the SoCs in the family. Add a device node for it. All the hardware specific settings are from the vendor BSP. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Fixed typo in tx-queues-config --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 6b6f2296bdff..449bcafbddcd 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -180,6 +180,16 @@ rgmii0_pins: rgmii0-pins { bias-disable; }; =20 + rgmii1_pins: rgmii1-pins { + pins =3D "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", + "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", + "PJ11", "PJ12", "PJ13", "PJ14", "PJ15"; + allwinner,pinmux =3D <5>; + function =3D "gmac1"; + drive-strength =3D <40>; + bias-disable; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; @@ -601,6 +611,51 @@ mdio0: mdio { }; }; =20 + gmac1: ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu RST_BUS_EMAC1>; + reset-names =3D "stmmaceth"; + interrupts =3D ; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 PD_VO1>; + syscon =3D <&syscon>; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config =3D <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac1_mtl_tx_setup>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + + queue0 {}; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0xf>; + snps,rd_osr_lmt =3D <0xf>; + snps,blen =3D <256 128 64 32 16 8 4>; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + + queue0 {}; + }; + }; + ppu: power-controller@7001400 { compatible =3D "allwinner,sun55i-a523-ppu"; reg =3D <0x07001400 0x400>; --=20 2.39.5 From nobody Wed Sep 10 01:58:03 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3341A3191A8; Mon, 8 Sep 2025 18:11:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; cv=none; b=NAyaK1dxm+KWQ6c17d8wr53d/yINwWSDIZBs8DNLg6nnGZCHvJ96QE4ujtDDroCMExR4SjgmpxGHl4oTzLFnuxzYImmtS5+cOJt7WNbDmia1/csjz/ZBmx0KVWrH6vL7CUbOZxpvg7F0O8Jj2q/go5ha6R2E5EO7kCH8u5o8dsM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; c=relaxed/simple; bh=CBUxzfQMcURd9xrdRX1X6MkdC4HdUWPC7RS7d5q4rC8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iaLgfuGM5DPpIFSsMHsQKxTvsSEUa2LsytsXAxUIEvh4nvLitwY2Svwz41Meyc4MnML3fNvxT0S3tukQMef807zOTHg3AcsIGoDFREDMIsRvJPPgv789n98K47DDG9wotUh/OWLiM8O6JqknX1cKHEG0vByConOOcwLz7jvDAZY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QoL2bmsq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QoL2bmsq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C5ECCC113D0; Mon, 8 Sep 2025 18:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757355074; bh=CBUxzfQMcURd9xrdRX1X6MkdC4HdUWPC7RS7d5q4rC8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QoL2bmsqrFTDNcyXn7/rTjjoOHFY6ciexniXAGJBY7IucNkeX0wgA6GiCd8cZHN29 AA4U4DT/VLcYDXhOo/lMdy72Ar+URZpgr/De5S9DLgQn9d7lnsZf2WXCyiqT283ZUv M7GFK+G1c+I2bWFQzXb2NdhjgkKGzjgX7FFLjT8f//1RW2VEwQtaAFPON6VK8eZC9T SFpeTw+/tJYvgVOQl1dBYRuMztB69btsD2Tl8IdTrI49iolxDvCHW+uvWYBwvIosaU sMHPNEO2WBDkpO7OUviTpug9ymTFTKPww357bSotk4KK5SOIbCnINggjAkVFKiX0Ts 8EQ2gPtn+/fVg== Received: by wens.tw (Postfix, from userid 1000) id 423F65FEEF; Tue, 09 Sep 2025 02:11:09 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v4 06/10] arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting Date: Tue, 9 Sep 2025 02:10:55 +0800 Message-Id: <20250908181059.1785605-7-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250908181059.1785605-1-wens@kernel.org> References: <20250908181059.1785605-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: acca163f3f51 ("arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E b= oard") Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 70d439bc845c..d4cee2222104 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -94,6 +94,9 @@ &mdio0 { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; }; }; =20 --=20 2.39.5 From nobody Wed Sep 10 01:58:03 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0F4731A059; Mon, 8 Sep 2025 18:11:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; cv=none; b=Wd6UOvkwqwKaR2NhmRi88klzKRqGyp993liH8SeMUgiYf2rNn0+Gy2IOAhD0VAJLLK3rvX0StJKAiz3uGRoq2R5EY/fzizzs5VOnwkuj05QW48bBHQRvsz9AYZaWb48k4xO+lmfeiKuTYrIBfQzbUaWF6Y1CXeYF0skEgDuYC8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; c=relaxed/simple; bh=1u87rs46+m5wL1Xw7aZOQ0O0nwgjPdStsou5RO+mPyc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ErAH5ro/DcvLnArjYAnCxcqaZciX+0nwO7UHYD0/bweHma5Q9r5VdtI2/WIyjSQ2NmFjRjUUcOdKi/q/6i6Eh1RboRPKIwYpazbljdY+dXMLzMUvcrY3pN2qcC15cRgHTzZga5V2mplnBAU5i7eL1KOvN69LuEP6o4WU0IaIq5o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FKZ6t9Ej; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FKZ6t9Ej" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7A1B3C4AF09; Mon, 8 Sep 2025 18:11:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757355074; bh=1u87rs46+m5wL1Xw7aZOQ0O0nwgjPdStsou5RO+mPyc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FKZ6t9EjeuFvlVYPdDV/X+7qVUk2cnIERi/G538DAyJOBxjxV6FcKDDgdgCatWZ4t lgRIzBxM+rRSlpqOBAII07Km0nbFQ630X3TBGwXLkLQsOg50eb8+0XhBfPamJE1h88 6h9Ji0RrmxPn+S7W+Ty86a0oPZGFc644RaF+6mPpG1tn9oyxHk8qIr8qdnhp83aZpL lHhxN5FMwq9kDSYlhk6iDTb27U346M+bFMDPzGbsPSce/CfKesb9rhLkZncD9dtFbw TJdY3SygngoKrc51mD8RkFSaxHG7SNzAnQbdHlY2cqsciQC5xft1+9NSaAidS6xHDy dQ1ldaaEfBuPQ== Received: by wens.tw (Postfix, from userid 1000) id 4E4555FF0D; Tue, 09 Sep 2025 02:11:09 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v4 07/10] arm64: dts: allwinner: a527: cubie-a5e: Enable second Ethernet port Date: Tue, 9 Sep 2025 02:10:56 +0800 Message-Id: <20250908181059.1785605-8-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250908181059.1785605-1-wens@kernel.org> References: <20250908181059.1785605-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Radxa Cubie A5E board, the second Ethernet controller, aka the GMAC200, is connected to a second external Maxio MAE0621A PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. An enable delay for the PHY supply regulator is added to make sure the PHY's internal regulators are fully powered and the PHY is operational. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Add PHY regulator delay --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index d4cee2222104..e96a419faf21 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -14,6 +14,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -76,7 +77,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_cldo3>; =20 allwinner,tx-delay-ps =3D <300>; @@ -85,13 +86,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <300>; + rx-internal-delay-ps =3D <400>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -100,6 +112,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ @@ -240,6 +262,8 @@ reg_cldo4: cldo4 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-name =3D "vcc-pj-phy"; + /* enough time for the PHY to fully power on */ + regulator-enable-ramp-delay =3D <150000>; }; =20 reg_cpusldo: cpusldo { --=20 2.39.5 From nobody Wed Sep 10 01:58:03 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 334D43191B1; Mon, 8 Sep 2025 18:11:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; cv=none; b=CfFvPLeIa2uMwt54/KUK020tg1o+BMV/V45NX2WE/erY4eP70F2iHcaiqAPLKMaO3tQF6obbrCVyeA+vLtCimZcgqzN61ocTg4wHsDGXDHlxN2ZalOL7fz4VopILX2RtDcHgVhDrh3dVUu3I9qq6uZM6O3hWPOctJB+gh4PR7bE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; c=relaxed/simple; bh=coKgeanaUZ3X4I0jziHLWfdNIN3UjLw9i/nP+qWcjHY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ik1P3yRUuge3DXXlrBEK1aoqCAGMGpm1ayMUBZdlepC469gQRxvsbh/VjSV1Pcr0qrjO9sz+XVREumPapabFlegjyXZVW9MqTFgMLP9TymOkn6fGamaA8Hylj6A6iCZVmMKMo1JwtcSgwGTKhj4VQBlM6w/o1+Vt4W1Wp57tqAA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NbjPAJVj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NbjPAJVj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BF70FC4CEF9; Mon, 8 Sep 2025 18:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757355073; bh=coKgeanaUZ3X4I0jziHLWfdNIN3UjLw9i/nP+qWcjHY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NbjPAJVj+Ccx1YTKZrvpsRHmbAEV0P6asEw8LJwiUJ/hVodfJHuxDiEB3U2dkEI6y NTrL18E/0x2Jj9reBGahfUtLqFZ1Wa/eCATTh3aKxaayBbifCy28Ra3bLf+7Q6EXTw Pik5J8qfj9NUWYfYNH0lduTRBKe3ig+seqEi6d/kwdYzNW9r8yWKhbFC5y6tfcFBi4 moOY7NR8iN5YVDsDwm1noOE0ecXRsjYZ8/IcataZX+EvcYAdtea4C3JS63q4LbPKYs jyt5oWNZVdgHo23+YafzlHasx82rfYbudDXTErU+BYqMH7c9xbNMJmT3Zk1go8JWEP JaZtukR2iu0Ag== Received: by wens.tw (Postfix, from userid 1000) id 5666E5FF5A; Tue, 09 Sep 2025 02:11:09 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v4 08/10] arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting Date: Tue, 9 Sep 2025 02:10:57 +0800 Message-Id: <20250908181059.1785605-9-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250908181059.1785605-1-wens@kernel.org> References: <20250908181059.1785605-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: c6800f15998b ("arm64: dts: allwinner: t527: add EMAC0 to Avaota-A1 b= oard") Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index b9eeb6753e9e..e7713678208d 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -85,6 +85,9 @@ &mdio0 { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; }; }; =20 --=20 2.39.5 From nobody Wed Sep 10 01:58:03 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 188FA31815E; Mon, 8 Sep 2025 18:11:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; cv=none; b=OKQ2XXpdvQmwgfSAeT1EmNXTcZN8k034pU6+qpMziE/OMNCIeq2X267LFmuRrQUFW8785FHrtnQvecNts8IrfJvLnCbdjeYFkZE5bGEyDpqj472YwSN/hN7+su4eTzGns3EYL1mVYSci0uFbYIQhHsMGBLHPtCMlzH5bYu2rLFk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; c=relaxed/simple; bh=KwQ33/Me6CtoPqF903pwWNvdntE/FNahw7BHgwIWeoE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KJOBZ1vQk2zsIXrvx0INiPEQ/YLCVOEFvj+WU3R1Zl9WsrPDQe6QlrMZXmH+tP7Kue7x0hE1/ZEK+EiZIvdpnJQFdj78WKX+yq1arpOFk3swOVW/82DP6ixUd+XU5w5Mr7o/4WAJTQXXldASlZuQTa2THBFboLGPJDVEKE1L044= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZnJYmZan; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZnJYmZan" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C5638C113CF; Mon, 8 Sep 2025 18:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757355074; bh=KwQ33/Me6CtoPqF903pwWNvdntE/FNahw7BHgwIWeoE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZnJYmZanz8ySftbkC/oRaB91MOOJ+Q5iana60PBbjbCfhuFHokJiwySTIEzDmbOtI ThtyYccx76x53Juj+YHXCRhoMY19EeavtFsarTd6xCj73D4ft7M8kjYcrrxVAJGf0f KcYH+H2Q7/MST6LAC19+2z6PhSb5saxWW4udOJb4dcxCYgy00ueX3pefFX9YgXq2bz LgkD79/NiPtbsu+NyR0C7w++0JhyM0UxMx9FW8dYY6dOAK+kSmcdIMPowK8ZmxaybH 8O0amtnyo9iMtiXtbZCmynq85sPNMQA+xyNarzczzaeTPDfdXizgfyN1mZiD5FX0kh 3cIw6HyRKMroQ== Received: by wens.tw (Postfix, from userid 1000) id 645E85FF75; Tue, 09 Sep 2025 02:11:09 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v4 09/10] arm64: dts: allwinner: t527: avaota-a1: enable second Ethernet port Date: Tue, 9 Sep 2025 02:10:58 +0800 Message-Id: <20250908181059.1785605-10-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250908181059.1785605-1-wens@kernel.org> References: <20250908181059.1785605-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Avaota A1 board, the second Ethernet controller, aka the GMAC200, is connected to a second external RTL8211F-CG PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-avaota-a1.dts | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index e7713678208d..f540965ffaa4 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -13,6 +13,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -67,7 +68,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_dcdc4>; =20 allwinner,tx-delay-ps =3D <100>; @@ -76,13 +77,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_dcdc4>; + + tx-internal-delay-ps =3D <100>; + rx-internal-delay-ps =3D <100>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -91,6 +103,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5 From nobody Wed Sep 10 01:58:03 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3352B3191B4; Mon, 8 Sep 2025 18:11:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; cv=none; b=SKYUUjABGfqncUGRrnchJpJ7Odh7Dbwu4mJpSPe3qHZfFj1UkwBkvpfAYP7LH/ZPZ91zNnABE0/Q6LewOyJXfb85yeGUpzU9cp7nM3z4Up3qY8xkJlFhDCnhuQTvf4FxjRzySX2AYb4hNQqc7m8P/yq+D3KKcCwMaFT2aIgJRCA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757355074; c=relaxed/simple; bh=zJ4rq1A7rDmdHeQfB8ynFE9503F7ovKFxfivFN/5hPw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MTdBgKXtpS9zOVRtuaRBxVuqWwZRJaJXd5UQB4Blp86rWkwFQ/6LDcLNpgMt4QXjwkVqi/cyl/Z+Mg2TWkn5EFPiIhY669oDytsIxU14tMH/GXXPOAgF9WwTYITPLVjULfK67PoD/21g6CQ0zpvV6PSjOYy7wPiNztS4uRlT/D4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hQ7y1IxU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hQ7y1IxU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B5601C4CEFC; Mon, 8 Sep 2025 18:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757355073; bh=zJ4rq1A7rDmdHeQfB8ynFE9503F7ovKFxfivFN/5hPw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hQ7y1IxUPVquvYgy5yUlyXqwhJc6iLQCwcSIFcqEjolAZNOyLB6+v3SRR2bxwaYTP dn0GnEftM+3JCtzI28l+z6EtBy2t2V6M8qGgtDu2XsnUSIndOr5LBM5CrRiHyydBaa TIg6n5G33v5pQ3tM7uVIf5GiGEXvIbGmX/+3Ece2SGgRMdinljCU6As5Kipc/H9xL7 1/dxb+RAntzX9qc8L12Z5ARFPiZvngI4B9DbAd6h+8DdXN7peM19tvbGyUens0F9KP 21lN9HzQQNf4b6c52XDkRRmKGzgGQpDPabLAx5UYqUM9TZJSga7yj07X5355fSPi98 x8R6mDUh6svYQ== Received: by wens.tw (Postfix, from userid 1000) id 68C9B5FFA1; Tue, 09 Sep 2025 02:11:09 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v4 10/10] arm64: dts: allwinner: t527: orangepi-4a: Enable Ethernet port Date: Tue, 9 Sep 2025 02:10:59 +0800 Message-Id: <20250908181059.1785605-11-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250908181059.1785605-1-wens@kernel.org> References: <20250908181059.1785605-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Orangepi 4A board, the second Ethernet controller, aka the GMAC200, is connected to an external Motorcomm YT8531 PHY. The PHY uses an external 25MHz crystal, has the SoC's PI15 pin connected to its reset pin, and the PI16 pin for its interrupt pin. Enable it. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 38cd8c7e92da..7afd6e57fe86 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -15,6 +15,7 @@ / { compatible =3D "xunlong,orangepi-4a", "allwinner,sun55i-t527"; =20 aliases { + ethernet0 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -95,11 +96,33 @@ &ehci1 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <0>; + rx-internal-delay-ps =3D <300>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 +&mdio1 { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupts-extended =3D <&pio 8 16 IRQ_TYPE_LEVEL_LOW>; /* PI16 */ + reset-gpios =3D <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5