From nobody Wed Sep 10 05:59:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 480013126D1; Mon, 8 Sep 2025 16:31:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757349113; cv=none; b=JVwy80csCrtNDLzpEgIXiBwcvjvsdcSBCSMAumonRMYvXjnt3TvmSX+lT7fuJiBO2rzOWR3WMHgSN8vR5oxTzdet7iHeGA0c0VsYnLdLWCFZ8d4GJ7q5pCAZcmvnSycHynz7Kwlk1vH8EFnRPWbnvT9oGrsFDuW01tur13CEy40= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757349113; c=relaxed/simple; bh=zMQRaJoyFUYzTVpLFAFRUWCGuYufHSxl4b1HcSp9Kzk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fmOI3s6HD0xNusF2vXEwlhmVwYS505oO9AoF0GINACGbpoL9finAASXjpwuk2BbuGpjByBTni2lVlfl2kfCKSTIlWy892W4G2yzUhJeLsQDSni56fUeei0LN4fucquADdsSyTQMJsJjq25r4nYPlwLCJOT+AiaI84HxfwN/yTII= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=f3V3amZs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="f3V3amZs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 082EFC4AF0C; Mon, 8 Sep 2025 16:31:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757349113; bh=zMQRaJoyFUYzTVpLFAFRUWCGuYufHSxl4b1HcSp9Kzk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f3V3amZsFt/DMSg/6ruYiOpg02JWsF8FSgfy4jJMdovBwN5rC36sF06JSoBXoMr1Q ifPdvY02d6yhKOi8a0Y0se3BgZ1x9+bfPhcLnKAU8elG8O8JYjN6bUMD3VbR5fJU47 o1RiYzVE4IcETTO46mz4Cq/pVBKpaEbpXCu1LLMob/bU/WkPJ6M21xGcGH2+l5LC3+ 4TJfap10a7QYCYpvnNarygNFxA2VadF/62vHBO+mQ91eXMBq4zA3yZcFzJU0dXi0Pi ZdPkwWJuAeXlgIpysulJ1rNAwmAZTWdrTV6s4q9lptnwLgdkPkbksz4kVQC0NY6B+Z tpNaVVuAIL9vw== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1uvemV-00000004NTm-0x1e; Mon, 08 Sep 2025 16:31:51 +0000 From: Marc Zyngier To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: Thomas Gleixner , Mark Rutland , Will Deacon , "Rafael J. Wysocki" , Rob Herring , Saravana Kannan , Greg Kroah-Hartman , Sven Peter , Janne Grunau , Suzuki K Poulose , James Clark Subject: [PATCH 21/25] irqchip/gic-v3: Drop support for custom PPI partitions Date: Mon, 8 Sep 2025 17:31:23 +0100 Message-Id: <20250908163127.2462948-22-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250908163127.2462948-1-maz@kernel.org> References: <20250908163127.2462948-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, tglx@linutronix.de, mark.rutland@arm.com, will@kernel.org, rafael@kernel.org, robh@kernel.org, saravanak@google.com, gregkh@linuxfoundation.org, sven@kernel.org, j@jannau.net, suzuki.poulose@arm.com, james.clark@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" We are finally getting there. The only thing getting in the way of correctly handling PPIs in the way they were intended is to drop the GICv3 hack that deals with PPI partitions. Signed-off-by: Marc Zyngier --- drivers/irqchip/Kconfig | 1 - drivers/irqchip/irq-gic-v3.c | 133 +++-------------------------------- 2 files changed, 8 insertions(+), 126 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 6d12c6ab9ea47..c31d2f99d7b91 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -36,7 +36,6 @@ config GIC_NON_BANKED config ARM_GIC_V3 bool select IRQ_DOMAIN_HIERARCHY - select PARTITION_PERCPU select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP select HAVE_ARM_SMCCC_DISCOVERY select IRQ_MSI_IOMMU diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 4a90dbf9daedb..cdf6fac32908d 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -46,8 +45,6 @@ static u8 dist_prio_nmi __ro_after_init =3D GICV3_PRIO_NM= I; #define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 2) #define FLAGS_WORKAROUND_INSECURE (1ULL << 3) =20 -#define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) - static struct cpumask broken_rdists __read_mostly __maybe_unused; =20 struct redist_region { @@ -68,11 +65,15 @@ struct gic_chip_data { u64 flags; bool has_rss; unsigned int ppi_nr; - struct partition_desc **ppi_descs; struct partition_affinity *parts; unsigned int nr_parts; }; =20 +struct partition_affinity { + cpumask_t mask; + struct fwnode_handle *partition_id; +}; + #define T241_CHIPS_MAX 4 static void __iomem *t241_dist_base_alias[T241_CHIPS_MAX] __read_mostly; static DEFINE_STATIC_KEY_FALSE(gic_nvidia_t241_erratum); @@ -596,18 +597,6 @@ static void gic_irq_set_prio(struct irq_data *d, u8 pr= io) writeb_relaxed(prio, base + offset + index); } =20 -static u32 __gic_get_ppi_index(irq_hw_number_t hwirq) -{ - switch (__get_intid_range(hwirq)) { - case PPI_RANGE: - return hwirq - 16; - case EPPI_RANGE: - return hwirq - EPPI_BASE_INTID + 16; - default: - unreachable(); - } -} - static u32 __gic_get_rdist_index(irq_hw_number_t hwirq) { switch (__get_intid_range(hwirq)) { @@ -1668,13 +1657,6 @@ static int gic_irq_domain_translate(struct irq_domai= n *d, case GIC_IRQ_TYPE_LPI: /* LPI */ *hwirq =3D fwspec->param[1]; break; - case GIC_IRQ_TYPE_PARTITION: - *hwirq =3D fwspec->param[1]; - if (fwspec->param[1] >=3D 16) - *hwirq +=3D EPPI_BASE_INTID - 16; - else - *hwirq +=3D 16; - break; default: return -EINVAL; } @@ -1683,10 +1665,8 @@ static int gic_irq_domain_translate(struct irq_domai= n *d, =20 /* * Make it clear that broken DTs are... broken. - * Partitioned PPIs are an unfortunate exception. */ - WARN_ON(*type =3D=3D IRQ_TYPE_NONE && - fwspec->param[0] !=3D GIC_IRQ_TYPE_PARTITION); + WARN_ON(*type =3D=3D IRQ_TYPE_NONE); return 0; } =20 @@ -1743,32 +1723,11 @@ static void gic_irq_domain_free(struct irq_domain *= domain, unsigned int virq, } } =20 -static bool fwspec_is_partitioned_ppi(struct irq_fwspec *fwspec, - irq_hw_number_t hwirq) -{ - enum gic_intid_range range; - - if (!gic_data.ppi_descs) - return false; - - if (!is_of_node(fwspec->fwnode)) - return false; - - if (fwspec->param_count < 4 || !fwspec->param[3]) - return false; - - range =3D __get_intid_range(hwirq); - if (range !=3D PPI_RANGE && range !=3D EPPI_RANGE) - return false; - - return true; -} - static int gic_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec, enum irq_domain_bus_token bus_token) { - unsigned int type, ret, ppi_idx; + unsigned int type, ret; irq_hw_number_t hwirq; =20 /* Not for us */ @@ -1787,15 +1746,7 @@ static int gic_irq_domain_select(struct irq_domain *= d, if (WARN_ON_ONCE(ret)) return 0; =20 - if (!fwspec_is_partitioned_ppi(fwspec, hwirq)) - return d =3D=3D gic_data.domain; - - /* - * If this is a PPI and we have a 4th (non-null) parameter, - * then we need to match the partition domain. - */ - ppi_idx =3D __gic_get_ppi_index(hwirq); - return d =3D=3D partition_get_domain(gic_data.ppi_descs[ppi_idx]); + return d =3D=3D gic_data.domain; } =20 static int gic_irq_get_info(struct irq_fwspec_info *info) @@ -1854,45 +1805,6 @@ static const struct irq_domain_ops gic_irq_domain_op= s =3D { .get_info =3D gic_irq_get_info, }; =20 -static int partition_domain_translate(struct irq_domain *d, - struct irq_fwspec *fwspec, - unsigned long *hwirq, - unsigned int *type) -{ - unsigned long ppi_intid; - struct device_node *np; - unsigned int ppi_idx; - int ret; - - if (!gic_data.ppi_descs) - return -ENOMEM; - - np =3D of_find_node_by_phandle(fwspec->param[3]); - if (WARN_ON(!np)) - return -EINVAL; - - ret =3D gic_irq_domain_translate(d, fwspec, &ppi_intid, type); - if (WARN_ON_ONCE(ret)) - return 0; - - ppi_idx =3D __gic_get_ppi_index(ppi_intid); - ret =3D partition_translate_id(gic_data.ppi_descs[ppi_idx], - of_fwnode_handle(np)); - if (ret < 0) - return ret; - - *hwirq =3D ret; - *type =3D fwspec->param[2] & IRQ_TYPE_SENSE_MASK; - - return 0; -} - -static const struct irq_domain_ops partition_domain_ops =3D { - .translate =3D partition_domain_translate, - .select =3D gic_irq_domain_select, - .get_info =3D gic_irq_get_info, -}; - static bool gic_enable_quirk_msm8996(void *data) { struct gic_chip_data *d =3D data; @@ -2225,12 +2137,7 @@ static void __init gic_populate_ppi_partitions(struc= t device_node *gic_node) if (!parts_node) return; =20 - gic_data.ppi_descs =3D kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_desc= s), GFP_KERNEL); - if (!gic_data.ppi_descs) - goto out_put_node; - nr_parts =3D of_get_child_count(parts_node); - if (!nr_parts) goto out_put_node; =20 @@ -2286,30 +2193,6 @@ static void __init gic_populate_ppi_partitions(struc= t device_node *gic_node) gic_data.parts =3D parts; gic_data.nr_parts =3D nr_parts; =20 - for (i =3D 0; i < gic_data.ppi_nr; i++) { - unsigned int irq; - struct partition_desc *desc; - struct irq_fwspec ppi_fwspec =3D { - .fwnode =3D gic_data.fwnode, - .param_count =3D 3, - .param =3D { - [0] =3D GIC_IRQ_TYPE_PARTITION, - [1] =3D i, - [2] =3D IRQ_TYPE_NONE, - }, - }; - - irq =3D irq_create_fwspec_mapping(&ppi_fwspec); - if (WARN_ON(!irq)) - continue; - desc =3D partition_create_desc(gic_data.fwnode, parts, nr_parts, - irq, &partition_domain_ops); - if (WARN_ON(!desc)) - continue; - - gic_data.ppi_descs[i] =3D desc; - } - out_put_node: of_node_put(parts_node); } --=20 2.39.2