From nobody Wed Sep 10 06:02:25 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D0D430CDA0; Mon, 8 Sep 2025 14:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341772; cv=none; b=V479li+wG+KustNdM68ocbsPCp+6kFQpPtJVZCwAAr0O/40lf52U1MPTvFzxEGQN6AY4xXXMthd8ULt5kOY0gUZeisHdbPK6aAYQzSEhuSifEXQfrXDpxpiTqTI+1xonQOMKWT2lvtxTO7eihTPK71gKlSLp6X7n/WA64twKZ7I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341772; c=relaxed/simple; bh=Czz4akFVG59N+rjaaPq2vtuDFQb/j94ID7gZeCgnzS4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=am1snsYlVAAKVM9GU2F8Umu18U2G3ZwL4J7IddE4oRIp2hKlgs5yUkK9r9kIs1uct57pd23ZQhIcBkBROviKIKIx/ZGLL6iTRSLI5U8UT1K3P/iHWHmwmHdPD/ofEIgeYZSdu36CU9et5e0cSFpP9wl/LEwZaOr0o+ZzQkHXagI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=xeVNTehk; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xeVNTehk" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 588ETPFO120230; Mon, 8 Sep 2025 09:29:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757341765; bh=+MmfN1IQYEE8r5e1s4yKjVfzY5BZ6vPdwdrmD6/gUoo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xeVNTehkFZGpL7OxA9s1Fz5/eooklS2lkqoSqCPsasWl7ihuwgRqsdaj8ZsCvuwmm TRwkW9tOf+SXgM/svbQrWULRvjvXe9eAuLR3zeflQaXh+GFxrwIGDTY8Vxmfpa3Hs0 SsQ2PVeW2wESMZyZ+WrAuWcHaVTv5yQzo0kf7xI0= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 588ETPX43019519 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 09:29:25 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:29:24 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:29:24 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecj1037553; Mon, 8 Sep 2025 09:29:20 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 07/34] arm64: dts: ti: k3-am62a: Enable remote processors at board level Date: Mon, 8 Sep 2025 19:57:59 +0530 Message-ID: <20250908142826.1828676-8-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level AM62A SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Tested-by: Judith Mendez --- v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-8-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B, T/B tags. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-8-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 24/33] to [PATCH v2 07/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-25-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 1 + 5 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts= /ti/k3-am62a-mcu.dtsi index ee961ced7208..d22caa7c346b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -197,6 +197,7 @@ mcu_r5fss0_core0: r5f@79000000 { ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <9>; ti,sci-proc-ids =3D <0x03 0xff>; + status =3D "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/= boot/dts/ti/k3-am62a-phycore-som.dtsi index 207ca00630d1..403adfbf7dce 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -406,6 +406,7 @@ &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_mcu_r5_0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &ospi0 { @@ -444,4 +445,5 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62a-wakeup.dtsi index 9ef1c829a9df..23877dadc98d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -127,6 +127,7 @@ wkup_r5fss0_core0: r5f@78000000 { ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <121>; ti,sci-proc-ids =3D <0x01 0xff>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index bceead5e288e..03291862f07a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -870,6 +870,7 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0>, <&mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &mcu_r5fss0 { @@ -880,6 +881,7 @@ &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &c7x_0 { diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62d2-evm.dts index daea18b0bc61..d45fc42b03f3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -586,6 +586,7 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; bootph-pre-ram; }; =20 --=20 2.34.1