From nobody Wed Sep 10 06:02:25 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3309F30DD11; Mon, 8 Sep 2025 14:29:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341759; cv=none; b=gIM2HgjMug+G2/Ufi2m7eGZhKvPXqqtzU6qKZdpcOjtnbljLFDtcY/R4LipnAWOcDRYRflh0cvYNTLwBcmyZVngRDQmbS8cNZE4duo8V3onyRVnOQAqgEnO4CIOF3W1tXM/j9WVEjc9C52wBHZ/TyHO94VcT5wZuJWmICwoo7NA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341759; c=relaxed/simple; bh=JvRRlcSCw8fAOExv2zFLwikKXll00+ytwt1i/OAHFiE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NesZb1iKjis7eOdZaOoJXS/6DX+PJZIIHzHABURUDq8ezFQ25E3FsFbbpVHT1ybtBGc7guG3ltLyQxrMONY+9E2nJ3qycRfeva76bHYHazivBHQukfNucyQOmKUQGMZhaakpr7kzKgGnmdV5OXBB8CTOd52hzjqF+zT7TTroXEA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Q8ONq12q; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Q8ONq12q" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 588ETAbI3883021; Mon, 8 Sep 2025 09:29:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757341750; bh=oYmqmDcavZhbioQhWBZ1l9KsdHUtq0/7Xk+DnYj/bRA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Q8ONq12qBhGDCbSQ/e6DoSqWBjqOt1j5G5jsLGeNBD+C8oIJ7zE1zVVp22vAGh37k m8ajdsPGPmoO2MCZ5Rv3kJ62VPRsXJCALO5zojydfPpzgH8D3rCqUiznHL1kJbzgc+ +arPW5LAXqtmUsYxOas7vcIcHb8NwELTK2LFjFGU= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 588ETA0T3063556 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 09:29:10 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:29:10 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:29:10 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecg1037553; Mon, 8 Sep 2025 09:29:05 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 04/34] arm64: dts: ti: k3-j784s4-j742s2: Enable remote processors at board level Date: Mon, 8 Sep 2025 19:57:56 +0530 Message-ID: <20250908142826.1828676-5-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level J784S4-J742S2 common SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis --- v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-5-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B tag. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-5-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 10/33] to [PATCH v2 04/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-11-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am69-sk.dts | 15 +++++++++++++++ .../boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 7 +++++++ .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 9 +++++++++ .../ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi | 3 +++ 4 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index f4f7b89bf0d2..af8eafc3f54a 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -992,24 +992,32 @@ &mcu_cpsw_port1 { bootph-all; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &mcu_r5fss0_core1 { mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 &main_r5fss1 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 /* Timers are used by Remoteproc firmware */ @@ -1055,42 +1063,49 @@ &main_timer9 { =20 &main_r5fss2 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 &main_r5fss2_core0 { mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; memory-region =3D <&main_r5fss2_core0_dma_memory_region>, <&main_r5fss2_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss2_core1 { mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; memory-region =3D <&main_r5fss2_core1_dma_memory_region>, <&main_r5fss2_core1_memory_region>; + status =3D "okay"; }; =20 &c71_0 { diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index 6afa802544e9..c269e5b29b96 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -1154,6 +1154,10 @@ mbox_c71_2: mbox-c71-2 { }; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { status =3D "okay"; mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; @@ -1170,14 +1174,17 @@ &mcu_r5fss0_core1 { =20 &main_r5fss0 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 &main_r5fss1 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 &main_r5fss2 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 /* Timers are used by Remoteproc firmware */ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arc= h/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index fbbe768e7a30..9cc0901d58fb 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -2174,6 +2174,7 @@ main_r5fss0: r5fss@5c00000 { ranges =3D <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains =3D <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss0_core0: r5f@5c00000 { compatible =3D "ti,j721s2-r5f"; @@ -2188,6 +2189,7 @@ main_r5fss0_core0: r5f@5c00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss0_core1: r5f@5d00000 { @@ -2203,6 +2205,7 @@ main_r5fss0_core1: r5f@5d00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 @@ -2214,6 +2217,7 @@ main_r5fss1: r5fss@5e00000 { ranges =3D <0x5e00000 0x00 0x5e00000 0x20000>, <0x5f00000 0x00 0x5f00000 0x20000>; power-domains =3D <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss1_core0: r5f@5e00000 { compatible =3D "ti,j721s2-r5f"; @@ -2228,6 +2232,7 @@ main_r5fss1_core0: r5f@5e00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss1_core1: r5f@5f00000 { @@ -2243,6 +2248,7 @@ main_r5fss1_core1: r5f@5f00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 @@ -2254,6 +2260,7 @@ main_r5fss2: r5fss@5900000 { ranges =3D <0x5900000 0x00 0x5900000 0x20000>, <0x5a00000 0x00 0x5a00000 0x20000>; power-domains =3D <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss2_core0: r5f@5900000 { compatible =3D "ti,j721s2-r5f"; @@ -2268,6 +2275,7 @@ main_r5fss2_core0: r5f@5900000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss2_core1: r5f@5a00000 { @@ -2283,6 +2291,7 @@ main_r5fss2_core1: r5f@5a00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi= b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index 52e2965a3bf5..cc22bfb5f599 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -595,6 +595,7 @@ mcu_r5fss0: r5fss@41000000 { ranges =3D <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains =3D <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 mcu_r5fss0_core0: r5f@41000000 { compatible =3D "ti,j721s2-r5f"; @@ -609,6 +610,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 mcu_r5fss0_core1: r5f@41400000 { @@ -624,6 +626,7 @@ mcu_r5fss0_core1: r5f@41400000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 --=20 2.34.1