From nobody Wed Sep 10 05:55:15 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 917FB312836; Mon, 8 Sep 2025 14:31:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341892; cv=none; b=XwIpxdZy0ELCjbM1t7mxznZ7WjRAGPz+AH7VFWJbMrjRXnp6raa+LReSKmwcv6+GGj1O6mNWdTdZNhc3x5Bo9NGRbElcod3506AqpFXQ/YwUeynoimwOUdW25fAgaARYt2e2IyOPuJLClffh/krWCjbfnLTnlNaQ7CQwTr8NC08= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341892; c=relaxed/simple; bh=GG0NQ0Ch3U4h+L7LgPwgmIwoTVZU5ojvbWH9JFkM5uk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZC8epAmA9SCrfoQOEBrY9bGm9MSROXeEKle6DFPwqtWK7DKR0CORa6nIq3TvSYToSCO7WZNoVcqKYEKFJ5zpcsOjLZ/lfpT2qn4IDMoyIE/FNdGS/MhA/9joyVzj2ISwmttnlKc57FzPs6Rd0ZOsr/mH+/UivywItQP8Pqp5B/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=RSFfBlzd; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="RSFfBlzd" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 588EVQrk072034; Mon, 8 Sep 2025 09:31:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757341886; bh=Ag2nFBWKbKH3lm2NQIfVXxyGLoETIZJG5xVL5KhUQVA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RSFfBlzd878kL1rgm7URYdy9rxkf/BYLwFeOe5owpFQCNLLm2e2yzqths+d4tC7Qv /q2uxam9A7oGwIrgvRdNL253IVEDAZXIJMbnnWXFvGphtBfAqHLcINR9UXG5esdNUx vesDDguU7kTVCslma3mRH8fwz9WKbnNfV9UT7A2c= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 588EVQ6G3836049 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 09:31:26 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:31:25 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:31:25 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESed81037553; Mon, 8 Sep 2025 09:31:21 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 30/34] arm64: dts: ti: k3-am62p-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Mon, 8 Sep 2025 19:58:22 +0530 Message-ID: <20250908142826.1828676-31-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 AM62P SoCs have multiple programmable remote processors like R5Fs. The TI SDKs for AM62P SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Tested-by: Judith Mendez Reviewed-by: Dhruva Gole --- v4: Changelog: 1. Updated node names to generic 'memory@addr' 2. Carried R/B tag. Link to v3: https://lore.kernel.org/all/20250905051846.1189612-30-b-padhi@ti.com/ v3: Changelog: 1. Carried T/B tag. 2. Changed memory node name to memory@addr. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-30-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 17/33] to [PATCH v2 29/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-18-b-padhi@ti.com/ .../boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi | 60 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 54 +---------------- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 54 +---------------- 3 files changed, 64 insertions(+), 104 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi b/arch/ar= m64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..d29a5dbe13ef --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM62P SoCs + * + * Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/= dts/ti/k3-am62p-verdin.dtsi index 671d367b40d1..99810047614e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -162,18 +162,6 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@9b900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c800000 0x00 0x100000>; @@ -848,46 +836,6 @@ &epwm2 { status =3D "disabled"; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - &main0_alert { temperature =3D <95000>; }; @@ -1466,3 +1414,5 @@ &wkup_uart0 { uart-has-rtscts; status =3D "disabled"; }; + +#include "k3-am62p-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index aa363aaf6d59..56f0eb11b902 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -49,18 +49,6 @@ reserved_memory: reserved-memory { #size-cells =3D <2>; ranges; =20 - mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@9b900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c800000 0x00 0x100000>; @@ -699,46 +687,6 @@ partition@3fc0000 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - &main_uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins_default>; @@ -810,3 +758,5 @@ &epwm1 { pinctrl-0 =3D <&main_epwm1_pins_default>; status =3D "okay"; }; + +#include "k3-am62p-ti-ipc-firmware.dtsi" --=20 2.34.1