From nobody Wed Sep 10 05:52:55 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF45A1DF26E; Mon, 8 Sep 2025 14:30:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341846; cv=none; b=G8rpnLQ/0gheRdHMVrhCD/M/RE5rEnpe82IRTfT1nvAe88nuweCSPsgxJ4nriGZuqaPsp/6o5qRgyvyW4otQJpe5L2EAxmqeu1dnl7tq6YOagE//p/zvkMhr8EKQcs4530mLr3uhADfmeQ+FKDL0bA+Ap12o5D083+j6bMN0FTc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341846; c=relaxed/simple; bh=tsEBDBmRULEMBJ2eXXYee3Y6YWJ6kKce90MqXTpxQjM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=chbNmsXqcL00MCLAvYTH6+3QjNz7pSHKT1M3nNkJB2QfcfhrGb2/KbMTvVuPPLuyzJm9OWyjp4u20DnbYV+EEbyDFhpeZ2kN9MmKrJeVIKazHm73HwoNKQJ1BWVf/iwvvudBLytoq6M4BbxzK1EDQp2AC+wMdAGo6Eu3R9c64eQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=UnJ1mXmx; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="UnJ1mXmx" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 588EUcvQ3883548; Mon, 8 Sep 2025 09:30:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757341838; bh=KNDeTcriY+g/ZMvH40cW+600x4qCRysa7bksKPsxzYc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UnJ1mXmx6SP/xzO9f4GflYr+OkuIkhAFZlonhryotMII6/UknpuTLMQ9ZRJ0MqxIM tIGne+4N0E1HnOj/xUmiZL8q9dWKFbIloEaunNSHAFY3Piu1ITfSlu0G9zDgm8m0sv hthmET8aWnsUMvGGzIbE+BIxs5rSxX9So/UAsCdU= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 588EUcUL3021101 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 09:30:38 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:30:38 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:30:38 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecw1037553; Mon, 8 Sep 2025 09:30:33 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Matthias Schiffer Subject: [PATCH v4 20/34] arm64: dts: ti: k3-am642-tqma64xxl: Add missing cfg for TI IPC Firmware Date: Mon, 8 Sep 2025 19:58:12 +0530 Message-ID: <20250908142826.1828676-21-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Currently, only R5F remote processors are enabled for k3-am642-tqma64xxl whereas the M4F in MCU domain is disabled. Enable the M4F remote processor at board level by reserving memory carveouts and assigning mailboxes. While at it, reserve the MAIN domain timers that are used by R5F remote processors for ticks to avoid rproc crashes. This config aligns with other AM64 boards and can be refactored out later. Signed-off-by: Beleswar Padhi --- Cc: Matthias Schiffer Request for review/test of this patch. v4: Changelog: 1. Updated carveout node names to generic 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-20-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-20-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 29/33] to [PATCH v2 19/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-30-b-padhi@ti.com/ .../arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am642-tqma64xxl.dtsi index 4068d2c2b10c..f6d1e980d32f 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -79,6 +79,18 @@ main_r5fss1_core1_memory_region: memory@a3100000 { no-map; }; =20 + mcu_m4fss_dma_memory_region: memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: memory@a5000000 { reg =3D <0x00 0xa5000000 0x00 0x00800000>; alignment =3D <0x1000>; @@ -167,6 +179,26 @@ mbox_m4_0: mbox-m4-0 { }; }; =20 +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status =3D "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status =3D "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status =3D "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status =3D "reserved"; +}; + &main_r5fss0 { status =3D "okay"; }; @@ -203,6 +235,13 @@ &main_r5fss1_core1 { status =3D "okay"; }; =20 +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + &ospi0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.34.1