From nobody Wed Sep 10 06:02:22 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A87081A9FA8; Mon, 8 Sep 2025 14:30:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341820; cv=none; b=iBnOtTmJE9w9wztYZpIoUCTzq8bxkfnzsK/ECD+/jYql/zUdT2FkvlMTYA8mOL7tWbpxh8MNp5bz0/50QMknlBzBlAMQ63J0BH0/z4Jx38D3A/qPdWWyDDTgGHZDXp8da9pR+YmHxtTFKENZ1QHsNCSEteOsCqpANdXDSlSM8v4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341820; c=relaxed/simple; bh=mCvNefpm3X1d5CPBNW2nvQeu6euRRme4omoZM/wmVo4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mRjefNq+QA6PByECU8Irv1zjUfLnCtfn9BOSjMiBE+tAFlmPxX9YO+IuHSu/ERBnbOPK7cm5vICeLYfDh/sE1ZkDk+YU166CAp6orpheie/SPbMFjhdfHExvV8JzxZiZaQI8D9i+LsqwNCddLbuJ+B9+ya++xTz1ghHsEiyAT/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=dO16PSg5; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="dO16PSg5" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 588EUAq6071614; Mon, 8 Sep 2025 09:30:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757341810; bh=b0wBhaKXtjGUz6kkTHFGePg1AFzstofbpng1uUtJ6YM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dO16PSg5U7CIvzY3bV6MPf93Z9+lBxAxCaomWmyJmmbtk8XogytPlO7j4FnqIJdmI 5h+vKB8vR7n4xDB2wfdFAZIfxkzFnBiaxmlMm82e1gGQKqYgL01CavKZH7feNYMXAK nQyTAdygj7POHQrxkUiAJposjRTnbw+D+icbgM5E= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 588EUAkL3020760 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 09:30:10 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:30:10 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:30:10 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecr1037553; Mon, 8 Sep 2025 09:30:04 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Hiago De Franco , Francesco Dolcini , Emanuele Ghidoli , Parth Pancholi , Jo_o Paulo Gon_alves Subject: [PATCH v4 15/34] arm64: dts: ti: k3-am62p-verdin: Add missing cfg for TI IPC Firmware Date: Mon, 8 Sep 2025 19:58:07 +0530 Message-ID: <20250908142826.1828676-16-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The wkup_r5fss0_core0_memory_region is used to store the text/data sections of the Device Manager (DM) firmware itself and is necessary for platform boot. Whereas the wkup_r5fss0_core0_dma_memory_region is used for allocating the Virtio buffers needed for IPC with the DM core which could be optional. The labels were incorrectly used in the k3-am62p-verdin.dtsi file. Correct the firmware memory region label. Currently, only mailbox node is enabled with FIFO assignment. However, there are no users of the enabled mailboxes. Add the missing carveouts for WKUP and MCU R5F remote processors, and enable those by associating to the above carveout and mailboxes. This config aligns with other AM62P boards and can be refactored out later. Signed-off-by: Beleswar Padhi Tested-by: Hiago De Franco # Verdin AM62P Acked-by: Francesco Dolcini --- Cc: Francesco Dolcini Cc: Emanuele Ghidoli Cc: Parth Pancholi Cc: Jo_o Paulo Gon_alves Cc: Hiago De Franco Requesting for a review/test. v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-15-b-padhi@ti.com/ v3: Changelog: 1. Changed carveout node names to memory@addr. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-15-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 16/33] to [PATCH v2 14/33]. 2. Added T/B tag. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-17-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/= dts/ti/k3-am62p-verdin.dtsi index 522d6f029c36..671d367b40d1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -162,6 +162,24 @@ secure_ddr: optee@9e800000 { no-map; }; =20 + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c900000 0x00 0x01e00000>; @@ -848,6 +866,28 @@ mbox_mcu_r5_0: mbox-mcu-r5-0 { }; }; =20 +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + &main0_alert { temperature =3D <95000>; }; --=20 2.34.1