From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E010227EA7; Mon, 8 Sep 2025 14:29:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341745; cv=none; b=I9lScZ+XSer/yhoNrJS8m+59HgrKV+hoWYzM8A/3TfqSMU0rY6IqCidBW7kIgLQ1UWPvTNFskfuXEmJItDqhVSObXUmp4CnQT1oK7gAznyeTJSYDorpblxuefN1k4cwD2/a+o9SnkutJ0pm5hCPaMm4FKOZozl+CnPC4hhM7nEU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341745; c=relaxed/simple; bh=MzRwDHZaIOFpSe8OcyzGvaG/lo4PrLvExvLf6g7BS3A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=a1oH208bR+ldClJFbjPOjN+QWonPgLtGbIyBgraWofCM3Zc+rBhUCO+AJPYgAPEtq7CYxihU54jMRJMtAw2tMlhj+GY+gPUPFXCfKXcheDGnzF+Bp5RDFyFSHbmd6I37EGXStHDlSiOGz7N5uE17uVZ0DivdekmsfVyofp6FVeI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=tEw8xPH2; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="tEw8xPH2" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 588ESuiB071229; Mon, 8 Sep 2025 09:28:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757341736; bh=h9Qoj1O/YYivqHMFvW2L/nQl6AjXQMU33yjrzupImFo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tEw8xPH2o9qVvWESStUpkhgpOWwLzbTOW2E6a48Puo7T/yDu8W7ib2ejU+5434H2z GTyVYM+CH/sT1n+qspjbUaNR8krwbAKoEqR77MHLIu0q+DAP9iRcFUnoszdm2cDNfz bx6hWnck9m53r0uuGEhkyD5DV6cJctKNJW2scSpA= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 588ESuoO3832977 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 09:28:56 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:28:56 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:28:55 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecd1037553; Mon, 8 Sep 2025 09:28:51 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 01/34] arm64: dts: ti: k3-j7200: Enable R5F remote processors at board level Date: Mon, 8 Sep 2025 19:57:53 +0530 Message-ID: <20250908142826.1828676-2-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level J7200 SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis --- v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-2-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B tag. 2. Updated $subject to include R5F remote processors. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-2-b-padhi@ti.com/ v2: Changelog: 1. None Link to v1: https://lore.kernel.org/all/20250814223839.3256046-2-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 9 +++++++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 5ce5f0a3d6f5..628ff89dd72f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -1516,6 +1516,7 @@ main_r5fss0: r5fss@5c00000 { ranges =3D <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains =3D <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss0_core0: r5f@5c00000 { compatible =3D "ti,j7200-r5f"; @@ -1530,6 +1531,7 @@ main_r5fss0_core0: r5f@5c00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss0_core1: r5f@5d00000 { @@ -1545,6 +1547,7 @@ main_r5fss0_core1: r5f@5d00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 56ab144fea07..692c4745040e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -612,6 +612,7 @@ mcu_r5fss0: r5fss@41000000 { ranges =3D <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains =3D <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 mcu_r5fss0_core0: r5f@41000000 { compatible =3D "ti,j7200-r5f"; @@ -626,6 +627,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 mcu_r5fss0_core1: r5f@41400000 { @@ -641,6 +643,7 @@ mcu_r5fss0_core1: r5f@41400000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j7200-som-p0.dtsi index 291ab9bb414d..90befcdc8d08 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -254,20 +254,27 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { }; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &mcu_r5fss0_core1 { mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 /* Timers are used by Remoteproc firmware */ @@ -287,12 +294,14 @@ &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; }; =20 &main_i2c0 { --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE85130C630; 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Mon, 8 Sep 2025 09:29:01 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:29:00 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:29:00 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESece1037553; Mon, 8 Sep 2025 09:28:56 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 02/34] arm64: dts: ti: k3-j721e: Enable remote processors at board level Date: Mon, 8 Sep 2025 19:57:54 +0530 Message-ID: <20250908142826.1828676-3-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level J721E SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis --- v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-3-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B tag. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-3-b-padhi@ti.com/ v2: Changelog: 1. Reordered patch from [PATCH 05/33] to [PATCH v2 02/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-6-b-padhi@ti.com/ .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 6 ++++++ .../arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 12 ++++++++++++ 5 files changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index fb899c99753e..0d1a313a7d10 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -935,37 +935,55 @@ mbox_c71_0: mbox-c71-0 { }; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; =20 &mcu_r5fss0_core1 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; =20 +&main_r5fss0 { + status =3D "okay"; +}; + &main_r5fss0_core0 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; =20 &main_r5fss0_core1 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; =20 +&main_r5fss1 { + status =3D "okay"; +}; + &main_r5fss1_core0 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; =20 &main_r5fss1_core1 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index ab3666ff4297..e748f704e3b6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -2182,6 +2182,7 @@ main_r5fss0: r5fss@5c00000 { ranges =3D <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains =3D <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss0_core0: r5f@5c00000 { compatible =3D "ti,j721e-r5f"; @@ -2196,6 +2197,7 @@ main_r5fss0_core0: r5f@5c00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss0_core1: r5f@5d00000 { @@ -2211,6 +2213,7 @@ main_r5fss0_core1: r5f@5d00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 @@ -2222,6 +2225,7 @@ main_r5fss1: r5fss@5e00000 { ranges =3D <0x5e00000 0x00 0x5e00000 0x20000>, <0x5f00000 0x00 0x5f00000 0x20000>; power-domains =3D <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss1_core0: r5f@5e00000 { compatible =3D "ti,j721e-r5f"; @@ -2236,6 +2240,7 @@ main_r5fss1_core0: r5f@5e00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss1_core1: r5f@5f00000 { @@ -2251,6 +2256,7 @@ main_r5fss1_core1: r5f@5f00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index b02142b2b460..42a21398e389 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -594,6 +594,7 @@ mcu_r5fss0: r5fss@41000000 { ranges =3D <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains =3D <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 mcu_r5fss0_core0: r5f@41000000 { compatible =3D "ti,j721e-r5f"; @@ -608,6 +609,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 mcu_r5fss0_core1: r5f@41400000 { @@ -623,6 +625,7 @@ mcu_r5fss0_core1: r5f@41400000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index ffef3d1cfd55..62b9c13a91e7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -1349,13 +1349,19 @@ mbox_c71_0: mbox-c71-0 { }; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; =20 &mcu_r5fss0_core1 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; @@ -1363,10 +1369,12 @@ &mcu_r5fss0_core1 { =20 &main_r5fss0 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 &main_r5fss1 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 /* Timers are used by Remoteproc firmware */ @@ -1399,24 +1407,28 @@ &main_timer15 { }; =20 &main_r5fss0_core0 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; =20 &main_r5fss0_core1 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; =20 &main_r5fss1_core0 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; =20 &main_r5fss1_core1 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j721e-som-p0.dtsi index 0722f6361cc8..795b041ee733 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -554,23 +554,31 @@ mbox_c71_0: mbox-c71-0 { }; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; =20 &mcu_r5fss0_core1 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; =20 &main_r5fss0 { + status =3D "okay"; ti,cluster-mode =3D <0>; }; =20 &main_r5fss1 { + status =3D "okay"; ti,cluster-mode =3D <0>; }; =20 @@ -604,24 +612,28 @@ &main_timer15 { }; =20 &main_r5fss0_core0 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; =20 &main_r5fss0_core1 { + status =3D "okay"; mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; 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Mon, 8 Sep 2025 09:29:05 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecf1037553; Mon, 8 Sep 2025 09:29:01 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 03/34] arm64: dts: ti: k3-j721s2: Enable remote processors at board level Date: Mon, 8 Sep 2025 19:57:55 +0530 Message-ID: <20250908142826.1828676-4-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level J721S2 SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis --- v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-4-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B tag. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-4-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 08/33] to [PATCH v2 03/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-9-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 12 ++++++++++++ 5 files changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am68-phycore-som.dtsi index fd715fee8170..383594732e81 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi @@ -371,24 +371,28 @@ &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 /* eMMC */ @@ -407,10 +411,12 @@ &main_sdhci1 { =20 &main_r5fss0 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 &main_r5fss1 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 /* Timers are used by Remoteproc firmware */ @@ -438,16 +444,22 @@ &main_timer5 { status =3D "reserved"; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &mcu_r5fss0_core1 { mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + status =3D "okay"; }; =20 &ospi0 { diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/d= ts/ti/k3-am68-sk-som.dtsi index 4ca2d4e2fb9b..2d2edeeb7347 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -291,24 +291,32 @@ mbox_c71_1: mbox-c71-1 { }; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &mcu_r5fss0_core1 { mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 &main_r5fss1 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 /* Timers are used by Remoteproc firmware */ @@ -340,24 +348,28 @@ &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 &c71_0 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 0ad752975acd..80c51b11ac9f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1895,6 +1895,7 @@ main_r5fss0: r5fss@5c00000 { ranges =3D <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains =3D <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss0_core0: r5f@5c00000 { compatible =3D "ti,j721s2-r5f"; @@ -1909,6 +1910,7 @@ main_r5fss0_core0: r5f@5c00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss0_core1: r5f@5d00000 { @@ -1924,6 +1926,7 @@ main_r5fss0_core1: r5f@5d00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 @@ -1935,6 +1938,7 @@ main_r5fss1: r5fss@5e00000 { ranges =3D <0x5e00000 0x00 0x5e00000 0x20000>, <0x5f00000 0x00 0x5f00000 0x20000>; power-domains =3D <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss1_core0: r5f@5e00000 { compatible =3D "ti,j721s2-r5f"; @@ -1949,6 +1953,7 @@ main_r5fss1_core0: r5f@5e00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss1_core1: r5f@5f00000 { @@ -1964,6 +1969,7 @@ main_r5fss1_core1: r5f@5f00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index bc31266126d0..837097751c18 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -690,6 +690,7 @@ mcu_r5fss0: r5fss@41000000 { ranges =3D <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains =3D <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 mcu_r5fss0_core0: r5f@41000000 { compatible =3D "ti,j721s2-r5f"; @@ -704,6 +705,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 mcu_r5fss0_core1: r5f@41400000 { @@ -719,6 +721,7 @@ mcu_r5fss0_core1: r5f@41400000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index a9dbe14fb0c9..f252007262d3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -572,24 +572,32 @@ mbox_c71_1: mbox-c71-1 { }; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &mcu_r5fss0_core1 { mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 &main_r5fss1 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 /* Timers are used by Remoteproc firmware */ @@ -621,24 +629,28 @@ &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; 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Mon, 8 Sep 2025 09:29:10 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecg1037553; Mon, 8 Sep 2025 09:29:05 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 04/34] arm64: dts: ti: k3-j784s4-j742s2: Enable remote processors at board level Date: Mon, 8 Sep 2025 19:57:56 +0530 Message-ID: <20250908142826.1828676-5-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level J784S4-J742S2 common SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis --- v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-5-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B tag. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-5-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 10/33] to [PATCH v2 04/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-11-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am69-sk.dts | 15 +++++++++++++++ .../boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 7 +++++++ .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 9 +++++++++ .../ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi | 3 +++ 4 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index f4f7b89bf0d2..af8eafc3f54a 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -992,24 +992,32 @@ &mcu_cpsw_port1 { bootph-all; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &mcu_r5fss0_core1 { mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 &main_r5fss1 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 /* Timers are used by Remoteproc firmware */ @@ -1055,42 +1063,49 @@ &main_timer9 { =20 &main_r5fss2 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 &main_r5fss2_core0 { mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; memory-region =3D <&main_r5fss2_core0_dma_memory_region>, <&main_r5fss2_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss2_core1 { mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; memory-region =3D <&main_r5fss2_core1_dma_memory_region>, <&main_r5fss2_core1_memory_region>; + status =3D "okay"; }; =20 &c71_0 { diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index 6afa802544e9..c269e5b29b96 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -1154,6 +1154,10 @@ mbox_c71_2: mbox-c71-2 { }; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { status =3D "okay"; mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; @@ -1170,14 +1174,17 @@ &mcu_r5fss0_core1 { =20 &main_r5fss0 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 &main_r5fss1 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 &main_r5fss2 { ti,cluster-mode =3D <0>; + status =3D "okay"; }; =20 /* Timers are used by Remoteproc firmware */ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arc= h/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index fbbe768e7a30..9cc0901d58fb 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -2174,6 +2174,7 @@ main_r5fss0: r5fss@5c00000 { ranges =3D <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains =3D <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss0_core0: r5f@5c00000 { compatible =3D "ti,j721s2-r5f"; @@ -2188,6 +2189,7 @@ main_r5fss0_core0: r5f@5c00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss0_core1: r5f@5d00000 { @@ -2203,6 +2205,7 @@ main_r5fss0_core1: r5f@5d00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 @@ -2214,6 +2217,7 @@ main_r5fss1: r5fss@5e00000 { ranges =3D <0x5e00000 0x00 0x5e00000 0x20000>, <0x5f00000 0x00 0x5f00000 0x20000>; power-domains =3D <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss1_core0: r5f@5e00000 { compatible =3D "ti,j721s2-r5f"; @@ -2228,6 +2232,7 @@ main_r5fss1_core0: r5f@5e00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss1_core1: r5f@5f00000 { @@ -2243,6 +2248,7 @@ main_r5fss1_core1: r5f@5f00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 @@ -2254,6 +2260,7 @@ main_r5fss2: r5fss@5900000 { ranges =3D <0x5900000 0x00 0x5900000 0x20000>, <0x5a00000 0x00 0x5a00000 0x20000>; power-domains =3D <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss2_core0: r5f@5900000 { compatible =3D "ti,j721s2-r5f"; @@ -2268,6 +2275,7 @@ main_r5fss2_core0: r5f@5900000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss2_core1: r5f@5a00000 { @@ -2283,6 +2291,7 @@ main_r5fss2_core1: r5f@5a00000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi= b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index 52e2965a3bf5..cc22bfb5f599 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -595,6 +595,7 @@ mcu_r5fss0: r5fss@41000000 { ranges =3D <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains =3D <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 mcu_r5fss0_core0: r5f@41000000 { compatible =3D "ti,j721s2-r5f"; @@ -609,6 +610,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; 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Mon, 8 Sep 2025 09:29:14 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESech1037553; Mon, 8 Sep 2025 09:29:10 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 05/34] arm64: dts: ti: k3-am62p-j722s: Enable remote processors at board level Date: Mon, 8 Sep 2025 19:57:57 +0530 Message-ID: <20250908142826.1828676-6-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level AM62P-J722S common SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Tested-by: Judith Mendez Reviewed-by: Dhruva Gole --- v4: Changelog: 1. Carried R/B tag Link to v3: https://lore.kernel.org/all/20250905051846.1189612-6-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B and T/B tags. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-6-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 13/33] to [PATCH v2 05/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-14-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts | 3 +++ arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 3 +++ arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 1 + 6 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/a= rm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index bd6a00d13aea..5288c959f3c1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -205,6 +205,7 @@ mcu_r5fss0_core0: r5f@79000000 { ti,atcm-enable =3D <0>; ti,btcm-enable =3D <1>; ti,loczrama =3D <0>; + status =3D "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arc= h/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index 6757b37a9de3..8612b45e665c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -136,6 +136,7 @@ wkup_r5fss0_core0: r5f@78000000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index 899da7896563..2755598fd1f5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -725,6 +725,7 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &mcu_r5fss0 { @@ -735,6 +736,7 @@ &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_uart0 { diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/bo= ot/dts/ti/k3-am67a-beagley-ai.dts index bf9b23df1da2..b329e4cb0c37 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts @@ -515,6 +515,7 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_wkup_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &mcu_r5fss0 { @@ -525,6 +526,7 @@ &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0 { @@ -535,6 +537,7 @@ &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster3 &mbox_main_r5_0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &c7x_0 { diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index 9d8abfa9afd2..2b9e007432a9 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -850,6 +850,7 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_wkup_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &mcu_r5fss0 { @@ -860,6 +861,7 @@ &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0 { @@ -870,6 +872,7 @@ &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster3 &mbox_main_r5_0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &c7x_0 { diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index 993828872dfb..d57fdd38bdce 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -368,6 +368,7 @@ main_r5fss0_core0: r5f@78400000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13E3A30C62A; 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charset="utf-8" Remote Processors defined in top-level AM62x SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Reviewed-by: Wadim Egorov Tested-by: Wadim Egorov Acked-by: Andrew Davis Reviewed-by: Dhruva Gole --- v4: Changelog: 1. Carried R/B tag. Link to v3: https://lore.kernel.org/all/20250905051846.1189612-7-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B, T/B, R/B tags. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-7-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 21/33] to [PATCH v2 06/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-22-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am62-phycore-som.dtsi index 10e6b5c08619..dcd22ff487ec 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -407,4 +407,5 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-wakeup.dtsi index 6549b7efa656..75aed3a88284 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -128,6 +128,7 @@ wkup_r5fss0_core0: r5f@78000000 { ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <121>; ti,sci-proc-ids =3D <0x01 0xff>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 13e1d36123d5..840772060cb1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -506,6 +506,7 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &usbss0 { --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D0D430CDA0; Mon, 8 Sep 2025 14:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; 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Mon, 8 Sep 2025 09:29:24 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:29:24 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecj1037553; Mon, 8 Sep 2025 09:29:20 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 07/34] arm64: dts: ti: k3-am62a: Enable remote processors at board level Date: Mon, 8 Sep 2025 19:57:59 +0530 Message-ID: <20250908142826.1828676-8-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level AM62A SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Tested-by: Judith Mendez --- v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-8-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B, T/B tags. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-8-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 24/33] to [PATCH v2 07/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-25-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 1 + 5 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts= /ti/k3-am62a-mcu.dtsi index ee961ced7208..d22caa7c346b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -197,6 +197,7 @@ mcu_r5fss0_core0: r5f@79000000 { ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <9>; ti,sci-proc-ids =3D <0x03 0xff>; + status =3D "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/= boot/dts/ti/k3-am62a-phycore-som.dtsi index 207ca00630d1..403adfbf7dce 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -406,6 +406,7 @@ &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_mcu_r5_0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &ospi0 { @@ -444,4 +445,5 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62a-wakeup.dtsi index 9ef1c829a9df..23877dadc98d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -127,6 +127,7 @@ wkup_r5fss0_core0: r5f@78000000 { ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <121>; ti,sci-proc-ids =3D <0x01 0xff>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index bceead5e288e..03291862f07a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -870,6 +870,7 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0>, <&mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &mcu_r5fss0 { @@ -880,6 +881,7 @@ &mcu_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &c7x_0 { diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62d2-evm.dts index daea18b0bc61..d45fc42b03f3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -586,6 +586,7 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; bootph-pre-ram; }; =20 --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92B5430CDA0; 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Mon, 8 Sep 2025 09:29:30 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:29:29 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:29:29 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESeck1037553; Mon, 8 Sep 2025 09:29:25 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Wadim Egorov Subject: [PATCH v4 08/34] arm64: dts: ti: k3-am64: Enable remote processors at board level Date: Mon, 8 Sep 2025 19:58:00 +0530 Message-ID: <20250908142826.1828676-9-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level AM64x SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Reviewed-by: Wadim Egorov Tested-by: Wadim Egorov # phycore-am64x Acked-by: Andrew Davis Tested-by: Hari Nagalla --- v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-9-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B, R/B, T/B tags. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-9-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 26/33] to [PATCH v2 08/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-27-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 12 ++++++++++++ 6 files changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index c7e5da37486a..d872cc671094 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -921,6 +921,7 @@ main_r5fss0: r5fss@78000000 { <0x78200000 0x00 0x78200000 0x08000>, <0x78300000 0x00 0x78300000 0x08000>; power-domains =3D <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss0_core0: r5f@78000000 { compatible =3D "ti,am64-r5f"; @@ -935,6 +936,7 @@ main_r5fss0_core0: r5f@78000000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss0_core1: r5f@78200000 { @@ -950,6 +952,7 @@ main_r5fss0_core1: r5f@78200000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 @@ -963,6 +966,7 @@ main_r5fss1: r5fss@78400000 { <0x78600000 0x00 0x78600000 0x08000>, <0x78700000 0x00 0x78700000 0x08000>; power-domains =3D <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 main_r5fss1_core0: r5f@78400000 { compatible =3D "ti,am64-r5f"; @@ -977,6 +981,7 @@ main_r5fss1_core0: r5f@78400000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 main_r5fss1_core1: r5f@78600000 { @@ -992,6 +997,7 @@ main_r5fss1_core1: r5f@78600000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am64-phycore-som.dtsi index d9d491b12c33..03c46d74ebb5 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -349,28 +349,40 @@ &main_pktdma { bootph-all; }; =20 +&main_r5fss0 { + status =3D "okay"; +}; + &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 &mcu_m4fss { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index e01866372293..a07503b192c9 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -764,28 +764,40 @@ mbox_m4_0: mbox-m4-0 { }; }; =20 +&main_r5fss0 { + status =3D "okay"; +}; + &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 &mcu_m4fss { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 1deaa0be0085..ae4a6552644c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -679,28 +679,40 @@ mbox_m4_0: mbox-m4-0 { }; }; =20 +&main_r5fss0 { + status =3D "okay"; +}; + &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 &mcu_m4fss { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/= dts/ti/k3-am642-sr-som.dtsi index a5cec9a07510..d0c1e4dc1da7 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -488,28 +488,40 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.US= B0_DRVVBUS */ }; }; =20 +&main_r5fss0 { + status =3D "okay"; +}; + &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 /* SoC default UART console */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am642-tqma64xxl.dtsi index 828d815d6bdf..876cbb21961d 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -167,28 +167,40 @@ mbox_m4_0: mbox-m4-0 { }; }; =20 +&main_r5fss0 { + status =3D "okay"; +}; + &main_r5fss0_core0 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region =3D <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss0_core1 { mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region =3D <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + status =3D "okay"; }; =20 &main_r5fss1_core0 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region =3D <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status =3D "okay"; }; =20 &main_r5fss1_core1 { mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region =3D <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status =3D "okay"; }; =20 &ospi0 { --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E50E330AD1A; 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Mon, 8 Sep 2025 09:29:34 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:29:34 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:29:34 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecl1037553; Mon, 8 Sep 2025 09:29:30 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 09/34] arm64: dts: ti: k3-am65: Enable remote processors at board level Date: Mon, 8 Sep 2025 19:58:01 +0530 Message-ID: <20250908142826.1828676-10-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level AM65x SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis --- v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-10-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B tag. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-10-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 31/33] to [PATCH v2 09/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-32-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 6 ++++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index e5136ed94765..73936994a156 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -602,16 +602,22 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { }; }; =20 +&mcu_r5fss0 { + status =3D "okay"; +}; + &mcu_r5fss0_core0 { memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + status =3D "okay"; }; =20 &mcu_r5fss0_core1 { memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + status =3D "okay"; }; =20 &mcu_rti1 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am65-mcu.dtsi index 7cf1f646500a..f6d9a5779918 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -408,6 +408,7 @@ mcu_r5fss0: r5fss@41000000 { ranges =3D <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains =3D <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; =20 mcu_r5fss0_core0: r5f@41000000 { compatible =3D "ti,am654-r5f"; @@ -422,6 +423,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; =20 mcu_r5fss0_core1: r5f@41400000 { @@ -437,6 +439,7 @@ mcu_r5fss0_core1: r5f@41400000 { ti,atcm-enable =3D <1>; ti,btcm-enable =3D <1>; ti,loczrama =3D <1>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index e589690c7c82..39c2d46801de 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -541,16 +541,22 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { }; 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Mon, 8 Sep 2025 09:29:39 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecm1037553; Mon, 8 Sep 2025 09:29:34 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 10/34] arm64: dts: ti: k3-am62: Enable Mailbox nodes at the board level Date: Mon, 8 Sep 2025 19:58:02 +0530 Message-ID: <20250908142826.1828676-11-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Mailbox nodes defined in the top-level AM62x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Reviewed-by: Dhruva Gole --- v4: Changelog: 1. Carried R/B tag. Link to v3: https://lore.kernel.org/all/20250905051846.1189612-11-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B tag. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-11-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 20/33] to [PATCH v2 10/33]. 2. Added new-line before sub-nodes in mailboxes. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-21-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 2 ++ 3 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 029380dc1a35..40fb3c9e674c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -808,6 +808,7 @@ mailbox0_cluster0: mailbox@29000000 { #mbox-cells =3D <1>; ti,mbox-num-users =3D <4>; ti,mbox-num-fifos =3D <16>; + status =3D "disabled"; }; =20 ecap0: pwm@23100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/= boot/dts/ti/k3-am62-pocketbeagle2.dts index 2e4cf65ee323..2eee5f638e0f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -293,6 +293,8 @@ &epwm2 { }; =20 &mailbox0_cluster0 { + status =3D "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx =3D <0 0 0>; ti,mbox-tx =3D <1 0 0>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-verdin.dtsi index bc2289d74774..bbf2d630b305 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -1317,6 +1317,8 @@ &main_i2c3 { }; =20 &mailbox0_cluster0 { + status =3D "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx =3D <0 0 0>; ti,mbox-tx =3D <1 0 0>; --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA46A30FC1D; Mon, 8 Sep 2025 14:29:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341790; cv=none; b=FytoYG55sCjBOVuhmdBvq3s2iYGFiJrd2ZmSnu0T4s8k8+aqtQbNGyP9evUNfE+uKg6vLCVp3GzXOOn34yiF+UGDcPEpNh12/rd0AachIXCuHe7HU/cPJ1UnSLMInd/3vOCL8jntTcsRVJqUsM3bKeyi594PYDsmTJu5gWHunv4= ARC-Message-Signature: i=1; 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Mon, 8 Sep 2025 09:29:43 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecn1037553; Mon, 8 Sep 2025 09:29:39 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 11/34] arm64: dts: ti: k3-am62a: Enable Mailbox nodes at the board level Date: Mon, 8 Sep 2025 19:58:03 +0530 Message-ID: <20250908142826.1828676-12-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Mailbox nodes defined in the top-level AM62A SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Tested-by: Judith Mendez --- v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-12-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B, T/B tag. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-12-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 23/33] to [PATCH v2 11/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-24-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index 9cad79d7bbc1..d5f018768981 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -804,6 +804,7 @@ mailbox0_cluster0: mailbox@29000000 { #mbox-cells =3D <1>; ti,mbox-num-users =3D <4>; ti,mbox-num-fifos =3D <16>; + status =3D "disabled"; }; =20 mailbox0_cluster1: mailbox@29010000 { @@ -813,6 +814,7 @@ mailbox0_cluster1: mailbox@29010000 { #mbox-cells =3D <1>; ti,mbox-num-users =3D <4>; ti,mbox-num-fifos =3D <16>; + status =3D "disabled"; }; =20 mailbox0_cluster2: mailbox@29020000 { @@ -822,6 +824,7 @@ mailbox0_cluster2: mailbox@29020000 { #mbox-cells =3D <1>; ti,mbox-num-users =3D <4>; ti,mbox-num-fifos =3D <16>; + status =3D "disabled"; }; =20 mailbox0_cluster3: mailbox@29030000 { @@ -831,6 +834,7 @@ mailbox0_cluster3: mailbox@29030000 { #mbox-cells =3D <1>; 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Mon, 8 Sep 2025 09:29:44 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 12/34] arm64: dts: ti: k3-am6*-boards: Add label to reserved-memory node Date: Mon, 8 Sep 2025 19:58:04 +0530 Message-ID: <20250908142826.1828676-13-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add the label name 'reserved_memory' to the reserved-memory node in all K3 AM6* board level dts files. This is done so that the node can be referenced and extended to add more carveout entries as needed in future refactoring patches. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis --- v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-13-b-padhi@ti.com/ v3: Changelog: 1. Carried A/B tag. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-13-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 15/33] to [PATCH v2 12/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-16-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 +- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 2 +- arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 +- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 2 +- arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 2 +- 13 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-verdin.dtsi index bbf2d630b305..cbbcb96e2e24 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -189,7 +189,7 @@ reg_usb0_vbus: regulator-usb0-vbus { regulator-name =3D "USB_1_EN"; }; =20 - reserved-memory { + reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/= boot/dts/ti/k3-am62a-phycore-som.dtsi index 403adfbf7dce..3108e9b0c804 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -45,7 +45,7 @@ memory@80000000 { bootph-all; }; =20 - reserved-memory { + reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index 03291862f07a..7ebcfe8edfe1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -39,7 +39,7 @@ memory@80000000 { bootph-all; }; =20 - reserved-memory { + reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62d2-evm.dts index d45fc42b03f3..41860ac42f3c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -39,7 +39,7 @@ memory@80000000 { bootph-all; }; =20 - reserved-memory { + reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/= dts/ti/k3-am62p-verdin.dtsi index a2fdc6741da2..6a04b370d149 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -147,7 +147,7 @@ reg_vsodimm: regulator-vsodimm { regulator-name =3D "+V_SODIMM"; }; =20 - reserved-memory { + reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index 2755598fd1f5..c5b5b00c42b9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -44,7 +44,7 @@ memory@80000000 { bootph-pre-ram; }; =20 - reserved-memory { + reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 840772060cb1..03b8e246d8c2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -36,7 +36,7 @@ memory@80000000 { reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>; }; =20 - reserved-memory { + reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index a07503b192c9..7640c5efe9b8 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -42,7 +42,7 @@ memory@80000000 { reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>; }; =20 - reserved-memory { + reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index ae4a6552644c..fb8bd66f2f94 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -40,7 +40,7 @@ memory@80000000 { reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>; }; =20 - reserved-memory { + reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/= dts/ti/k3-am642-sr-som.dtsi index d0c1e4dc1da7..81adae0a8e55 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -105,7 +105,7 @@ memory@80000000 { device_type =3D "memory"; }; =20 - reserved-memory { + reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am642-tqma64xxl.dtsi index 876cbb21961d..40b619c9a6c9 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -20,7 +20,7 @@ memory@80000000 { =20 }; =20 - reserved-memory { + reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index 73936994a156..6cd499ea53e7 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -36,7 +36,7 @@ chosen { stdout-path =3D "serial3:115200n8"; }; =20 - reserved-memory { + reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index 39c2d46801de..e532ea0a22b2 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -39,7 +39,7 @@ memory@80000000 { <0x00000008 0x80000000 0x00000000 0x80000000>; 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Mon, 8 Sep 2025 09:29:58 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecp1037553; Mon, 8 Sep 2025 09:29:49 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Francesco Dolcini , Robert Nelson , Jo_o Paulo Gon_alves , Parth Pancholi , Emanuele Ghidoli , Matthias Schiffer , Logan Bristol , Josua Mayer , John Ma , Nathan Morrisson , Garrett Giordano , Matt McKee , Wadim Egorov , Andrejs Cainikovs , "Max Krummenacher" , Stefan Eichenberger , Hiago De Franco , Diogo Ivo , Li Hua Qian , Jan Kiszka , Baocheng Su , Benedikt Niedermayr Subject: [PATCH v4 13/34] arm64: dts: ti: k3: Rename rproc reserved-mem nodes to 'memory@addr' Date: Mon, 8 Sep 2025 19:58:05 +0530 Message-ID: <20250908142826.1828676-14-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Currently, the reserved memory carveouts used by remote processors are named like 'rproc-name--memory-region@addr'. While it is descriptive, the node label already serves that purpose. Rename reserved memory nodes to generic 'memory@addr' to align with the device tree specifications. This is done for all TI K3 based boards. Signed-off-by: Beleswar Padhi Reviewed-by: Francesco Dolcini --- Cc: Francesco Dolcini Cc: Robert Nelson Cc: Jo_o Paulo Gon_alves Cc: Parth Pancholi Cc: Emanuele Ghidoli Cc: Francesco Dolcini Cc: Matthias Schiffer Cc: Logan Bristol Cc: Josua Mayer Cc: John Ma Cc: Nathan Morrisson Cc: Garrett Giordano Cc: Matt McKee Cc: Wadim Egorov Cc: Andrejs Cainikovs Cc: Max Krummenacher Cc: Stefan Eichenberger Cc: Hiago De Franco Cc: Diogo Ivo Cc: Li Hua Qian Cc: Jan Kiszka Cc: Baocheng Su Cc: Benedikt Niedermayr v4: Changelog: 1. New patch .../boot/dts/ti/k3-am62-phycore-som.dtsi | 10 ++-- .../boot/dts/ti/k3-am62-pocketbeagle2.dts | 6 +-- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 2 +- .../arm64/boot/dts/ti/k3-am625-beagleplay.dts | 2 +- .../boot/dts/ti/k3-am62a-phycore-som.dtsi | 12 ++--- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 12 ++--- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 14 +++--- arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 8 ++-- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 8 ++-- .../boot/dts/ti/k3-am64-phycore-som.dtsi | 22 ++++----- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 22 ++++----- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 22 ++++----- arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 16 +++---- .../arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 18 +++---- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 10 ++-- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 10 ++-- .../arm64/boot/dts/ti/k3-am67a-beagley-ai.dts | 22 ++++----- .../boot/dts/ti/k3-am68-phycore-som.dtsi | 34 ++++++------- arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 34 ++++++------- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 48 +++++++++---------- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 18 +++---- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 38 +++++++-------- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 38 +++++++-------- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 38 +++++++-------- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 34 ++++++------- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 22 ++++----- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 4 +- .../dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 44 ++++++++--------- 29 files changed, 285 insertions(+), 285 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am62-phycore-som.dtsi index dcd22ff487ec..75b7e64f6659 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -46,31 +46,31 @@ ramoops@9c700000 { pmsg-size =3D <0x8000>; }; =20 - rtos_ipc_memory_region: ipc-memories@9c800000 { + rtos_ipc_memory_region: memory@9c800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c800000 0x00 0x00300000>; no-map; }; =20 - mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + mcu_m4fss_dma_memory_region: memory@9cb00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9cb00000 0x00 0x100000>; no-map; }; =20 - mcu_m4fss_memory_region: m4f-memory@9cc00000 { + mcu_m4fss_memory_region: memory@9cc00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9cc00000 0x00 0xe00000>; no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9da00000 0x00 0x100000>; no-map; }; =20 - wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + wkup_r5fss0_core0_memory_region: memory@9db00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9db00000 0x00 0xc00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/= boot/dts/ti/k3-am62-pocketbeagle2.dts index 2eee5f638e0f..2d46be298b0b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -54,13 +54,13 @@ linux,cma { linux,cma-default; }; =20 - mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + mcu_m4fss_dma_memory_region: memory@9cb00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9cb00000 0x00 0x100000>; no-map; }; =20 - mcu_m4fss_memory_region: m4f-memory@9cc00000 { + mcu_m4fss_memory_region: memory@9cc00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9cc00000 0x00 0xe00000>; no-map; @@ -78,7 +78,7 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9db00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9db00000 0x00 0xc00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-verdin.dtsi index cbbcb96e2e24..9384c9a0232a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -206,7 +206,7 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9db00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9db00000 0x00 0xc00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/bo= ot/dts/ti/k3-am625-beagleplay.dts index 72b09f9c69d8..7028d9835c4a 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -83,7 +83,7 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9db00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9db00000 0x00 0xc00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/= boot/dts/ti/k3-am62a-phycore-som.dtsi index 3108e9b0c804..0406a43ff704 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -59,37 +59,37 @@ linux,cma { linux,cma-default; }; =20 - c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + c7x_0_dma_memory_region: memory@99800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x99800000 0x00 0x100000>; no-map; }; =20 - c7x_0_memory_region: c7x-memory@99900000 { + c7x_0_memory_region: memory@99900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x99900000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9b800000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + mcu_r5fss0_core0_memory_region: memory@9b900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9b900000 0x00 0xf00000>; no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c800000 0x00 0x100000>; no-map; }; =20 - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c900000 0x00 0xf00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index 7ebcfe8edfe1..312bdab28784 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -53,37 +53,37 @@ linux,cma { linux,cma-default; }; =20 - c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + c7x_0_dma_memory_region: memory@99800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x99800000 0x00 0x100000>; no-map; }; =20 - c7x_0_memory_region: c7x-memory@99900000 { + c7x_0_memory_region: memory@99900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x99900000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9b800000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + mcu_r5fss0_core0_memory_region: memory@9b900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9b900000 0x00 0xf00000>; no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c800000 0x00 0x100000>; no-map; }; =20 - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c900000 0x00 0xf00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62d2-evm.dts index 41860ac42f3c..289f52b3481f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -58,37 +58,37 @@ secure_tfa_ddr: tfa@80000000 { no-map; }; =20 - c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + c7x_0_dma_memory_region: memory@99800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x99800000 0x00 0x100000>; no-map; }; =20 - c7x_0_memory_region: c7x-memory@99900000 { + c7x_0_memory_region: memory@99900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x99900000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9b800000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + mcu_r5fss0_core0_memory_region: memory@9b900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9b900000 0x00 0xf00000>; no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c800000 0x00 0x100000>; no-map; }; =20 - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c900000 0x00 0xf00000>; no-map; @@ -100,7 +100,7 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a0000000 { + rtos_ipc_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x01000000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/= dts/ti/k3-am62p-verdin.dtsi index 6a04b370d149..522d6f029c36 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -162,7 +162,7 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c900000 0x00 0x01e00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index c5b5b00c42b9..aa363aaf6d59 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -49,25 +49,25 @@ reserved_memory: reserved-memory { #size-cells =3D <2>; ranges; =20 - mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000= { + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9b800000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + mcu_r5fss0_core0_memory_region: memory@9b900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9b900000 0x00 0xf00000>; no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c800000 0x00 0x100000>; no-map; }; =20 - wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c900000 0x00 0xf00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 03b8e246d8c2..05cba3cfc79e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -58,25 +58,25 @@ linux,cma { linux,cma-default; }; =20 - mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + mcu_m4fss_dma_memory_region: memory@9cb00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9cb00000 0x00 0x100000>; no-map; }; =20 - mcu_m4fss_memory_region: m4f-memory@9cc00000 { + mcu_m4fss_memory_region: memory@9cc00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9cc00000 0x00 0xe00000>; no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9da00000 0x00 0x100000>; no-map; }; =20 - wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + wkup_r5fss0_core0_memory_region: memory@9db00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9db00000 0x00 0xc00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am64-phycore-som.dtsi index 03c46d74ebb5..ba425b125d63 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -41,67 +41,67 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + main_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss1_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + main_r5fss1_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss1_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + main_r5fss1_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + mcu_m4fss_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - mcu_m4fss_memory_region: m4f-memory@a4100000 { + mcu_m4fss_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a5000000 { + rtos_ipc_memory_region: memory@a5000000 { reg =3D <0x00 0xa5000000 0x00 0x00800000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index 7640c5efe9b8..ebc9fedc4d72 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -53,67 +53,67 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + main_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss1_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + main_r5fss1_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss1_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + main_r5fss1_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + mcu_m4fss_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - mcu_m4fss_memory_region: m4f-memory@a4100000 { + mcu_m4fss_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a5000000 { + rtos_ipc_memory_region: memory@a5000000 { reg =3D <0x00 0xa5000000 0x00 0x00800000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index fb8bd66f2f94..d2b06e508c7f 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -51,67 +51,67 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + main_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss1_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + main_r5fss1_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss1_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + main_r5fss1_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + mcu_m4fss_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - mcu_m4fss_memory_region: m4f-memory@a4100000 { + mcu_m4fss_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a5000000 { + rtos_ipc_memory_region: memory@a5000000 { reg =3D <0x00 0xa5000000 0x00 0x00800000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/= dts/ti/k3-am642-sr-som.dtsi index 81adae0a8e55..35294a5c46d5 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -115,49 +115,49 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + main_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss1_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + main_r5fss1_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss1_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + main_r5fss1_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am642-tqma64xxl.dtsi index 40b619c9a6c9..4068d2c2b10c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -31,55 +31,55 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + main_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss1_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + main_r5fss1_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss1_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + main_r5fss1_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a5000000 { + rtos_ipc_memory_region: memory@a5000000 { reg =3D <0x00 0xa5000000 0x00 0x00800000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index 6cd499ea53e7..df2eed0b4048 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -47,31 +47,31 @@ secure_ddr: secure-ddr@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0 0xa0000000 0 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0 0xa0100000 0 0xf00000>; no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0 0xa1000000 0 0x100000>; no-map; }; =20 - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0 0xa1100000 0 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a2000000 { + rtos_ipc_memory_region: memory@a2000000 { reg =3D <0x00 0xa2000000 0x00 0x00200000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index e532ea0a22b2..3ca771a4f9c7 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -50,31 +50,31 @@ secure_ddr: secure-ddr@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0 0xa0000000 0 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0 0xa0100000 0 0xf00000>; no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0 0xa1000000 0 0x100000>; no-map; }; =20 - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0 0xa1100000 0 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a2000000 { + rtos_ipc_memory_region: memory@a2000000 { reg =3D <0x00 0xa2000000 0x00 0x00100000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/bo= ot/dts/ti/k3-am67a-beagley-ai.dts index b329e4cb0c37..85436ea5b4e7 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts @@ -50,67 +50,67 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + wkup_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + wkup_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000= { + mcu_r5fss0_core0_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { + mcu_r5fss0_core0_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a20000= 00 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { + c7x_0_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - c7x_0_memory_region: c7x-memory@a3100000 { + c7x_0_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { + c7x_1_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - c7x_1_memory_region: c7x-memory@a4100000 { + c7x_1_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a5000000 { + rtos_ipc_memory_region: memory@a5000000 { reg =3D <0x00 0xa5000000 0x00 0x1c00000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am68-phycore-som.dtsi index 383594732e81..b9c60e078d21 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi @@ -49,103 +49,103 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5100000 0x00 0xf00000>; no-map; }; =20 - c71_0_dma_memory_region: c71-dma-memory@a6000000 { + c71_0_dma_memory_region: memory@a6000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6000000 0x00 0x100000>; no-map; }; =20 - c71_0_memory_region: c71-memory@a6100000 { + c71_0_memory_region: memory@a6100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6100000 0x00 0xf00000>; no-map; }; =20 - c71_1_dma_memory_region: c71-dma-memory@a7000000 { + c71_1_dma_memory_region: memory@a7000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7000000 0x00 0x100000>; no-map; }; =20 - c71_1_memory_region: c71-memory@a7100000 { + c71_1_memory_region: memory@a7100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a8000000 { + rtos_ipc_memory_region: memory@a8000000 { reg =3D <0x00 0xa8000000 0x00 0x01c00000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/d= ts/ti/k3-am68-sk-som.dtsi index 2d2edeeb7347..c423b1443e0c 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -27,103 +27,103 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5100000 0x00 0xf00000>; no-map; }; =20 - c71_0_dma_memory_region: c71-dma-memory@a6000000 { + c71_0_dma_memory_region: memory@a6000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6000000 0x00 0x100000>; no-map; }; =20 - c71_0_memory_region: c71-memory@a6100000 { + c71_0_memory_region: memory@a6100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6100000 0x00 0xf00000>; no-map; }; =20 - c71_1_dma_memory_region: c71-dma-memory@a7000000 { + c71_1_dma_memory_region: memory@a7000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7000000 0x00 0x100000>; no-map; }; =20 - c71_1_memory_region: c71-memory@a7100000 { + c71_1_memory_region: memory@a7100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a8000000 { + rtos_ipc_memory_region: memory@a8000000 { reg =3D <0x00 0xa8000000 0x00 0x01c00000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index af8eafc3f54a..60817c1f3104 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -49,145 +49,145 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + main_r5fss2_core0_dma_memory_region: memory@a6000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6000000 0x00 0x100000>; no-map; }; =20 - main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + main_r5fss2_core0_memory_region: memory@a6100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + main_r5fss2_core1_dma_memory_region: memory@a7000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7000000 0x00 0x100000>; no-map; }; =20 - main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + main_r5fss2_core1_memory_region: memory@a7100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7100000 0x00 0xf00000>; no-map; }; =20 - c71_0_dma_memory_region: c71-dma-memory@a8000000 { + c71_0_dma_memory_region: memory@a8000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa8000000 0x00 0x100000>; no-map; }; =20 - c71_0_memory_region: c71-memory@a8100000 { + c71_0_memory_region: memory@a8100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa8100000 0x00 0xf00000>; no-map; }; =20 - c71_1_dma_memory_region: c71-dma-memory@a9000000 { + c71_1_dma_memory_region: memory@a9000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa9000000 0x00 0x100000>; no-map; }; =20 - c71_1_memory_region: c71-memory@a9100000 { + c71_1_memory_region: memory@a9100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa9100000 0x00 0xf00000>; no-map; }; =20 - c71_2_dma_memory_region: c71-dma-memory@aa000000 { + c71_2_dma_memory_region: memory@aa000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xaa000000 0x00 0x100000>; no-map; }; =20 - c71_2_memory_region: c71-memory@aa100000 { + c71_2_memory_region: memory@aa100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xaa100000 0x00 0xf00000>; no-map; }; =20 - c71_3_dma_memory_region: c71-dma-memory@ab000000 { + c71_3_dma_memory_region: memory@ab000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xab000000 0x00 0x100000>; no-map; }; =20 - c71_3_memory_region: c71-memory@ab100000 { + c71_3_memory_region: memory@ab100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xab100000 0x00 0xf00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j7200-som-p0.dtsi index 90befcdc8d08..c689e417cf45 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -29,55 +29,55 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a4000000 { + rtos_ipc_memory_region: memory@a4000000 { reg =3D <0x00 0xa4000000 0x00 0x00800000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 0d1a313a7d10..ac4d90e82aab 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -51,115 +51,115 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5100000 0x00 0xf00000>; no-map; }; =20 - c66_0_dma_memory_region: c66-dma-memory@a6000000 { + c66_0_dma_memory_region: memory@a6000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6000000 0x00 0x100000>; no-map; }; =20 - c66_0_memory_region: c66-memory@a6100000 { + c66_0_memory_region: memory@a6100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6100000 0x00 0xf00000>; no-map; }; =20 - c66_1_dma_memory_region: c66-dma-memory@a7000000 { + c66_1_dma_memory_region: memory@a7000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7000000 0x00 0x100000>; no-map; }; =20 - c66_1_memory_region: c66-memory@a7100000 { + c66_1_memory_region: memory@a7100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7100000 0x00 0xf00000>; no-map; }; =20 - c71_0_dma_memory_region: c71-dma-memory@a8000000 { + c71_0_dma_memory_region: memory@a8000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa8000000 0x00 0x100000>; no-map; }; =20 - c71_0_memory_region: c71-memory@a8100000 { + c71_0_memory_region: memory@a8100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa8100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@aa000000 { + rtos_ipc_memory_region: memory@aa000000 { reg =3D <0x00 0xaa000000 0x00 0x01c00000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 62b9c13a91e7..0f05e65f7bf7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -48,115 +48,115 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5100000 0x00 0xf00000>; no-map; }; =20 - c66_0_dma_memory_region: c66-dma-memory@a6000000 { + c66_0_dma_memory_region: memory@a6000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6000000 0x00 0x100000>; no-map; }; =20 - c66_0_memory_region: c66-memory@a6100000 { + c66_0_memory_region: memory@a6100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6100000 0x00 0xf00000>; no-map; }; =20 - c66_1_dma_memory_region: c66-dma-memory@a7000000 { + c66_1_dma_memory_region: memory@a7000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7000000 0x00 0x100000>; no-map; }; =20 - c66_1_memory_region: c66-memory@a7100000 { + c66_1_memory_region: memory@a7100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7100000 0x00 0xf00000>; no-map; }; =20 - c71_0_dma_memory_region: c71-dma-memory@a8000000 { + c71_0_dma_memory_region: memory@a8000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa8000000 0x00 0x100000>; no-map; }; =20 - c71_0_memory_region: c71-memory@a8100000 { + c71_0_memory_region: memory@a8100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa8100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@aa000000 { + rtos_ipc_memory_region: memory@aa000000 { reg =3D <0x00 0xaa000000 0x00 0x01c00000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j721e-som-p0.dtsi index 795b041ee733..06388f28d122 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -29,115 +29,115 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5100000 0x00 0xf00000>; no-map; }; =20 - c66_1_dma_memory_region: c66-dma-memory@a6000000 { + c66_1_dma_memory_region: memory@a6000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6000000 0x00 0x100000>; no-map; }; =20 - c66_0_memory_region: c66-memory@a6100000 { + c66_0_memory_region: memory@a6100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6100000 0x00 0xf00000>; no-map; }; =20 - c66_0_dma_memory_region: c66-dma-memory@a7000000 { + c66_0_dma_memory_region: memory@a7000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7000000 0x00 0x100000>; no-map; }; =20 - c66_1_memory_region: c66-memory@a7100000 { + c66_1_memory_region: memory@a7100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7100000 0x00 0xf00000>; no-map; }; =20 - c71_0_dma_memory_region: c71-dma-memory@a8000000 { + c71_0_dma_memory_region: memory@a8000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa8000000 0x00 0x100000>; no-map; }; =20 - c71_0_memory_region: c71-memory@a8100000 { + c71_0_memory_region: memory@a8100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa8100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@aa000000 { + rtos_ipc_memory_region: memory@aa000000 { reg =3D <0x00 0xaa000000 0x00 0x01c00000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index f252007262d3..ff5264d4c2da 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -31,103 +31,103 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5100000 0x00 0xf00000>; no-map; }; =20 - c71_0_dma_memory_region: c71-dma-memory@a6000000 { + c71_0_dma_memory_region: memory@a6000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6000000 0x00 0x100000>; no-map; }; =20 - c71_0_memory_region: c71-memory@a6100000 { + c71_0_memory_region: memory@a6100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6100000 0x00 0xf00000>; no-map; }; =20 - c71_1_dma_memory_region: c71-dma-memory@a7000000 { + c71_1_dma_memory_region: memory@a7000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7000000 0x00 0x100000>; no-map; }; =20 - c71_1_memory_region: c71-memory@a7100000 { + c71_1_memory_region: memory@a7100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a8000000 { + rtos_ipc_memory_region: memory@a8000000 { reg =3D <0x00 0xa8000000 0x00 0x01c00000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index 2b9e007432a9..d323284a30ab 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -52,67 +52,67 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + wkup_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + wkup_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000= { + mcu_r5fss0_core0_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { + mcu_r5fss0_core0_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a20000= 00 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { + c7x_0_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - c7x_0_memory_region: c7x-memory@a3100000 { + c7x_0_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { + c7x_1_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - c7x_1_memory_region: c7x-memory@a4100000 { + c7x_1_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - rtos_ipc_memory_region: ipc-memories@a5000000 { + rtos_ipc_memory_region: memory@a5000000 { reg =3D <0x00 0xa5000000 0x00 0x1c00000>; alignment =3D <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index a84bde08f85e..2ed1ec6d53c8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -28,13 +28,13 @@ reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; =20 - c71_3_dma_memory_region: c71-dma-memory@ab000000 { + c71_3_dma_memory_region: memory@ab000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xab000000 0x00 0x100000>; no-map; }; =20 - c71_3_memory_region: c71-memory@ab100000 { + c71_3_memory_region: memory@ab100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xab100000 0x00 0xf00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index c269e5b29b96..fdde1bd0e831 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -35,133 +35,133 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1000000 0x00 0x100000>; no-map; }; =20 - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa1100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa2100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3000000 0x00 0x100000>; no-map; }; =20 - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa4100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5000000 0x00 0x100000>; no-map; }; =20 - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa5100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + main_r5fss2_core0_dma_memory_region: memory@a6000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6000000 0x00 0x100000>; no-map; }; =20 - main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + main_r5fss2_core0_memory_region: memory@a6100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6100000 0x00 0xf00000>; no-map; }; =20 - main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + main_r5fss2_core1_dma_memory_region: memory@a7000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7000000 0x00 0x100000>; no-map; }; =20 - main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + main_r5fss2_core1_memory_region: memory@a7100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7100000 0x00 0xf00000>; no-map; }; =20 - c71_0_dma_memory_region: c71-dma-memory@a8000000 { + c71_0_dma_memory_region: memory@a8000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa8000000 0x00 0x100000>; no-map; }; =20 - c71_0_memory_region: c71-memory@a8100000 { + c71_0_memory_region: memory@a8100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa8100000 0x00 0xf00000>; no-map; }; =20 - c71_1_dma_memory_region: c71-dma-memory@a9000000 { + c71_1_dma_memory_region: memory@a9000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa9000000 0x00 0x100000>; no-map; }; =20 - c71_1_memory_region: c71-memory@a9100000 { + c71_1_memory_region: memory@a9100000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa9100000 0x00 0xf00000>; no-map; }; =20 - c71_2_dma_memory_region: c71-dma-memory@aa000000 { + c71_2_dma_memory_region: memory@aa000000 { compatible =3D "shared-dma-pool"; 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Mon, 8 Sep 2025 09:30:04 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecq1037553; Mon, 8 Sep 2025 09:29:59 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Robert Nelson Subject: [PATCH v4 14/34] arm64: dts: ti: k3-j721e-beagleboneai64: Add missing cfg for TI IPC FW Date: Mon, 8 Sep 2025 19:58:06 +0530 Message-ID: <20250908142826.1828676-15-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI IPC Firmwares running on J721E SoCs use certain MAIN domain timers as tick. Reserve those at board level DT to avoid remote processor crashes. This config aligns with other J721E boards and can be refactored out later. Signed-off-by: Beleswar Padhi --- Cc: Robert Nelson Requesting for review/test of this patch. v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-14-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-14-b-padhi@ti.com/ v2: Changelog: 1. Split [PATCH 06/33] into [PATCH v2 13/33] and [PATCH v2 22/33]. This patch only reserves the timer nodes used by rproc firmware. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-7-b-padhi@ti.com/ .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index ac4d90e82aab..66c4614f9e42 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -935,6 +935,35 @@ mbox_c71_0: mbox-c71-0 { }; }; =20 +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status =3D "reserved"; +}; + +&main_timer1 { + status =3D "reserved"; +}; + +&main_timer2 { + status =3D "reserved"; +}; + +&main_timer12 { + status =3D "reserved"; +}; + +&main_timer13 { + status =3D "reserved"; +}; + +&main_timer14 { + status =3D "reserved"; +}; + +&main_timer15 { + status =3D "reserved"; +}; + &mcu_r5fss0 { status =3D "okay"; }; --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A87081A9FA8; Mon, 8 Sep 2025 14:30:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341820; cv=none; b=iBnOtTmJE9w9wztYZpIoUCTzq8bxkfnzsK/ECD+/jYql/zUdT2FkvlMTYA8mOL7tWbpxh8MNp5bz0/50QMknlBzBlAMQ63J0BH0/z4Jx38D3A/qPdWWyDDTgGHZDXp8da9pR+YmHxtTFKENZ1QHsNCSEteOsCqpANdXDSlSM8v4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341820; c=relaxed/simple; bh=mCvNefpm3X1d5CPBNW2nvQeu6euRRme4omoZM/wmVo4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mRjefNq+QA6PByECU8Irv1zjUfLnCtfn9BOSjMiBE+tAFlmPxX9YO+IuHSu/ERBnbOPK7cm5vICeLYfDh/sE1ZkDk+YU166CAp6orpheie/SPbMFjhdfHExvV8JzxZiZaQI8D9i+LsqwNCddLbuJ+B9+ya++xTz1ghHsEiyAT/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=dO16PSg5; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="dO16PSg5" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 588EUAq6071614; Mon, 8 Sep 2025 09:30:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757341810; bh=b0wBhaKXtjGUz6kkTHFGePg1AFzstofbpng1uUtJ6YM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dO16PSg5U7CIvzY3bV6MPf93Z9+lBxAxCaomWmyJmmbtk8XogytPlO7j4FnqIJdmI 5h+vKB8vR7n4xDB2wfdFAZIfxkzFnBiaxmlMm82e1gGQKqYgL01CavKZH7feNYMXAK nQyTAdygj7POHQrxkUiAJposjRTnbw+D+icbgM5E= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 588EUAkL3020760 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 09:30:10 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:30:10 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:30:10 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecr1037553; Mon, 8 Sep 2025 09:30:04 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Hiago De Franco , Francesco Dolcini , Emanuele Ghidoli , Parth Pancholi , Jo_o Paulo Gon_alves Subject: [PATCH v4 15/34] arm64: dts: ti: k3-am62p-verdin: Add missing cfg for TI IPC Firmware Date: Mon, 8 Sep 2025 19:58:07 +0530 Message-ID: <20250908142826.1828676-16-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The wkup_r5fss0_core0_memory_region is used to store the text/data sections of the Device Manager (DM) firmware itself and is necessary for platform boot. Whereas the wkup_r5fss0_core0_dma_memory_region is used for allocating the Virtio buffers needed for IPC with the DM core which could be optional. The labels were incorrectly used in the k3-am62p-verdin.dtsi file. Correct the firmware memory region label. Currently, only mailbox node is enabled with FIFO assignment. However, there are no users of the enabled mailboxes. Add the missing carveouts for WKUP and MCU R5F remote processors, and enable those by associating to the above carveout and mailboxes. This config aligns with other AM62P boards and can be refactored out later. Signed-off-by: Beleswar Padhi Tested-by: Hiago De Franco # Verdin AM62P Acked-by: Francesco Dolcini --- Cc: Francesco Dolcini Cc: Emanuele Ghidoli Cc: Parth Pancholi Cc: Jo_o Paulo Gon_alves Cc: Hiago De Franco Requesting for a review/test. v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-15-b-padhi@ti.com/ v3: Changelog: 1. Changed carveout node names to memory@addr. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-15-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 16/33] to [PATCH v2 14/33]. 2. Added T/B tag. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-17-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/= dts/ti/k3-am62p-verdin.dtsi index 522d6f029c36..671d367b40d1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -162,6 +162,24 @@ secure_ddr: optee@9e800000 { no-map; }; =20 + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c900000 0x00 0x01e00000>; @@ -848,6 +866,28 @@ mbox_mcu_r5_0: mbox-mcu-r5-0 { }; }; =20 +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + &main0_alert { temperature =3D <95000>; }; --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C231D131E2D; Mon, 8 Sep 2025 14:30:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" The wkup_r5fss0_core0_memory_region is used to store the text/data sections of the Device Manager (DM) firmware itself and is necessary for platform boot. Whereas the wkup_r5fss0_core0_dma_memory_region is used for allocating the Virtio buffers needed for IPC with the DM core which could be optional. The labels were incorrectly used in the k3-am62-verdin.dtsi file. Correct the firmware memory region label. Currently, only mailbox node is enabled with FIFO assignment for a single M4F remote core. However, there are no users of the enabled mailboxes. Add the missing carveouts for WKUP R5F and MCU M4F remote processors, and enable those by associating to the above carveout and mailboxes. This config aligns with other AM62 boards and can be refactored out later. Signed-off-by: Beleswar Padhi Tested-by: Hiago De Franco # Verdin AM62 Acked-by: Francesco Dolcini --- Cc: Francesco Dolcini Cc: Hiago De Franco Cc: Jo_o Paulo Gon_alves Cc: Stefan Eichenberger Cc: Max Krummenacher Cc: Andrejs Cainikovs Requesting for review/test of this patch v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-16-b-padhi@ti.com/ v3: Changelog: 1. Changed carveout node names to memory@addr. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-16-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 18/33] to [PATCH v2 15/33]. 2. Added T/B tag. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-19-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 43 +++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-verdin.dtsi index 9384c9a0232a..5ecdd833587e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -206,7 +206,25 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: memory@9db00000 { + mcu_m4fss_dma_memory_region: memory@9cb00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@9cc00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: memory@9db00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9db00000 0x00 0xc00000>; no-map; @@ -1323,6 +1341,29 @@ mbox_m4_0: mbox-m4-0 { ti,mbox-rx =3D <0 0 0>; ti,mbox-tx =3D <1 0 0>; }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 /* Verdin CAN_1 */ --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED8AA30F94A; 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Mon, 8 Sep 2025 09:30:21 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:30:21 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:30:21 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESect1037553; Mon, 8 Sep 2025 09:30:16 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Robert Nelson Subject: [PATCH v4 17/34] arm64: dts: ti: k3-am62-pocketbeagle2: Add missing cfg for TI IPC Firmware Date: Mon, 8 Sep 2025 19:58:09 +0530 Message-ID: <20250908142826.1828676-18-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The wkup_r5fss0_core0_memory_region is used to store the text/data sections of the Device Manager (DM) firmware itself and is necessary for platform boot. Whereas the wkup_r5fss0_core0_dma_memory_region is used for allocating the Virtio buffers needed for IPC with the DM core which could be optional. The labels were incorrectly used in the k3-am62-pocketbeagle2.dts file. Correct the firmware memory region label Currently, only mailbox node is enabled with FIFO assignment for a single M4F remote core. Add the missing carveouts for WKUP R5F remote processor, and enable that by associating to the above carveout and mailbox. This config aligns with other AM62 boards and can be refactored out later. Signed-off-by: Beleswar Padhi Reviewed-by: Dhruva Gole --- Cc: Robert Nelson Requesting for review/test of this patch v4: Changelog: 1. Changed node names to generic 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-17-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-17-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 19/33] to [PATCH v2 16/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-20-b-padhi@ti.com/ .../boot/dts/ti/k3-am62-pocketbeagle2.dts | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/= boot/dts/ti/k3-am62-pocketbeagle2.dts index 2d46be298b0b..621fb6c52db1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -78,7 +78,13 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: memory@9db00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: memory@9db00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9db00000 0x00 0xc00000>; no-map; @@ -299,6 +305,11 @@ mbox_m4_0: mbox-m4-0 { ti,mbox-rx =3D <0 0 0>; ti,mbox-tx =3D <1 0 0>; }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; }; =20 &main_uart0 { @@ -358,6 +369,17 @@ &mcu_m4fss { status =3D "okay"; }; =20 +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + &mcu_pmx0 { wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins =3D < --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C86930EF81; Mon, 8 Sep 2025 14:30:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341839; cv=none; b=beFZINaLTHv0m3ghe60HUG4EdmYAD0NsWTV4uDju4IYkAPQOZi2nz9BUVlgxctpOlHhTVPCGdZyjh2htHWaWMtN9eQN4yodznm296ptShlbpbFhiAhinKpovREWR4l4me3CqFxvDK1yNI51z1yy7EX7Pc1r0wR7/r2PbNZJhtWI= ARC-Message-Signature: i=1; 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Mon, 8 Sep 2025 09:30:26 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecu1037553; Mon, 8 Sep 2025 09:30:21 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Josua Mayer , Logan Bristol , Matthias Schiffer Subject: [PATCH v4 18/34] arm64: dts: ti: k3-am642-sr-som: Add missing cfg for TI IPC Firmware Date: Mon, 8 Sep 2025 19:58:10 +0530 Message-ID: <20250908142826.1828676-19-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Currently, only R5F remote processors are enabled for k3-am642-sr SoMs, whereas the M4F in MCU domain is disabled. Enable the M4F remote processor at board level by reserving memory carveouts and assigning mailboxes. While at it, reserve the MAIN domain timers that are used by R5F remote processors for ticks to avoid rproc crashes. This config aligns with other AM64 boards and can be refactored out later. Signed-off-by: Beleswar Padhi --- Cc: Josua Mayer Cc: Logan Bristol Cc: Matthias Schiffer Requesting for review/test of this patch. v4: Changelog: 1. Updated carveout node names to generic 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-18-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-18-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 27/33] to [PATCH v2 17/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-28-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 54 +++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/= dts/ti/k3-am642-sr-som.dtsi index 35294a5c46d5..38feda717d7a 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -162,6 +162,24 @@ main_r5fss1_core1_memory_region: memory@a3100000 { reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; + + mcu_m4fss_dma_memory_region: memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a5000000 { + reg =3D <0x00 0xa5000000 0x00 0x00800000>; + alignment =3D <0x1000>; + no-map; + }; }; =20 vdd_mmc0: regulator-vdd-mmc0 { @@ -291,6 +309,35 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { }; }; =20 +&mailbox0_cluster6 { + status =3D "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx =3D <0 0 2>; + ti,mbox-tx =3D <1 0 2>; + }; +}; + +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status =3D "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status =3D "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status =3D "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status =3D "reserved"; +}; + &main_i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_default_pins>; @@ -524,6 +571,13 @@ &main_r5fss1_core1 { status =3D "okay"; }; =20 +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + /* SoC default UART console */ &main_uart0 { pinctrl-names =3D "default"; --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFBB1310783; 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Mon, 8 Sep 2025 09:30:33 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:30:33 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:30:33 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecv1037553; Mon, 8 Sep 2025 09:30:27 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Wadim Egorov , Matt McKee , Garrett Giordano , Nathan Morrisson , John Ma , Logan Bristol Subject: [PATCH v4 19/34] arm64: dts: ti: k3-am64-phycore-som: Add missing cfg for TI IPC Firmware Date: Mon, 8 Sep 2025 19:58:11 +0530 Message-ID: <20250908142826.1828676-20-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The k3-am64-phycore SoM enables all R5F and M4F remote processors. Reserve the MAIN domain timers that are used by R5F remote processors for ticks to avoid rproc crashes. This config aligns with other AM64 boards and can be refactored out later. Signed-off-by: Beleswar Padhi Tested-by: Wadim Egorov --- Cc: Wadim Egorov Cc: Matt McKee Cc: Garrett Giordano Cc: Nathan Morrisson Cc: John Ma Cc: Logan Bristol Requesting for review/test of this patch. v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-19-b-padhi@ti.com/ v3: Changelog: 1. Carried T/B tag. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-19-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 28/33] to [PATCH v2 18/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-29-b-padhi@ti.com/ .../boot/dts/ti/k3-am64-phycore-som.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am64-phycore-som.dtsi index ba425b125d63..5e0c82960a6c 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -275,6 +275,30 @@ mbox_m4_0: mbox-m4-0 { }; }; =20 +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status =3D "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status =3D "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status =3D "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status =3D "reserved"; +}; + +&main_r5fss0 { + status =3D "okay"; +}; + &main_i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_pins_default>; --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF45A1DF26E; Mon, 8 Sep 2025 14:30:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341846; cv=none; b=G8rpnLQ/0gheRdHMVrhCD/M/RE5rEnpe82IRTfT1nvAe88nuweCSPsgxJ4nriGZuqaPsp/6o5qRgyvyW4otQJpe5L2EAxmqeu1dnl7tq6YOagE//p/zvkMhr8EKQcs4530mLr3uhADfmeQ+FKDL0bA+Ap12o5D083+j6bMN0FTc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341846; c=relaxed/simple; bh=tsEBDBmRULEMBJ2eXXYee3Y6YWJ6kKce90MqXTpxQjM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=chbNmsXqcL00MCLAvYTH6+3QjNz7pSHKT1M3nNkJB2QfcfhrGb2/KbMTvVuPPLuyzJm9OWyjp4u20DnbYV+EEbyDFhpeZ2kN9MmKrJeVIKazHm73HwoNKQJ1BWVf/iwvvudBLytoq6M4BbxzK1EDQp2AC+wMdAGo6Eu3R9c64eQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=UnJ1mXmx; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="UnJ1mXmx" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 588EUcvQ3883548; Mon, 8 Sep 2025 09:30:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757341838; bh=KNDeTcriY+g/ZMvH40cW+600x4qCRysa7bksKPsxzYc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UnJ1mXmx6SP/xzO9f4GflYr+OkuIkhAFZlonhryotMII6/UknpuTLMQ9ZRJ0MqxIM tIGne+4N0E1HnOj/xUmiZL8q9dWKFbIloEaunNSHAFY3Piu1ITfSlu0G9zDgm8m0sv hthmET8aWnsUMvGGzIbE+BIxs5rSxX9So/UAsCdU= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 588EUcUL3021101 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 09:30:38 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:30:38 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:30:38 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESecw1037553; Mon, 8 Sep 2025 09:30:33 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Matthias Schiffer Subject: [PATCH v4 20/34] arm64: dts: ti: k3-am642-tqma64xxl: Add missing cfg for TI IPC Firmware Date: Mon, 8 Sep 2025 19:58:12 +0530 Message-ID: <20250908142826.1828676-21-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Currently, only R5F remote processors are enabled for k3-am642-tqma64xxl whereas the M4F in MCU domain is disabled. Enable the M4F remote processor at board level by reserving memory carveouts and assigning mailboxes. While at it, reserve the MAIN domain timers that are used by R5F remote processors for ticks to avoid rproc crashes. This config aligns with other AM64 boards and can be refactored out later. Signed-off-by: Beleswar Padhi --- Cc: Matthias Schiffer Request for review/test of this patch. v4: Changelog: 1. Updated carveout node names to generic 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-20-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-20-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 29/33] to [PATCH v2 19/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-30-b-padhi@ti.com/ .../arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am642-tqma64xxl.dtsi index 4068d2c2b10c..f6d1e980d32f 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -79,6 +79,18 @@ main_r5fss1_core1_memory_region: memory@a3100000 { no-map; }; =20 + mcu_m4fss_dma_memory_region: memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: memory@a5000000 { reg =3D <0x00 0xa5000000 0x00 0x00800000>; alignment =3D <0x1000>; @@ -167,6 +179,26 @@ mbox_m4_0: mbox-m4-0 { }; }; =20 +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status =3D "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status =3D "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status =3D "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status =3D "reserved"; +}; + &main_r5fss0 { status =3D "okay"; }; @@ -203,6 +235,13 @@ &main_r5fss1_core1 { status =3D "okay"; }; =20 +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + &ospi0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1B9A30F535; Mon, 8 Sep 2025 14:30:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; 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charset="utf-8" This reverts commit 9f3814a7c06b7c7296cf8c1622078ad71820454b. The C6x carveouts are reversed intentionally. This is due to the requirement to keep the DMA memory region as non-cached, however the minimum granular cache region for C6x is 16MB. So, C66x_0 marks the entire C66x_1 16MB memory carveouts as non-cached, and uses the DMA memory region of C66x_1 as its own, and vice-versa. This was also called out in the original commit which introduced these reversed carveouts: "The minimum granularity on the Cache settings on C66x DSP cores is 16MB, so the DMA memory regions are chosen such that they are in separate 16MB regions for each DSP, while reserving a total of 16 MB for each DSP and not changing the overall DSP remoteproc carveouts." Fixes: 9f3814a7c06b ("arm64: dts: ti: k3-j721e-sk: Fix reversed C6x carveou= t locations") Signed-off-by: Beleswar Padhi --- v4: Changelog: 1. Updated carveout node names to generic 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-21-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-21-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 03/33] to [PATCH v2 20/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-4-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 0f05e65f7bf7..37bc33f2cc26 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -120,7 +120,8 @@ main_r5fss1_core1_memory_region: memory@a5100000 { no-map; }; =20 - c66_0_dma_memory_region: memory@a6000000 { + /* Carveout locations are flipped due to caching */ + c66_1_dma_memory_region: memory@a6000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6000000 0x00 0x100000>; no-map; @@ -132,7 +133,8 @@ c66_0_memory_region: memory@a6100000 { no-map; }; =20 - c66_1_dma_memory_region: memory@a7000000 { + /* Carveout locations are flipped due to caching */ + c66_0_dma_memory_region: memory@a7000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7000000 0x00 0x100000>; no-map; --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A3EA30C63B; Mon, 8 Sep 2025 14:30:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341856; cv=none; b=X9OfU8Fd/Pe/DJZgX6i3R6U+mo1y4rIYxCFfzt81vZSjWHn3cEdNMVkiOnEZcOCrsvgzvTLN4hM0Nsu4grrdlntqvIN3jwALoWSj76xcPuZ5ePTDLvMWkRny8OVhF+OvPfmXDc854su5a2yzdc5/EHVVQL3xJ6bMafGToCj7qoU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341856; c=relaxed/simple; bh=c60DcTlRug1elyU4jF0MKcGB81enrFFXoVDIEEmpTMI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=b0JxtCM0o57FX1hva0lzleFLfOZr2hKT+jgtiSJBmRrilEGxcT/fneHRIRm2fVQZOiX5FPTMjUzM1vb5aqRDemFt6j0MUz6i/FksT5p/4cm1zrmr16qrIcYHwdcV2NTe1YQjNXpsx5wWhxuKcgi/Pb/e/jMsABFUcAcO7a3J9eo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=EeXrUvXn; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="EeXrUvXn" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 588EUoS2071690; Mon, 8 Sep 2025 09:30:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757341850; bh=Q0G5fMfFq368J1CSgGKkpxs50mM6teQ4fVzBMLGiUHY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EeXrUvXnwb/y7fILvJFgRrf7vGiWAZNuw3eaPp4Uqvp+GzkCu8ZKz43K1tjsx2EO1 d6gb5mHTWbtE9NZV6pA5/M9mkbp1fO1iZteeLnM/AQCwjRAzp1vuSYAzf9FjJegdsC JqKJU97mzaKFHraMtQhLjSKx/GAlByyE/DxwxhBM= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 588EUowA3835561 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 09:30:50 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:30:47 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:30:47 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESed01037553; Mon, 8 Sep 2025 09:30:43 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 22/34] Revert "arm64: dts: ti: k3-j721e-beagleboneai64: Fix reversed C6x carveout locations" Date: Mon, 8 Sep 2025 19:58:14 +0530 Message-ID: <20250908142826.1828676-23-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" This reverts commit 1a314099b7559690fe23cdf3300dfff6e830ecb1. The C6x carveouts are reversed intentionally. This is due to the requirement to keep the DMA memory region as non-cached, however the minimum granular cache region for C6x is 16MB. So, C66x_0 marks the entire C66x_1 16MB memory carveouts as non-cached, and uses the DMA memory region of C66x_1 as its own, and vice-versa. This was also called out in the original commit which introduced these reversed carveouts: "The minimum granularity on the Cache settings on C66x DSP cores is 16MB, so the DMA memory regions are chosen such that they are in separate 16MB regions for each DSP, while reserving a total of 16 MB for each DSP and not changing the overall DSP remoteproc carveouts." Fixes: 1a314099b755 ("arm64: dts: ti: k3-j721e-beagleboneai64: Fix reversed= C6x carveout locations") Signed-off-by: Beleswar Padhi --- v4: Changelog: 1. Updaed node names to 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-22-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-22-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 04/33] to [PATCH v2 21/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-5-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 66c4614f9e42..92f5e4a14a49 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -123,7 +123,8 @@ main_r5fss1_core1_memory_region: memory@a5100000 { no-map; }; =20 - c66_0_dma_memory_region: memory@a6000000 { + /* Carveout locations are flipped due to caching */ + c66_1_dma_memory_region: memory@a6000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6000000 0x00 0x100000>; no-map; @@ -135,7 +136,8 @@ c66_0_memory_region: memory@a6100000 { no-map; }; =20 - c66_1_dma_memory_region: memory@a7000000 { + /* Carveout locations are flipped due to caching */ + c66_0_dma_memory_region: memory@a7000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7000000 0x00 0x100000>; no-map; --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDF31311949; Mon, 8 Sep 2025 14:30:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341859; cv=none; b=WtKzvWVWLz9SUepfPT3lQs7gPHYro+z8BSzQMHdo2vRMPiqXFIXwAgbAwZDijnkqx9fvjppx959kG0CAggkD6UwKg5r22AzU1q48o8gcKnil38rGuF6raXmHpro0w6gKEogZy7IVdNdg0dM3qrnvvJ6P+edDS7SIKIFsW7T/g/A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341859; c=relaxed/simple; bh=oY80pW/was+AuqcFIjz6WHSDDqv4vJpDRwAIiKqsj5s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qjMHJceBjvMLVqSHblsXeQlBL6HR/NP5kMsrNq9obp3rCjW4BnjR+HGuZ2tYfOtKOzJgp8L5mfjVOuC1A7LJ4xO/YGm2t4WzO6YMswJJ/qiQkew6q7XoLEx0d/QdssKVyQ6wpeQW658CK3RdD1Sts+GJtUQHEIp/G+tSSjCpwUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=VgJDWexs; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VgJDWexs" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 588EUrSv3883569; Mon, 8 Sep 2025 09:30:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757341853; bh=6yfW6NnAc+YqJbw3pkggnHrxvyuQfI1HfG4W55w/utU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VgJDWexs5TCSi2xCi78BGSbNc16DPKsxFy+95pNuqhN1EBVi/LExntNW5DUhv8Ga1 pQLi+nIZRtNCca2154n85EdY6HcpJ8zjA2c/P6RY5MtmGpVmv2fGneFVMJ3sVTNOBZ PJTNZRRL/ON7r3BaR6n9yxfk0Sro7/NXgOHtLZYg= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 588EUrOR3065013 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 09:30:53 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:30:52 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:30:52 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESed11037553; Mon, 8 Sep 2025 09:30:48 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Robert Nelson Subject: [PATCH v4 23/34] arm64: dts: ti: k3-j721e-beagleboneai64: Switch MAIN R5F clusters to Split-mode Date: Mon, 8 Sep 2025 19:58:15 +0530 Message-ID: <20250908142826.1828676-24-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Switch the MAIN domain R5F clusters into split mode to maximize the number of R5F processors. The TI IPC firmware for the split processors is already available public. This config aligns with other J721E boards and can be refactored out later. Signed-off-by: Beleswar Padhi --- Cc: Robert Nelson Requesting for review/test of this patch. v4: Changelog: 1. None Link to v3: https://lore.kernel.org/all/20250905051846.1189612-23-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-23-b-padhi@ti.com/ v2: Changelog: 1. Split patch from [PATCH 06/33] to [PATCH v2 13/33] and [PATCH v2 22/33]. This patch switches the Main domain R5Fs into split mode. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-7-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 92f5e4a14a49..3a7813c8770f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -985,6 +985,7 @@ &mcu_r5fss0_core1 { }; =20 &main_r5fss0 { + ti,cluster-mode =3D <0>; status =3D "okay"; }; =20 @@ -1003,6 +1004,7 @@ &main_r5fss0_core1 { }; =20 &main_r5fss1 { + ti,cluster-mode =3D <0>; status =3D "okay"; }; =20 --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78859311976; Mon, 8 Sep 2025 14:31:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341864; cv=none; b=OAdwE3cYYIk4FyWNtEejosvaeby/ywAtBOQpFoZl0cexmakTm9zNSG82Wz3HaK11Ev4LVnjUFdXUtSlwz5aVIhNz8l1dGdxyeN77QgJpJnx2Q/gHljbh/2mdIB0K+RPFt00pBfAGxyuBINrFOH/N3s4p0kP7DgJDMplqW11CjL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341864; c=relaxed/simple; bh=b35ClakyTZZyfQzqYrXOqPypaP2FAVYsfwTWDK1+cS0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UUgwZXk54ftL/Tkx7xeEiNfLwE6VuIveFIrurg9C3Z0jJovFcPM6SWg033z/nVPcl/m2qcMl1Hfsz5J8mAtuh07/2Gb8wiHmxcLiARfrOxJSnXLbkQOVpIiDrpQSOeOnuUIQT8EvBB8zmJ2bZq9qH1UtDJWYNB647AwgFs8zIcg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=xnBwUafR; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xnBwUafR" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 588EUv6K120744; Mon, 8 Sep 2025 09:30:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757341857; bh=TG1LtKX0tdP2t3mfCrJOwWBCs1D+18xGpP7/K9IBq2o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xnBwUafRxMr8GVcM0BEl+f/2MPfag1jJw7hQuZDABOcuHDwCfc/tkvFNHZ90GOxeS Henurbhnp109OCxsEX8tXUEGv6nApuGfaoeiUWF2omQWx7y9egkXniwQ8r5HxWmItF s7fH6NpXN9vf2tzpscwt/lcHIMUCASXloZfi+5PM= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 588EUvBh3065225 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 09:30:57 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:30:57 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:30:57 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESed21037553; Mon, 8 Sep 2025 09:30:53 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 24/34] arm64: dts: ti: k3-j7200-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Mon, 8 Sep 2025 19:58:16 +0530 Message-ID: <20250908142826.1828676-25-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 J7200 SoCs have multiple programmable remote processors like R5Fs. The TI SDKs for J7200 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi --- v4: Changelog: 1. Updated memory node names to 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-24-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-24-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 02/33] to [PATCH v2 23/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-3-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 124 +---------------- .../boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi | 130 ++++++++++++++++++ 2 files changed, 132 insertions(+), 122 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j7200-som-p0.dtsi index c689e417cf45..5a8c2e707fde 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -40,48 +40,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a4000000 { - reg =3D <0x00 0xa4000000 0x00 0x00800000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 mux0: mux-controller-0 { @@ -224,86 +182,6 @@ partition@800000 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - &main_i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_pins_default>; @@ -546,3 +424,5 @@ &main_mcan0 { pinctrl-names =3D "default"; phys =3D <&transceiver0>; }; + +#include "k3-j7200-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi b/arch/ar= m64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..9477f1efbbc6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J7200 SoCs + * + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a4000000 { + reg =3D <0x00 0xa4000000 0x00 0x00800000>; + alignment =3D <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + interrupts =3D <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + interrupts =3D <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status =3D "reserved"; +}; + +&main_timer1 { + status =3D "reserved"; +}; + +&main_timer2 { + status =3D "reserved"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&mcu_r5fss0_core1 { + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss0 { + ti,cluster-mode =3D <0>; + status =3D "okay"; +}; + +&main_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&main_r5fss0_core1 { + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region =3D <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA66A311979; Mon, 8 Sep 2025 14:31:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; 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charset="utf-8" The TI K3 J721E SoCs have multiple programmable remote processors like R5F, C6x, C7x etc. The TI SDKs for J721E SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi --- v4: Changelog: 1. Updated carveout node names to 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-25-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-25-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 07/33] to [PATCH v2 24/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-8-b-padhi@ti.com/ .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 280 +---------------- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 280 +---------------- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 278 +---------------- .../boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi | 288 ++++++++++++++++++ 4 files changed, 291 insertions(+), 835 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 3a7813c8770f..352fb60e6ce8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -62,110 +62,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - /* Carveout locations are flipped due to caching */ - c66_1_dma_memory_region: memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - /* Carveout locations are flipped due to caching */ - c66_0_dma_memory_region: memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a8000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a8100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@aa000000 { - reg =3D <0x00 0xaa000000 0x00 0x01c00000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 gpio_keys: gpio-keys { @@ -867,178 +763,4 @@ &ufs_wrapper { status =3D "disabled"; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - interrupts =3D <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status =3D "okay"; - interrupts =3D <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - interrupts =3D <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&main_timer12 { - status =3D "reserved"; -}; - -&main_timer13 { - status =3D "reserved"; -}; - -&main_timer14 { - status =3D "reserved"; -}; - -&main_timer15 { - status =3D "reserved"; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss0_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss1_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster3 &mbox_c66_0>; - memory-region =3D <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster3 &mbox_c66_1>; - memory-region =3D <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; +#include "k3-j721e-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 37bc33f2cc26..5e5784ef6f85 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -59,110 +59,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - /* Carveout locations are flipped due to caching */ - c66_1_dma_memory_region: memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - /* Carveout locations are flipped due to caching */ - c66_0_dma_memory_region: memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a8000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a8100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@aa000000 { - reg =3D <0x00 0xaa000000 0x00 0x01c00000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 vusb_main: fixedregulator-vusb-main5v0 { @@ -1281,178 +1177,4 @@ &ufs_wrapper { status =3D "disabled"; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - interrupts =3D <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status =3D "okay"; - interrupts =3D <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - interrupts =3D <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&main_timer12 { - status =3D "reserved"; -}; - -&main_timer13 { - status =3D "reserved"; -}; - -&main_timer14 { - status =3D "reserved"; -}; - -&main_timer15 { - status =3D "reserved"; -}; - -&main_r5fss0_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster3 &mbox_c66_0>; - memory-region =3D <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster3 &mbox_c66_1>; - memory-region =3D <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; +#include "k3-j721e-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/= dts/ti/k3-j721e-som-p0.dtsi index 06388f28d122..c8073ee634b7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -40,108 +40,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c66_1_dma_memory_region: memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a8000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a8100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@aa000000 { - reg =3D <0x00 0xaa000000 0x00 0x01c00000>; - alignment =3D <0x1000>; - no-map; - }; }; }; =20 @@ -484,178 +382,4 @@ partition@800000 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - interrupts =3D <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status =3D "okay"; - interrupts =3D <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - interrupts =3D <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - status =3D "okay"; - ti,cluster-mode =3D <0>; -}; - -&main_r5fss1 { - status =3D "okay"; - ti,cluster-mode =3D <0>; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&main_timer12 { - status =3D "reserved"; -}; - -&main_timer13 { - status =3D "reserved"; -}; - -&main_timer14 { - status =3D "reserved"; -}; - -&main_timer15 { - status =3D "reserved"; -}; - -&main_r5fss0_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster3 &mbox_c66_0>; - memory-region =3D <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster3 &mbox_c66_1>; - memory-region =3D <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; +#include "k3-j721e-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi b/arch/ar= m64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..40c6cc99c405 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J721E SoCs + * + * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: memory@a5000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: memory@a5100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + /* Carveout locations are flipped due to caching */ + c66_1_dma_memory_region: memory@a6000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c66_0_memory_region: memory@a6100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + /* Carveout locations are flipped due to caching */ + c66_0_dma_memory_region: memory@a7000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c66_1_memory_region: memory@a7100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: memory@a8000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: memory@a8100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@aa000000 { + reg =3D <0x00 0xaa000000 0x00 0x01c00000>; + alignment =3D <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + interrupts =3D <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + interrupts =3D <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + interrupts =3D <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status =3D "okay"; + interrupts =3D <424>; + + mbox_c66_0: mbox-c66-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_c66_1: mbox-c66-1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status =3D "okay"; + interrupts =3D <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status =3D "reserved"; +}; + +&main_timer1 { + status =3D "reserved"; +}; + +&main_timer2 { + status =3D "reserved"; +}; + +&main_timer12 { + status =3D "reserved"; +}; + +&main_timer13 { + status =3D "reserved"; +}; + +&main_timer14 { + status =3D "reserved"; +}; + +&main_timer15 { + status =3D "reserved"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0 { + status =3D "okay"; + ti,cluster-mode =3D <0>; +}; + +&main_r5fss0_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region =3D <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1 { + status =3D "okay"; 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Mon, 8 Sep 2025 09:31:07 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:31:06 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:31:06 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESed41037553; Mon, 8 Sep 2025 09:31:02 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 26/34] arm64: dts: ti: k3-j721s2-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Mon, 8 Sep 2025 19:58:18 +0530 Message-ID: <20250908142826.1828676-27-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 J721S2 SoCs have multiple programmable remote processors like R5F, C7x etc. The TI SDKs for J721S2 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi --- v4: Changelog: 1. Updated carveout node names to generic 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-26-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-26-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 09/33] to [PATCH v2 25/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-10-b-padhi@ti.com/ .../boot/dts/ti/k3-am68-phycore-som.dtsi | 247 +---------------- arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 241 +---------------- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 243 +---------------- .../dts/ti/k3-j721s2-ti-ipc-firmware.dtsi | 253 ++++++++++++++++++ 4 files changed, 258 insertions(+), 726 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am68-phycore-som.dtsi index b9c60e078d21..adef02bd8040 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi @@ -60,96 +60,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a8000000 { - reg =3D <0x00 0xa8000000 0x00 0x01c00000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 vdd_sd_dv: regulator-sd { @@ -243,80 +153,6 @@ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT_PULLUP, 0) /* (H27)= WKUP_I2C0_SDA */ }; }; =20 -&c71_0 { - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; - status =3D "okay"; -}; - -&c71_1 { - mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; - memory-region =3D <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; - status =3D "okay"; -}; - -&mailbox0_cluster0 { - interrupts =3D <436>; - status =3D "okay"; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - interrupts =3D <432>; - status =3D "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - interrupts =3D <428>; - status =3D "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - interrupts =3D <420>; - status =3D "okay"; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - &main_cpsw { pinctrl-names =3D "default"; pinctrl-0 =3D <&rgmii1_pins_default>; @@ -367,34 +203,6 @@ &main_gpio0 { status =3D "okay"; }; =20 -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - /* eMMC */ &main_sdhci0 { non-removable; @@ -409,59 +217,6 @@ &main_sdhci1 { bootph-all; }; =20 -&main_r5fss0 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&main_timer3 { - status =3D "reserved"; -}; - -&main_timer4 { - status =3D "reserved"; -}; - -&main_timer5 { - status =3D "reserved"; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - &ospi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; @@ -611,3 +366,5 @@ som_eeprom_opt: eeprom@51 { pagesize =3D <32>; }; }; + +#include "k3-j721s2-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/d= ts/ti/k3-am68-sk-som.dtsi index c423b1443e0c..6a6dc816b658 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -38,96 +38,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a8000000 { - reg =3D <0x00 0xa8000000 0x00 0x01c00000>; - alignment =3D <0x1000>; - no-map; - }; }; }; =20 @@ -235,153 +145,4 @@ partition@3fc0000 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - interrupts =3D <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - interrupts =3D <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&main_timer3 { - status =3D "reserved"; -}; - -&main_timer4 { - status =3D "reserved"; -}; - -&main_timer5 { - status =3D "reserved"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&c71_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; - memory-region =3D <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; +#include "k3-j721s2-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index ff5264d4c2da..12a38dd1514b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -42,96 +42,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a8000000 { - reg =3D <0x00 0xa8000000 0x00 0x01c00000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 mux0: mux-controller-0 { @@ -516,157 +426,6 @@ partition@3fc0000 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - interrupts =3D <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - interrupts =3D <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&main_timer3 { - status =3D "reserved"; -}; - -&main_timer4 { - status =3D "reserved"; -}; - -&main_timer5 { - status =3D "reserved"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&c71_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; - memory-region =3D <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; - &main_i2c4 { bridge_dsi_edp: bridge-dsi-edp@2c { compatible =3D "ti,sn65dsi86"; @@ -693,3 +452,5 @@ port@1 { }; }; }; + +#include "k3-j721s2-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi b/arch/a= rm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..ebab0cc580bb --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J721S2 SoCs + * + * Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: memory@a5000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: memory@a5100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: memory@a6000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: memory@a6100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: memory@a7000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: memory@a7100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a8000000 { + reg =3D <0x00 0xa8000000 0x00 0x01c00000>; + alignment =3D <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + interrupts =3D <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + interrupts =3D <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + interrupts =3D <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status =3D "okay"; + interrupts =3D <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status =3D "reserved"; +}; + +&main_timer1 { + status =3D "reserved"; +}; + +&main_timer2 { + status =3D "reserved"; +}; + +&main_timer3 { + status =3D "reserved"; +}; + +&main_timer4 { + status =3D "reserved"; +}; + +&main_timer5 { + status =3D "reserved"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&mcu_r5fss0_core1 { + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss0 { + ti,cluster-mode =3D <0>; + status =3D "okay"; +}; + +&main_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&main_r5fss0_core1 { + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region =3D <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; 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Mon, 8 Sep 2025 09:31:12 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:31:11 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:31:11 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESed51037553; Mon, 8 Sep 2025 09:31:07 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 27/34] arm64: dts: ti: k3-j784s4-j742s2-ti-ipc-firmware-common: Refactor IPC cfg into new dtsi Date: Mon, 8 Sep 2025 19:58:19 +0530 Message-ID: <20250908142826.1828676-28-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 J784S4/J742S2 SoCs have multiple programmable remote processors like R5F, C7x etc. The TI SDKs for J784S4/J742S2 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi --- v4: Changelog: 1. Updated carveout node names to 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-27-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-27-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 11/33] to [PATCH v2 26/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-12-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am69-sk.dts | 336 +---------------- .../dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 344 +---------------- ...-j784s4-j742s2-ti-ipc-firmware-common.dtsi | 350 ++++++++++++++++++ 3 files changed, 354 insertions(+), 676 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware= -common.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index 60817c1f3104..3be74d828d84 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -61,126 +61,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core0_dma_memory_region: memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core0_memory_region: memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core1_dma_memory_region: memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core1_memory_region: memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a8000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a8100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: memory@a9000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa9000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: memory@a9100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa9100000 0x00 0xf00000>; - no-map; - }; - - c71_2_dma_memory_region: memory@aa000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xaa000000 0x00 0x100000>; - no-map; - }; - - c71_2_memory_region: memory@aa100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xaa100000 0x00 0xf00000>; - no-map; - }; - c71_3_dma_memory_region: memory@ab000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xab000000 0x00 0x100000>; @@ -640,84 +520,7 @@ &phy_gmii_sel { bootph-all; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - interrupts =3D <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status =3D "okay"; - interrupts =3D <424>; - mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - interrupts =3D <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - &mailbox0_cluster5 { - status =3D "okay"; - interrupts =3D <416>; - mbox_c71_2: mbox-c71-2 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - mbox_c71_3: mbox-c71-3 { ti,mbox-rx =3D <2 0 0>; ti,mbox-tx =3D <3 0 0>; @@ -992,143 +795,6 @@ &mcu_cpsw_port1 { bootph-all; }; =20 -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&main_timer3 { - status =3D "reserved"; -}; - -&main_timer4 { - status =3D "reserved"; -}; - -&main_timer5 { - status =3D "reserved"; -}; - -&main_timer6 { - status =3D "reserved"; -}; - -&main_timer7 { - status =3D "reserved"; -}; - -&main_timer8 { - status =3D "reserved"; -}; - -&main_timer9 { - status =3D "reserved"; -}; - -&main_r5fss2 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss2_core0 { - mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; - memory-region =3D <&main_r5fss2_core0_dma_memory_region>, - <&main_r5fss2_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss2_core1 { - mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; - memory-region =3D <&main_r5fss2_core1_dma_memory_region>, - <&main_r5fss2_core1_memory_region>; - status =3D "okay"; -}; - -&c71_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; - memory-region =3D <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; - -&c71_2 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster5 &mbox_c71_2>; - memory-region =3D <&c71_2_dma_memory_region>, - <&c71_2_memory_region>; -}; - &c71_3 { status =3D "okay"; mboxes =3D <&mailbox0_cluster5 &mbox_c71_3>; @@ -1418,3 +1084,5 @@ &usb0 { phys =3D <&serdes0_usb_link>; phy-names =3D "cdns3,usb3-phy"; }; + +#include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch= /arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index fdde1bd0e831..419c1a70e028 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -46,126 +46,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core0_dma_memory_region: memory@a6000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core0_memory_region: memory@a6100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core1_dma_memory_region: memory@a7000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core1_memory_region: memory@a7100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a8000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a8100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: memory@a9000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa9000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: memory@a9100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa9100000 0x00 0xf00000>; - no-map; - }; - - c71_2_dma_memory_region: memory@aa000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xaa000000 0x00 0x100000>; - no-map; - }; - - c71_2_memory_region: memory@aa100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xaa100000 0x00 0xf00000>; - no-map; - }; }; =20 evm_12v0: regulator-evm12v0 { @@ -1069,228 +949,6 @@ &main_cpsw1_port1 { status =3D "okay"; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - interrupts =3D <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status =3D "okay"; - interrupts =3D <424>; - - mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - interrupts =3D <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mailbox0_cluster5 { - status =3D "okay"; - interrupts =3D <416>; - - mbox_c71_2: mbox-c71-2 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -&main_r5fss2 { - ti,cluster-mode =3D <0>; - status =3D "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&main_timer3 { - status =3D "reserved"; -}; - -&main_timer4 { - status =3D "reserved"; -}; - -&main_timer5 { - status =3D "reserved"; -}; - -&main_timer6 { - status =3D "reserved"; -}; - -&main_timer7 { - status =3D "reserved"; -}; - -&main_timer8 { - status =3D "reserved"; -}; - -&main_timer9 { - status =3D "reserved"; -}; - -&main_r5fss0_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&main_r5fss2_core0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; - memory-region =3D <&main_r5fss2_core0_dma_memory_region>, - <&main_r5fss2_core0_memory_region>; -}; - -&main_r5fss2_core1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; - memory-region =3D <&main_r5fss2_core1_dma_memory_region>, - <&main_r5fss2_core1_memory_region>; -}; - -&c71_0 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; - memory-region =3D <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; - memory-region =3D <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; - -&c71_2 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster5 &mbox_c71_2>; - memory-region =3D <&c71_2_dma_memory_region>, - <&c71_2_memory_region>; -}; - &tscadc0 { pinctrl-0 =3D <&mcu_adc0_pins_default>; pinctrl-names =3D "default"; @@ -1619,3 +1277,5 @@ &mcasp0 { 0 0 0 0 >; }; + +#include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common= .dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi new file mode 100644 index 000000000000..455397227d4a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J784S4/J74= 2S2 SoCs + * + * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: memory@a5000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: memory@a5100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core0_dma_memory_region: memory@a6000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core0_memory_region: memory@a6100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core1_dma_memory_region: memory@a7000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core1_memory_region: memory@a7100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: memory@a8000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: memory@a8100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: memory@a9000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa9000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: memory@a9100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa9100000 0x00 0xf00000>; + no-map; + }; + + c71_2_dma_memory_region: memory@aa000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xaa000000 0x00 0x100000>; + no-map; + }; + + c71_2_memory_region: memory@aa100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xaa100000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + interrupts =3D <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + interrupts =3D <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + interrupts =3D <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status =3D "okay"; + interrupts =3D <424>; + + mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status =3D "okay"; + interrupts =3D <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status =3D "okay"; + interrupts =3D <416>; + + mbox_c71_2: mbox-c71-2 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status =3D "reserved"; +}; + +&main_timer1 { + status =3D "reserved"; +}; + +&main_timer2 { + status =3D "reserved"; +}; + +&main_timer3 { + status =3D "reserved"; +}; + +&main_timer4 { + status =3D "reserved"; +}; + +&main_timer5 { + status =3D "reserved"; +}; + +&main_timer6 { + status =3D "reserved"; +}; + +&main_timer7 { + status =3D "reserved"; +}; + +&main_timer8 { + status =3D "reserved"; +}; + +&main_timer9 { + status =3D "reserved"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0 { + ti,cluster-mode =3D <0>; + status =3D "okay"; +}; + +&main_r5fss0_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region =3D <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1 { + ti,cluster-mode =3D <0>; + status =3D "okay"; +}; + +&main_r5fss1_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region =3D <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region =3D <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&main_r5fss2 { + ti,cluster-mode =3D <0>; + status =3D "okay"; +}; + +&main_r5fss2_core0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; + memory-region =3D <&main_r5fss2_core0_dma_memory_region>, + <&main_r5fss2_core0_memory_region>; +}; + +&main_r5fss2_core1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; + memory-region =3D <&main_r5fss2_core1_dma_memory_region>, + <&main_r5fss2_core1_memory_region>; +}; + +&c71_0 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster4 &mbox_c71_0>; + memory-region =3D <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster4 &mbox_c71_1>; + memory-region =3D <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; + +&c71_2 { + status =3D "okay"; + mboxes =3D <&mailbox0_cluster5 &mbox_c71_2>; + memory-region =3D <&c71_2_dma_memory_region>, + <&c71_2_memory_region>; +}; --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BB5B3043A4; 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Mon, 8 Sep 2025 09:31:16 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:31:16 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:31:16 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESed61037553; Mon, 8 Sep 2025 09:31:12 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 28/34] arm64: dts: ti: k3-j784s4-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Mon, 8 Sep 2025 19:58:20 +0530 Message-ID: <20250908142826.1828676-29-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 J784S4 SoCs have multiple programmable remote processors like R5F, C7x etc. The TI SDKs for J784S4 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. This patch only refactors the C71_3 remote processor related nodes into the new dtsi. All other nodes have been refactored in the previous commit as part of k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi. Signed-off-by: Beleswar Padhi --- v4: Changelog: 1. Update node names to generic 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-28-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-28-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 12/33] to [PATCH v2 27/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-13-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am69-sk.dts | 27 +------------- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 26 +------------- .../dts/ti/k3-j784s4-ti-ipc-firmware.dtsi | 35 +++++++++++++++++++ 3 files changed, 37 insertions(+), 51 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index 3be74d828d84..5896e57b5b9e 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -60,18 +60,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - c71_3_dma_memory_region: memory@ab000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xab000000 0x00 0x100000>; - no-map; - }; - - c71_3_memory_region: memory@ab100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xab100000 0x00 0xf00000>; - no-map; - }; }; =20 vusb_main: regulator-vusb-main5v0 { @@ -520,13 +508,6 @@ &phy_gmii_sel { bootph-all; }; =20 -&mailbox0_cluster5 { - mbox_c71_3: mbox-c71-3 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - &wkup_uart0 { /* Firmware usage */ status =3D "reserved"; @@ -795,13 +776,6 @@ &mcu_cpsw_port1 { bootph-all; }; =20 -&c71_3 { - status =3D "okay"; - mboxes =3D <&mailbox0_cluster5 &mbox_c71_3>; - memory-region =3D <&c71_3_dma_memory_region>, - <&c71_3_memory_region>; -}; - &wkup_gpio_intr { status =3D "okay"; }; @@ -1086,3 +1060,4 @@ &usb0 { }; =20 #include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi" +#include "k3-j784s4-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index 2ed1ec6d53c8..6c7458c76f53 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -27,31 +27,7 @@ memory@80000000 { reserved_memory: reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; - - c71_3_dma_memory_region: memory@ab000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xab000000 0x00 0x100000>; - no-map; - }; - - c71_3_memory_region: memory@ab100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xab100000 0x00 0xf00000>; - no-map; - }; - }; -}; - -&mailbox0_cluster5 { - mbox_c71_3: mbox-c71-3 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; }; }; =20 -&c71_3 { - mboxes =3D <&mailbox0_cluster5 &mbox_c71_3>; - memory-region =3D <&c71_3_dma_memory_region>, - <&c71_3_memory_region>; - status =3D "okay"; -}; +#include "k3-j784s4-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi b/arch/a= rm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..81b508b9b05e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J784S4 SoCs + * + * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + c71_3_dma_memory_region: memory@ab000000 { + compatible =3D "shared-dma-pool"; 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Mon, 8 Sep 2025 09:31:21 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESed71037553; Mon, 8 Sep 2025 09:31:16 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 29/34] arm64: dts: ti: k3-j722s-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Mon, 8 Sep 2025 19:58:21 +0530 Message-ID: <20250908142826.1828676-30-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 J722S SoCs have multiple programmable remote processors like R5F, C7x etc. The TI SDKs for J722S SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi --- v4: Changelog: 1. Updated carveout node names to 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-29-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-29-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 14/33] to [PATCH v2 28/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-15-b-padhi@ti.com/ .../arm64/boot/dts/ti/k3-am67a-beagley-ai.dts | 155 +---------------- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 157 +---------------- .../boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi | 163 ++++++++++++++++++ 3 files changed, 166 insertions(+), 309 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/bo= ot/dts/ti/k3-am67a-beagley-ai.dts index 85436ea5b4e7..b697035df04e 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts @@ -61,60 +61,6 @@ wkup_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core0_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - c7x_0_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - c7x_1_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - c7x_1_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg =3D <0x00 0xa5000000 0x00 0x1c00000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 vsys_5v0: regulator-1 { @@ -453,103 +399,4 @@ &sdhci1 { status =3D "okay"; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_wkup_r5_0: mbox-wkup-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster3 { - status =3D "okay"; - - mbox_main_r5_0: mbox-main-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c7x_1: mbox-c7x-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_wkup_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0 { - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster3 &mbox_main_r5_0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&c7x_0 { - mboxes =3D <&mailbox0_cluster2 &mbox_c7x_0>; - memory-region =3D <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; - status =3D "okay"; -}; - -&c7x_1 { - mboxes =3D <&mailbox0_cluster3 &mbox_c7x_1>; - memory-region =3D <&c7x_1_dma_memory_region>, - <&c7x_1_memory_region>; - status =3D "okay"; -}; +#include "k3-j722s-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index d323284a30ab..a9b5d9a06241 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -63,60 +63,6 @@ wkup_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core0_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - c7x_0_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - c7x_1_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - c7x_1_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg =3D <0x00 0xa5000000 0x00 0x1c00000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 vmain_pd: regulator-0 { @@ -788,107 +734,6 @@ &sdhci1 { bootph-all; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_wkup_r5_0: mbox-wkup-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster3 { - status =3D "okay"; - - mbox_main_r5_0: mbox-main-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_c7x_1: mbox-c7x-1 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status =3D "reserved"; -}; - -&main_timer1 { - status =3D "reserved"; -}; - -&main_timer2 { - status =3D "reserved"; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_wkup_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0 { - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster3 &mbox_main_r5_0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&c7x_0 { - mboxes =3D <&mailbox0_cluster2 &mbox_c7x_0>; - memory-region =3D <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; - status =3D "okay"; -}; - -&c7x_1 { - mboxes =3D <&mailbox0_cluster3 &mbox_c7x_1>; - memory-region =3D <&c7x_1_dma_memory_region>, - <&c7x_1_memory_region>; - status =3D "okay"; -}; - &serdes_ln_ctrl { idle-states =3D , ; @@ -999,3 +844,5 @@ &mcu_i2c0 { clock-frequency =3D <400000>; status =3D "okay"; }; + +#include "k3-j722s-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi b/arch/ar= m64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..cb7cd385a165 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J722S SoCs + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + mcu_r5fss0_core0_dma_memory_region: memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + c7x_0_dma_memory_region: memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + c7x_1_dma_memory_region: memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + c7x_1_memory_region: memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a5000000 { + reg =3D <0x00 0xa5000000 0x00 0x1c00000>; + alignment =3D <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + + mbox_wkup_r5_0: mbox-wkup-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster3 { + status =3D "okay"; + + mbox_main_r5_0: mbox-main-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_c7x_1: mbox-c7x-1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status =3D "reserved"; +}; + +&main_timer1 { + status =3D "reserved"; +}; + +&main_timer2 { + status =3D "reserved"; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_wkup_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&main_r5fss0 { + status =3D "okay"; +}; + +&main_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster3 &mbox_main_r5_0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&c7x_0 { + mboxes =3D <&mailbox0_cluster2 &mbox_c7x_0>; + memory-region =3D <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status =3D "okay"; +}; + +&c7x_1 { + mboxes =3D <&mailbox0_cluster3 &mbox_c7x_1>; + memory-region =3D <&c7x_1_dma_memory_region>, + <&c7x_1_memory_region>; + status =3D "okay"; +}; --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 917FB312836; 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Mon, 8 Sep 2025 09:31:26 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:31:25 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:31:25 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESed81037553; Mon, 8 Sep 2025 09:31:21 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Subject: [PATCH v4 30/34] arm64: dts: ti: k3-am62p-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Mon, 8 Sep 2025 19:58:22 +0530 Message-ID: <20250908142826.1828676-31-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 AM62P SoCs have multiple programmable remote processors like R5Fs. The TI SDKs for AM62P SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Tested-by: Judith Mendez Reviewed-by: Dhruva Gole --- v4: Changelog: 1. Updated node names to generic 'memory@addr' 2. Carried R/B tag. Link to v3: https://lore.kernel.org/all/20250905051846.1189612-30-b-padhi@ti.com/ v3: Changelog: 1. Carried T/B tag. 2. Changed memory node name to memory@addr. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-30-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 17/33] to [PATCH v2 29/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-18-b-padhi@ti.com/ .../boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi | 60 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 54 +---------------- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 54 +---------------- 3 files changed, 64 insertions(+), 104 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi b/arch/ar= m64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..d29a5dbe13ef --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM62P SoCs + * + * Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/= dts/ti/k3-am62p-verdin.dtsi index 671d367b40d1..99810047614e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -162,18 +162,6 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@9b900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c800000 0x00 0x100000>; @@ -848,46 +836,6 @@ &epwm2 { status =3D "disabled"; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - &main0_alert { temperature =3D <95000>; }; @@ -1466,3 +1414,5 @@ &wkup_uart0 { uart-has-rtscts; status =3D "disabled"; }; + +#include "k3-am62p-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index aa363aaf6d59..56f0eb11b902 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -49,18 +49,6 @@ reserved_memory: reserved-memory { #size-cells =3D <2>; ranges; =20 - mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@9b900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c800000 0x00 0x100000>; @@ -699,46 +687,6 @@ partition@3fc0000 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - &main_uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins_default>; @@ -810,3 +758,5 @@ &epwm1 { pinctrl-0 =3D <&main_epwm1_pins_default>; status =3D "okay"; }; + +#include "k3-am62p-ti-ipc-firmware.dtsi" --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A161F30F938; Mon, 8 Sep 2025 14:31:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341901; cv=none; b=NDOrQaEUEEAXtJp36wwT2iWLOenbEM64JXJrsZE/5ORx8Dvik4YxMNl2WTEqj0/JsAXGMvFogGzbpTlebXWrvOioDl+Sw2Mzje7HU22maViOd3vmsTY0vw/hpiBUsQUoSdSjeisTs3X6/qvXBuODHxwxmu/7V33UyW/jKgbjgNc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341901; c=relaxed/simple; bh=e+frbV8iVyJj4q9h2e3zbt198W5glPK8qWzPVMkFpP4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Mon, 8 Sep 2025 09:31:26 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Wadim Egorov Subject: [PATCH v4 31/34] arm64: dts: ti: k3-am62-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Mon, 8 Sep 2025 19:58:23 +0530 Message-ID: <20250908142826.1828676-32-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 AM62 SoCs have multiple programmable remote processors like R5F, M4F etc. The TI SDKs for AM62 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Reviewed-by: Wadim Egorov Tested-by: Wadim Egorov # phycore-am62x Reviewed-by: Dhruva Gole --- v4: Changelog: 1. Updated node names to generic 'memory@addr' 2. Carried R/B tag. Link to v3: https://lore.kernel.org/all/20250905051846.1189612-31-b-padhi@ti.com/ v3: Changelog: 1. Changed memory node name to memory@addr.=20 2. Carried R/B, T/B tags. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-31-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 22/33] to [PATCH v2 30/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-23-b-padhi@ti.com/ .../boot/dts/ti/k3-am62-phycore-som.dtsi | 44 +--------------- .../boot/dts/ti/k3-am62-pocketbeagle2.dts | 46 +--------------- .../boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi | 52 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 46 +--------------- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 46 +--------------- 5 files changed, 59 insertions(+), 175 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am62-phycore-som.dtsi index 75b7e64f6659..eeca643fedbe 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -52,18 +52,6 @@ rtos_ipc_memory_region: memory@9c800000 { no-map; }; =20 - mcu_m4fss_dma_memory_region: memory@9cb00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@9cc00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9da00000 0x00 0x100000>; @@ -245,20 +233,6 @@ cpsw3g_phy1: ethernet-phy@1 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - &main_pktdma { bootph-all; }; @@ -364,13 +338,6 @@ i2c_som_rtc: rtc@52 { }; }; =20 -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - &ospi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; @@ -399,13 +366,4 @@ &sdhci0 { status =3D "okay"; }; =20 -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/= boot/dts/ti/k3-am62-pocketbeagle2.dts index 621fb6c52db1..7a4cffc27bda 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -54,18 +54,6 @@ linux,cma { linux,cma-default; }; =20 - mcu_m4fss_dma_memory_region: memory@9cb00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@9cc00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; alignment =3D <0x1000>; @@ -298,20 +286,6 @@ &epwm2 { pinctrl-0 =3D <&epwm2_pins_default>; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - &main_uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins_default>; @@ -362,24 +336,6 @@ &main_i2c2 { status =3D "okay"; }; =20 -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - &mcu_pmx0 { wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins =3D < @@ -543,3 +499,5 @@ ldo4_reg: ldo4 { }; }; }; + +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi b/arch/arm= 64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..ea69fab9b52b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM62 SoCs + * + * Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + mcu_m4fss_dma_memory_region: memory@9cb00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@9cc00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-verdin.dtsi index 5ecdd833587e..dc4b228a9fd7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -206,18 +206,6 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - mcu_m4fss_dma_memory_region: memory@9cb00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@9cc00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9da00000 0x00 0x100000>; @@ -1334,38 +1322,6 @@ &main_i2c3 { status =3D "disabled"; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - /* Verdin CAN_1 */ &main_mcan0 { pinctrl-names =3D "default"; @@ -1549,3 +1505,5 @@ &wkup_uart0 { pinctrl-0 =3D <&pinctrl_wkup_uart0>; status =3D "disabled"; }; + +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 05cba3cfc79e..241902fc1cf2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -58,18 +58,6 @@ linux,cma { linux,cma-default; }; =20 - mcu_m4fss_dma_memory_region: memory@9cb00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@9cc00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9da00000 0x00 0x100000>; @@ -477,38 +465,6 @@ cpsw3g_phy0: ethernet-phy@0 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - &usbss0 { bootph-all; status =3D "okay"; @@ -601,3 +557,5 @@ &epwm1 { pinctrl-0 =3D <&main_epwm1_pins_default>; status =3D "okay"; }; + +#include "k3-am62-ti-ipc-firmware.dtsi" --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA85E30AD1A; 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charset="utf-8" The TI K3 AM62A SoCs have multiple programmable remote processors like R5F, C7x etc. The TI SDKs for AM62A SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Tested-by: Judith Mendez Reviewed-by: Dhruva Gole --- v4: Changelog: 1. Updated node names to generic 'memory@addr' 2. Carried R/B tag. Link to v3: https://lore.kernel.org/all/20250905051846.1189612-32-b-padhi@ti.com/ v3: Changelog: 1. Carried T/B tag. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-32-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 25/33] to [PATCH v2 31/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-26-b-padhi@ti.com/ .../boot/dts/ti/k3-am62a-phycore-som.dtsi | 90 +---------------- .../boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi | 98 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 92 +---------------- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 76 +------------- 4 files changed, 102 insertions(+), 254 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/= boot/dts/ti/k3-am62a-phycore-som.dtsi index 0406a43ff704..b3d012a5a26a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -59,30 +59,6 @@ linux,cma { linux,cma-default; }; =20 - c7x_0_dma_memory_region: memory@99800000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x99800000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: memory@99900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x99900000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@9b900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c800000 0x00 0x100000>; @@ -209,13 +185,6 @@ opp-1400000000 { }; }; =20 -&c7x_0 { - mboxes =3D <&mailbox0_cluster1 &mbox_c7x_0>; - memory-region =3D <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; - status =3D "okay"; -}; - &cpsw3g { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_rgmii1_pins_default>; @@ -246,33 +215,6 @@ &fss { status =3D "okay"; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - &main_i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_pins_default>; @@ -388,27 +330,6 @@ &main_pktdma { bootph-all; }; =20 -/* main_rti4 is used by C7x DSP */ -&main_rti4 { - status =3D "reserved"; -}; - -/* main_timer2 is used by C7x DSP */ -&main_timer2 { - status =3D "reserved"; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_mcu_r5_0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - &ospi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; @@ -437,13 +358,4 @@ &sdhci0 { status =3D "okay"; }; =20 -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; +#include "k3-am62a-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi b/arch/ar= m64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..950f4f37d477 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM62A SoCs + * + * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + c7x_0_dma_memory_region: memory@99800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: memory@99900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0>, <&mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&c7x_0 { + mboxes =3D <&mailbox0_cluster1>, <&mbox_c7x_0>; + memory-region =3D <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status =3D "okay"; +}; + +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status =3D "reserved"; +}; + +/* main_timer2 is used by C7x DSP */ +&main_timer2 { + status =3D "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index 312bdab28784..9f148b89e74d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -53,30 +53,6 @@ linux,cma { linux,cma-default; }; =20 - c7x_0_dma_memory_region: memory@99800000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x99800000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: memory@99900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x99900000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@9b900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c800000 0x00 0x100000>; @@ -713,11 +689,6 @@ &main_uart1 { status =3D "reserved"; }; =20 -/* main_timer2 is used by C7x DSP */ -&main_timer2 { - status =3D "reserved"; -}; - &usbss0 { status =3D "okay"; ti,vbus-divider; @@ -835,67 +806,6 @@ &epwm1 { status =3D "okay"; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0>, <&mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&c7x_0 { - mboxes =3D <&mailbox0_cluster1>, <&mbox_c7x_0>; - memory-region =3D <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; - status =3D "okay"; -}; - -/* main_rti4 is used by C7x DSP */ -&main_rti4 { - status =3D "reserved"; -}; - &fss { status =3D "okay"; }; @@ -937,3 +847,5 @@ AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ >; }; }; + +#include "k3-am62a-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62d2-evm.dts index 289f52b3481f..c958a1c4a657 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -58,30 +58,6 @@ secure_tfa_ddr: tfa@80000000 { no-map; }; =20 - c7x_0_dma_memory_region: memory@99800000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x99800000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: memory@99900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x99900000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@9b900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c800000 0x00 0x100000>; @@ -551,66 +527,16 @@ cpsw3g_phy1: ethernet-phy@3 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - &wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; bootph-pre-ram; }; =20 -&mcu_r5fss0 { - status =3D "okay"; -}; - &mcu_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_mcu_r5_0>; - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; firmware-name =3D "am62d-mcu-r5f0_0-fw"; - status =3D "okay"; }; =20 &c7x_0 { - mboxes =3D <&mailbox0_cluster1 &mbox_c7x_0>; - memory-region =3D <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; firmware-name =3D "am62d-c71_0-fw"; - status =3D "okay"; }; =20 -/* main_rti4 is used by C7x DSP */ -&main_rti4 { - status =3D "reserved"; -}; +#include "k3-am62a-ti-ipc-firmware.dtsi" --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CCC230FC09; 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Mon, 8 Sep 2025 09:31:41 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 09:31:40 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 09:31:40 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESedB1037553; Mon, 8 Sep 2025 09:31:36 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Wadim Egorov Subject: [PATCH v4 33/34] arm64: dts: ti: k3-am64-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Mon, 8 Sep 2025 19:58:25 +0530 Message-ID: <20250908142826.1828676-34-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 AM64 SoCs have multiple programmable remote processors like R5F, M4F etc. The TI SDKs for AM64 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Reviewed-by: Wadim Egorov # phycore-am64x Tested-by: Wadim Egorov # phycore-am64x Tested-by: Hari Nagalla Reviewed-by: Dhruva Gole --- v4: Changelog: 1. Updated memory node names to generic 'memory@addr' 2. Carried R/B tag. Link to v3: https://lore.kernel.org/all/20250905051846.1189612-33-b-padhi@ti.com/ v3: Changelog: 1. Carried R/B, T/B tags. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-33-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 30/33] to [PATCH v2 32/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-31-b-padhi@ti.com/ .../boot/dts/ti/k3-am64-phycore-som.dtsi | 160 +---------------- .../boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi | 162 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 156 +---------------- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 156 +---------------- arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 156 +---------------- .../arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 156 +---------------- 6 files changed, 172 insertions(+), 774 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am64-phycore-som.dtsi index 5e0c82960a6c..02ef1dd92eaa 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -52,60 +52,6 @@ main_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg =3D <0x00 0xa5000000 0x00 0x00800000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 leds { @@ -238,67 +184,6 @@ &cpsw_port1 { status =3D "okay"; }; =20 -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status =3D "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status =3D "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status =3D "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status =3D "reserved"; -}; - -&main_r5fss0 { - status =3D "okay"; -}; - &main_i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_pins_default>; @@ -373,49 +258,6 @@ &main_pktdma { bootph-all; }; =20 -&main_r5fss0 { - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1 { - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - &ospi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; @@ -451,3 +293,5 @@ adc { ti,adc-channels =3D <0 1 2 3 4 5 6 7>; }; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi b/arch/arm= 64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..6b10646ae64a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM64 SoCs + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: memory@a2000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: memory@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + mcu_m4fss_dma_memory_region: memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a5000000 { + reg =3D <0x00 0xa5000000 0x00 0x00800000>; + alignment =3D <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx =3D <0 0 2>; + ti,mbox-tx =3D <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx =3D <2 0 2>; + ti,mbox-tx =3D <3 0 2>; + }; +}; + +&mailbox0_cluster4 { + status =3D "okay"; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx =3D <0 0 2>; + ti,mbox-tx =3D <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx =3D <2 0 2>; + ti,mbox-tx =3D <3 0 2>; + }; +}; + +&mailbox0_cluster6 { + status =3D "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx =3D <0 0 2>; + ti,mbox-tx =3D <1 0 2>; + }; +}; + +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status =3D "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status =3D "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status =3D "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status =3D "reserved"; +}; + +&main_r5fss0 { + status =3D "okay"; +}; + +&main_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&main_r5fss0_core1 { + mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region =3D <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + status =3D "okay"; +}; + +&main_r5fss1_core0 { + mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region =3D <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1_core1 { + mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region =3D <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; + status =3D "okay"; +}; + +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index ebc9fedc4d72..85dcff104936 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -64,60 +64,6 @@ main_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg =3D <0x00 0xa5000000 0x00 0x00800000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 evm_12v0: regulator-0 { @@ -727,106 +673,6 @@ partition@3fc0000 { }; }; =20 -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; -}; - -&main_r5fss0 { - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1 { - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status =3D "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status =3D "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status =3D "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status =3D "reserved"; -}; - &serdes_ln_ctrl { idle-states =3D ; }; @@ -890,3 +736,5 @@ &icssg1_iep0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&icssg1_iep0_pins_default>; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index d2b06e508c7f..1fb1b91a1bad 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -62,60 +62,6 @@ main_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg =3D <0x00 0xa5000000 0x00 0x00800000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 vusb_main: regulator-0 { @@ -642,106 +588,6 @@ partition@3fc0000 { }; }; =20 -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; -}; - -&main_r5fss0 { - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1 { - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status =3D "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status =3D "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status =3D "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status =3D "reserved"; -}; - &ecap0 { status =3D "okay"; /* PWM is available on Pin 1 of header J3 */ @@ -755,3 +601,5 @@ &eqep0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_eqep0_pins_default>; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/= dts/ti/k3-am642-sr-som.dtsi index 38feda717d7a..fcbcc04521b8 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -126,60 +126,6 @@ main_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg =3D <0x00 0xa5000000 0x00 0x00800000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 vdd_mmc0: regulator-vdd-mmc0 { @@ -281,63 +227,6 @@ ethernet_phy2: ethernet-phy@f { }; }; =20 -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status =3D "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status =3D "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status =3D "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status =3D "reserved"; -}; - &main_i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_default_pins>; @@ -535,49 +424,6 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB= 0_DRVVBUS */ }; }; =20 -&main_r5fss0 { - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1 { - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - /* SoC default UART console */ &main_uart0 { pinctrl-names =3D "default"; @@ -656,3 +502,5 @@ &usbss0 { ti,vbus-divider; ti,usb2-only; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am642-tqma64xxl.dtsi index f6d1e980d32f..ff3b2e0b8dd4 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -42,60 +42,6 @@ main_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg =3D <0x00 0xa5000000 0x00 0x00800000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 reg_1v8: regulator-1v8 { @@ -142,106 +88,6 @@ eeprom1: eeprom@54 { }; }; =20 -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status =3D "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status =3D "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status =3D "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status =3D "reserved"; -}; - -&main_r5fss0 { - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1 { - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - &ospi0 { status =3D "okay"; pinctrl-names =3D "default"; @@ -315,3 +161,5 @@ AM64X_IOPAD(0x0008, PIN_INPUT, 0) >; }; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" --=20 2.34.1 From nobody Wed Sep 10 02:01:34 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8E8B30C603; Mon, 8 Sep 2025 14:31:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341915; cv=none; b=lKTW5Xv5k2GeXTl7dxvGy4vQqtV0du0tBgNh47UnSNSjj1ldK+qAsNLtvPlBvtTYzb/JZCzHZeQaYaALiE/0ig4ZLClgB7AokCK0tWcayFmeeSEiSJ/QPw6KNGpGQJvoaZ4clIUmmgE+Y1BoIBYjT8AN3g70br0k7r+GLca+Egw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757341915; c=relaxed/simple; bh=qqvLiOWphBmzKOVF2cjHpoDClBnWoaYIyM4jU5kOtRI=; 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Mon, 8 Sep 2025 09:31:46 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588ESedC1037553; Mon, 8 Sep 2025 09:31:41 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , , Diogo Ivo , Li Hua Qian , Jan Kiszka , Baocheng Su , Benedikt Niedermayr Subject: [PATCH v4 34/34] arm64: dts: ti: k3-am65-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Mon, 8 Sep 2025 19:58:26 +0530 Message-ID: <20250908142826.1828676-35-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908142826.1828676-1-b-padhi@ti.com> References: <20250908142826.1828676-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 AM65 SoCs have multiple programmable remote processors like R5Fs. The TI SDKs for AM65 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi --- Cc: Diogo Ivo Cc: Li Hua Qian Cc: Jan Kiszka Cc: Baocheng Su Cc: Benedikt Niedermayr Requesting for review/test of this patch. v4: Changelog: 1. Updated carveout node names to generic 'memory@addr' Link to v3: https://lore.kernel.org/all/20250905051846.1189612-34-b-padhi@ti.com/ v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-34-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 32/33] to [PATCH v2 33/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-33-b-padhi@ti.com/ .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 62 ++---------------- .../boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi | 64 +++++++++++++++++++ .../arm64/boot/dts/ti/k3-am654-base-board.dts | 58 +---------------- 3 files changed, 72 insertions(+), 112 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index df2eed0b4048..42ba3dab2fc1 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -59,24 +59,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0 0xa1000000 0 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0 0xa1100000 0 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a2000000 { - reg =3D <0x00 0xa2000000 0x00 0x00200000>; - alignment =3D <0x1000>; - no-map; - }; - /* To reserve the power-on(PON) reason for watchdog reset */ wdt_reset_memory_region: wdt-memory@a2200000 { reg =3D <0x00 0xa2200000 0x00 0x1000>; @@ -582,44 +564,6 @@ &pcie1_rc { reset-gpios =3D <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-tx =3D <1 0 0>; - ti,mbox-rx =3D <0 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-tx =3D <1 0 0>; - ti,mbox-rx =3D <0 0 0>; - }; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - status =3D "okay"; -}; - -&mcu_r5fss0_core1 { - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; - status =3D "okay"; -}; - &mcu_rti1 { memory-region =3D <&wdt_reset_memory_region>; }; @@ -692,3 +636,9 @@ &mcu_r5fss0 { /* lock-step mode not supported on iot2050 boards */ ti,cluster-mode =3D <0>; }; + +#include "k3-am65-ti-ipc-firmware.dtsi" + +&rtos_ipc_memory_region { + reg =3D <0x00 0xa2000000 0x00 0x00200000>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi b/arch/arm= 64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..61ab0357fc0d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM65 SoCs + * + * Copyright (C) 2016-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0xa1000000 0 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0xa1100000 0 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a2000000 { + reg =3D <0x00 0xa2000000 0x00 0x00100000>; + alignment =3D <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + interrupts =3D <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-tx =3D <1 0 0>; + ti,mbox-rx =3D <0 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + interrupts =3D <432>; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-tx =3D <1 0 0>; + ti,mbox-rx =3D <0 0 0>; + }; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + status =3D "okay"; +}; + +&mcu_r5fss0_core1 { + memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index 3ca771a4f9c7..0c42c486d83a 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -61,24 +61,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg =3D <0 0xa0100000 0 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0 0xa1000000 0 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0 0xa1100000 0 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a2000000 { - reg =3D <0x00 0xa2000000 0x00 0x00100000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 gpio-keys { @@ -521,44 +503,6 @@ &serdes1 { status =3D "disabled"; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-tx =3D <1 0 0>; - ti,mbox-rx =3D <0 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-tx =3D <1 0 0>; - ti,mbox-rx =3D <0 0 0>; - }; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - status =3D "okay"; -}; - -&mcu_r5fss0_core1 { - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; - status =3D "okay"; -}; - &ospi0 { status =3D "okay"; pinctrl-names =3D "default"; @@ -653,3 +597,5 @@ &dss { &wkup_gpio0 { bootph-all; }; + +#include "k3-am65-ti-ipc-firmware.dtsi" --=20 2.34.1