From nobody Wed Sep 10 01:34:23 2025 Received: from mail.grinn-global.com (mail.grinn-global.com [77.55.128.204]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F1162FE04F; Mon, 8 Sep 2025 13:17:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=77.55.128.204 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757337448; cv=none; b=MuPGBsusksJDd4Ixp6xGyMCplzHYpyTtlWSaGyjot0ONTnvvaSPr94NNypOd+GRrKoLloeCFrPdODIIckKPEaJLTaX2Uag8QNNzxLWnHNt/GRmX3I9RSyWeNFpjIswYzIniE5T+eA3GWBsyhCt7JysLM2vxazgyoXZD95RCtop8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757337448; c=relaxed/simple; bh=J8dFM/HrJWgiGaRDg/OJNfiDZ1JTY6X946g87aqwciU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GX5PVWrYEqi6bXdgovlSNnC/iqd4xMZ/4a1PaEXSGU+I9jQoavfzpUHYsyqWL4xII6G5GouE4KGG6bWVaEGtDeqYYsbHBFpPNLXze06XGvWOITkJIFJK2mUrH/p/gizrniyxDUEf5RbaGYrczVpf2B2zG5+KO1cvndnMLsTfOaQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=grinn-global.com; spf=pass smtp.mailfrom=grinn-global.com; arc=none smtp.client-ip=77.55.128.204 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=grinn-global.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=grinn-global.com X-Virus-Scanned: by amavisd-new using ClamAV (9) X-Spam-Flag: NO X-Spam-Score: -1 X-Spam-Level: Received: from mateusz.int.grinn-global.com (f90-187.icpnet.pl [46.228.90.187]) by server220076.nazwa.pl (Postfix) with ESMTP id CE19A1BE98F; Mon, 08 Sep 2025 15:07:01 +0200 (CEST) From: Mateusz Koza To: angelogioacchino.delregno@collabora.com, robh@kernel.org Cc: krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, marcin.czarnecki@grinn-global.com, b.bilas@grinn-global.com, mateusz.koza@grinn-global.com, andrew@lunn.ch Subject: [PATCH v4 1/4] arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700 Date: Mon, 8 Sep 2025 15:05:34 +0200 Message-ID: <20250908130620.2309399-2-mateusz.koza@grinn-global.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908130620.2309399-1-mateusz.koza@grinn-global.com> References: <20250908130620.2309399-1-mateusz.koza@grinn-global.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NA-AI-Spam-Probability: 0.47 X-NA-AI-Is-Spam: no Content-Type: text/plain; charset="utf-8" Add support for Grinn GenioSBC-700. The Grinn GenioSBC-700 is a single-board computer based on the MediaTek Genio 700 SoC. Its device tree is split into separate SoM (.dtsi) and SBC (.dtsi) files, which are combined in the SoC-specific .dts file. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-700 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Reviewed-by: Andrew Lunn Signed-off-by: Mateusz Koza --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../mediatek/mt8390-grinn-genio-700-sbc.dts | 19 + .../dts/mediatek/mt8390-grinn-genio-sbc.dtsi | 538 ++++++++++++++++++ .../dts/mediatek/mt8390-grinn-genio-som.dtsi | 209 +++++++ 4 files changed, 767 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc= .dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index a4df4c21399e..b37a8c65e724 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-genio-510-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-genio-700-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-grinn-genio-700-sbc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-radxa-nio-12l-8-hd-panel.dtbo diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts b/= arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts new file mode 100644 index 000000000000..a37507a5a5d0 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza + */ +/dts-v1/; + +#include "mt8188.dtsi" +#include "mt8390-grinn-genio-som.dtsi" +#include "mt8390-grinn-genio-sbc.dtsi" + +/ { + model =3D "Grinn GenioSBC-700"; + compatible =3D "grinn,genio-700-sbc", "mediatek,mt8390", "mediatek,mt8188= "; + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 1 0x00000000>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi b/arc= h/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi new file mode 100644 index 000000000000..0e6006cd8ed9 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi @@ -0,0 +1,538 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza + */ + +#include + +/ { + chassis-type =3D "embedded"; + aliases { + ethernet0 =3D ð + i2c0 =3D &i2c0; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:921600n8"; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg =3D <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg =3D <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + + adsp_mem: memory@60000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x61000000 0 0x100000>; + no-map; + }; + }; + + reg_sbc_vsys: regulator-vsys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys"; + regulator-always-on; + regulator-boot-on; + }; + + reg_fixed_5v: regulator-0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed_5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + regulator-always-on; + vin-supply =3D <®_sbc_vsys>; + }; + + reg_fixed_4v2: regulator-1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed_4v2"; + regulator-min-microvolt =3D <4200000>; + regulator-max-microvolt =3D <4200000>; + enable-active-high; + regulator-always-on; + vin-supply =3D <®_sbc_vsys>; + }; + + reg_fixed_3v3: regulator-2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + regulator-always-on; + vin-supply =3D <®_sbc_vsys>; + }; +}; + +&pio { + gpio-line-names =3D + /* 0 - 4 */ "RPI_GPIO0", "RPI_GPIO1", "", "", "RPI_GPIO4", + /* 5 - 9 */ "", "RPI_GPIO6", "", "", "RPI_GPIO9", + /* 10 - 14 */ "RPI_GPIO10", "RPI_GPIO11", "", "", "", + /* 15 - 19 */ "", "", "", "", "", + /* 20 - 24 */ "", "RPI_GPIO21", "", "RPI_GPIO23", "", + /* 25 - 29 */ "", "", "", "", "", + /* 30 - 34 */ "RPI_GPIO30", "", "", "", "", + /* 35 - 39 */ "RPI_GPIO35", "RPI_GPIO36", "", "", "", + /* 40 - 44 */ "", "", "", "", "", + /* 45 - 49 */ "", "", "", "", "", + /* 50 - 54 */ "", "", "", "", "", + /* 55 - 59 */ "RPI_GPIO55", "RPI_GPIO56", "", "", "RPI_GPIO59", + /* 60 - 64 */ "RPI_GPIO60", "", "", "", "", + /* 65 - 69 */ "", "", "", "", "RPI_GPIO69", + /* 70 - 74 */ "", "", "RPI_GPIO72", "RPI_GPIO73", "RPI_GPIO74", + /* 75 - 79 */ "", "", "", "", "RPI_GPIO79", + /* 80 - 84 */ "RPI_GPIO80", "RPI_GPIO81", "RPI_GPIO82", "", "", + /* 85 - 89 */ "", "", "", "", "", + /* 90 - 94 */ "", "", "", "", "", + /* 95 - 99 */ "", "", "", "", "", + /*100 - 104 */ "", "", "", "", "", + /*105 - 109 */ "", "", "", "", "", + /*110 - 114 */ "", "", "", "", "", + /*115 - 119 */ "", "", "", "", "", + /*120 - 124 */ "", "RPI_GPIO121", "RPI_GPIO122", "RPI_GPIO123", "RPI_GPI= O124"; + + i2c0_pins: i2c0-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c5_pins: i2c5-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + pcie_pins_default: pcie-default { + mux { + pinmux =3D , + , + ; + bias-pull-up; + }; + }; + + eth_default_pins: eth-default-pins { + pins-cc { + pinmux =3D , + , + , + ; + drive-strength =3D <8>; + }; + + pins-mdio { + pinmux =3D , + ; + drive-strength =3D <8>; + input-enable; + }; + + pins-power { + pinmux =3D , + ; + output-high; + }; + + pins-rxd { + pinmux =3D , + , + , + ; + drive-strength =3D <8>; + }; + + pins-txd { + pinmux =3D , + , + , + ; + drive-strength =3D <8>; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux =3D , + , + , + ; + }; + + pins-mdio { + pinmux =3D , + ; + input-disable; + bias-disable; + }; + + pins-rxd { + pinmux =3D , + , + , + ; + }; + + pins-txd { + pinmux =3D , + , + , + ; + }; + }; + + spi2_pins: spi2-pins { + pins-spi { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; + + audio_default_pins: audio-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + ; + }; + }; + + usb_default_pins: usb-default-pins { + pins-valid { + pinmux =3D ; + input-enable; + }; + }; +}; + +ð { + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðernet_phy0>; + snps,reset-active-low; + snps,reset-delays-us =3D <0 11000 200000>; + mediatek,tx-delay-ps =3D <30>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <ð_default_pins>; + pinctrl-1 =3D <ð_sleep_pins>; + mediatek,mac-wol; + snps,reset-gpio =3D <&pio 147 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +ð_mdio { + ethernet_phy0: ethernet-phy@3 { + reg =3D <3>; + compatible =3D "ethernet-phy-ieee802.3-c22"; + eee-broken-1000t; + interrupts-extended =3D <&pio 148 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + pinctrl-0 =3D <&uart1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_pins_default>; + status =3D "okay"; +}; + +&pciephy { + status =3D "okay"; +}; + +&spi2 { + pinctrl-0 =3D <&spi2_pins>; + pinctrl-names =3D "default"; + mediatek,pad-select =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; +}; + +&u3phy0 { + status =3D "okay"; +}; + +&u3phy1 { + status =3D "okay"; +}; + +&u3phy2 { + status =3D "okay"; +}; + +&xhci1 { + status =3D "okay"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + hub_2_0: hub@1 { + compatible =3D "usb451,8027"; + reg =3D <1>; + peer-hub =3D <&hub_3_0>; + reset-gpios =3D <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply =3D <®_fixed_3v3>; + }; + + hub_3_0: hub@2 { + compatible =3D "usb451,8025"; + reg =3D <2>; + peer-hub =3D <&hub_2_0>; + reset-gpios =3D <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply =3D <®_fixed_3v3>; + }; +}; + +&xhci2 { + status =3D "okay"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + hub@1 { + compatible =3D "microchip,usb2513bi"; + reg =3D <1>; + vdd-supply =3D <®_fixed_3v3>; + }; +}; + +&ssusb0 { + status =3D "okay"; + dr_mode =3D "peripheral"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + pinctrl-0 =3D <&usb_default_pins>; + pinctrl-names =3D "default"; +}; + +&ssusb1 { + status =3D "okay"; + dr_mode =3D "host"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + maximum-speed =3D "super-speed"; +}; + +&ssusb2 { + status =3D "okay"; + dr_mode =3D "host"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + maximum-speed =3D "high-speed"; +}; + +&scp_cluster { + status =3D "okay"; +}; + +&scp_c0 { + firmware-name =3D "mediatek/mt8188/scp.img"; + memory-region =3D <&scp_mem>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&mt6359_vproc2_buck_reg>; + status =3D "okay"; +}; + +&adsp { + memory-region =3D <&adsp_dma_mem>, <&adsp_mem>; + status =3D "okay"; +}; + +&afe { + memory-region =3D <&afe_dma_mem>; + status =3D "okay"; +}; + +&sound { + compatible =3D "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb"; + model =3D "mt8390-evk"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_default_pins>; + audio-routing =3D + "Headphone", "Headphone L", + "Headphone", "Headphone R", + "AP DMIC", "AUDGLB", + "AP DMIC", "MIC_BIAS_0", + "AP DMIC", "MIC_BIAS_2", + "DMIC_INPUT", "AP DMIC"; + + mediatek,adsp =3D <&adsp>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi b/arc= h/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi new file mode 100644 index 000000000000..d88481beff9d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza + */ + +#include "mt6359.dtsi" +#include + +/ { + aliases { + i2c1 =3D &i2c1; + mmc0 =3D &mmc0; + }; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&mfg0 { + domain-supply =3D <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply =3D <&mt6359_vsram_others_ldo_reg>; +}; + +&mmc0 { + status =3D "okay"; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_default_pins>; + pinctrl-1 =3D <&mmc0_uhs_pins>; + bus-width =3D <8>; + max-frequency =3D <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay =3D <0x1481b>; + vmmc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply =3D <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-name =3D "vcn18_pmu"; + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-name =3D "vcn33_2_pmu"; + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-name =3D "dvdd_proc_l"; + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-name =3D "dvdd_core"; + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-name =3D "vpa_pmu"; + regulator-max-microvolt =3D <3100000>; +}; + +&mt6359_vproc2_buck_reg { + /* The name "vgpu" is required by mtk-regulator-coupler */ + regulator-name =3D "vgpu"; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <800000>; + regulator-coupled-with =3D <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread =3D <6250>; +}; + +&mt6359_vpu_buck_reg { + regulator-name =3D "dvdd_adsp"; + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-name =3D "va12_abb2_pmu"; + regulator-always-on; +}; + +&mt6359_vsim1_ldo_reg { + regulator-name =3D "vsim1_pmu"; + regulator-enable-ramp-delay =3D <480>; +}; + +&mt6359_vsram_others_ldo_reg { + /* The name "vsram_gpu" is required by mtk-regulator-coupler */ + regulator-name =3D "vsram_gpu"; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <800000>; + regulator-coupled-with =3D <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread =3D <6250>; +}; + +&mt6359_vufs_ldo_reg { + regulator-name =3D "vufs18_pmu"; + regulator-always-on; +}; + +&pio { + + i2c1_pins: i2c1-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + + pins-ds { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + }; +}; + +&pmic { + interrupt-parent =3D <&pio>; + interrupts =3D <222 IRQ_TYPE_LEVEL_HIGH>; + + mt6359keys: keys { + compatible =3D "mediatek,mt6359-keys"; + mediatek,long-press-mode =3D <1>; + power-off-time-sec =3D <0>; + + power-key { + linux,keycodes =3D ; + wakeup-source; + }; + }; +}; --=20 2.43.0 From nobody Wed Sep 10 01:34:23 2025 Received: from mail.grinn-global.com (mail.grinn-global.com [77.55.128.204]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC9C28F58; Mon, 8 Sep 2025 13:17:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=77.55.128.204 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757337445; cv=none; b=jqGbc2p1iTNrpZuRGibfu0eowe3NxQqSHwLUnKvwdoB9baax1uGnTUrUmmTlykyVODFZk8wIYXwESioX/WLDMPCa7K85eKpaxvpFYDRZglHfL6MgdOP7rnPGJMEhHxbfs/D/b2EULzUEXw2lyeQdiHX14tK7VETDhhmfrcHhtDQ= ARC-Message-Signature: i=1; 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Mon, 08 Sep 2025 15:07:04 +0200 (CEST) From: Mateusz Koza To: angelogioacchino.delregno@collabora.com, robh@kernel.org Cc: krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, marcin.czarnecki@grinn-global.com, b.bilas@grinn-global.com, mateusz.koza@grinn-global.com, andrew@lunn.ch, Conor Dooley Subject: [PATCH v4 2/4] dt-bindings: arm: mediatek: Add grinn,genio-700-sbc Date: Mon, 8 Sep 2025 15:05:35 +0200 Message-ID: <20250908130620.2309399-3-mateusz.koza@grinn-global.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908130620.2309399-1-mateusz.koza@grinn-global.com> References: <20250908130620.2309399-1-mateusz.koza@grinn-global.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NA-AI-Spam-Probability: 0.46 X-NA-AI-Is-Spam: no Content-Type: text/plain; charset="utf-8" Add device tree bindings support for the Grinn GenioSBC-700, a single-board computer based on the MediaTek Genio 700 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-700 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Acked-by: Conor Dooley Signed-off-by: Mateusz Koza Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 19ed9448c9c2..448241939a75 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -436,6 +436,7 @@ properties: - const: mediatek,mt8188 - items: - enum: + - grinn,genio-700-sbc - mediatek,mt8390-evk - const: mediatek,mt8390 - const: mediatek,mt8188 --=20 2.43.0 From nobody Wed Sep 10 01:34:23 2025 Received: from mail.grinn-global.com (mail.grinn-global.com [77.55.128.204]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D89430AD06; Mon, 8 Sep 2025 13:17:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=77.55.128.204 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757337451; cv=none; b=R0Nqj0Y201eEqNdNp3iHcImuyfW29NUKtV5lFkEJdaKh3SCALWqUc3XQn47ZfVRWrPTAyLSlUHdLa+j88RRnV3dXuMJ8ndvuKbycSKNUU9BUNhRxfSalDnaYUBbjhLrnuVxpvKEb71vVHHKPOEGiu05r3Q2iuC4QhlhMjyqXFjc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757337451; c=relaxed/simple; bh=Q1bGA4pdQZuqvG2+0h8LLkvYaRB2gK1j031dCppVCno=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J0fiO04ZJCLqOLOGonTpvxoBvUSSjeHNWiMMmE8jr3YGJlQf31eOMuyB6smMxHz2EO/EQlbmqhm9b8ANQ3BJ8jzWiHoPlhiOFrfLEGikQ8ju9NNLBQftjetFcpPZUeb/Q/C+UuZPvzi/3CRucv6mh2XjBSBF3P0HBP5zXNeXkRU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=grinn-global.com; spf=pass smtp.mailfrom=grinn-global.com; arc=none smtp.client-ip=77.55.128.204 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=grinn-global.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=grinn-global.com X-Virus-Scanned: by amavisd-new using ClamAV (9) X-Spam-Flag: NO X-Spam-Score: -1 X-Spam-Level: Received: from mateusz.int.grinn-global.com (f90-187.icpnet.pl [46.228.90.187]) by server220076.nazwa.pl (Postfix) with ESMTP id F23B61BE9F2; Mon, 08 Sep 2025 15:07:06 +0200 (CEST) From: Mateusz Koza To: angelogioacchino.delregno@collabora.com, robh@kernel.org Cc: krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, marcin.czarnecki@grinn-global.com, b.bilas@grinn-global.com, mateusz.koza@grinn-global.com, andrew@lunn.ch Subject: [PATCH v4 3/4] arm64: dts: mediatek: mt8370-grinn-genio-510-sbc: Add Grinn GenioSBC-510 Date: Mon, 8 Sep 2025 15:05:36 +0200 Message-ID: <20250908130620.2309399-4-mateusz.koza@grinn-global.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908130620.2309399-1-mateusz.koza@grinn-global.com> References: <20250908130620.2309399-1-mateusz.koza@grinn-global.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NA-AI-Spam-Probability: 0.50 X-NA-AI-Is-Spam: no Content-Type: text/plain; charset="utf-8" From: Bartosz Bilas Add support for Grinn GenioSBC-510. Based on the commit introducing support for the Grinn GenioSBC-700, this change adds support for the Grinn GenioSBC-510, a single-board computer based on the MediaTek Genio 510 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-510 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Signed-off-by: Bartosz Bilas Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../mediatek/mt8370-grinn-genio-510-sbc.dts | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc= .dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index b37a8c65e724..4b8ee6970f40 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -99,6 +99,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-genio-510-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-grinn-genio-510-sbc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-grinn-genio-700-sbc.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts b/= arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts new file mode 100644 index 000000000000..117ea694cda3 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Bartosz Bilas + */ +/dts-v1/; + +#include "mt8370.dtsi" +#include "mt8390-grinn-genio-som.dtsi" +#include "mt8390-grinn-genio-sbc.dtsi" + +/ { + model =3D "Grinn GenioSBC-510"; + compatible =3D "grinn,genio-510-sbc", "mediatek,mt8370", "mediatek,mt8188= "; + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 1 0x00000000>; + }; +}; --=20 2.43.0 From nobody Wed Sep 10 01:34:23 2025 Received: from mail.grinn-global.com (mail.grinn-global.com [77.55.128.204]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA23F30AD0B; Mon, 8 Sep 2025 13:07:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=77.55.128.204 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757336835; cv=none; b=Fey+5GUojvFkHZPiFXp9exo1ng3AXY9kFacYEWu3V6z63pfASX/PJD4YCyIrk+vLop/z1WhNlR/C4bfZo1ArX/NI0NNzJBikIWYA+jgvk8PJC94Umk2hZAJ7VrSdpIBjOxN8HOjiBgtc8kNnJiMgsTyR1f93hUXr3dGPA+sTbtk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757336835; c=relaxed/simple; bh=/FbxD6PGi8gjSZleYHn/czXQ24LedLEZERt/RTij+ho=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=K7yhfA5+zDamTMwlNvHTcdRLcBBKqoehEdKSsYoD9gTW7HsO4b26HtPrE1gav9bAmASIAalmB10TpfUGQoubQMLJkErI17r0I0nybP7J4Y9VNxOXUrscjUSSYzzXysMBItgDoOj0b6zLocV+drtzICB/kdSimJpxzxyCQOLxvog= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=grinn-global.com; spf=pass smtp.mailfrom=grinn-global.com; arc=none smtp.client-ip=77.55.128.204 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=grinn-global.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=grinn-global.com X-Virus-Scanned: by amavisd-new using ClamAV (9) X-Spam-Flag: NO X-Spam-Score: -1 X-Spam-Level: Received: from mateusz.int.grinn-global.com (f90-187.icpnet.pl [46.228.90.187]) by server220076.nazwa.pl (Postfix) with ESMTP id 451411BE92E; Mon, 08 Sep 2025 15:07:10 +0200 (CEST) From: Mateusz Koza To: angelogioacchino.delregno@collabora.com, robh@kernel.org Cc: krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, marcin.czarnecki@grinn-global.com, b.bilas@grinn-global.com, mateusz.koza@grinn-global.com, andrew@lunn.ch, Conor Dooley Subject: [PATCH v4 4/4] dt-bindings: arm: mediatek: Add grinn,genio-510-sbc Date: Mon, 8 Sep 2025 15:05:37 +0200 Message-ID: <20250908130620.2309399-5-mateusz.koza@grinn-global.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250908130620.2309399-1-mateusz.koza@grinn-global.com> References: <20250908130620.2309399-1-mateusz.koza@grinn-global.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NA-AI-Spam-Probability: 0.51 X-NA-AI-Is-Spam: no Content-Type: text/plain; charset="utf-8" Add device tree bindings support for the Grinn GenioSBC-510, a single-board computer based on the MediaTek Genio 510 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-510 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Acked-by: Conor Dooley Signed-off-by: Mateusz Koza Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 448241939a75..f04277873694 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -431,6 +431,7 @@ properties: - const: mediatek,mt8365 - items: - enum: + - grinn,genio-510-sbc - mediatek,mt8370-evk - const: mediatek,mt8370 - const: mediatek,mt8188 --=20 2.43.0