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Mon, 08 Sep 2025 05:59:47 -0700 (PDT) From: Tomer Maimon To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, avifishman70@gmail.com, tali.perry1@gmail.com, joel@jms.id.au, venture@google.com, yuenn@google.com, benjaminfair@google.com Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tomer Maimon Subject: [PATCH v2 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes Date: Mon, 8 Sep 2025 15:59:38 +0300 Message-Id: <20250908125938.3584927-3-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908125938.3584927-1-tmaimon77@gmail.com> References: <20250908125938.3584927-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable peripheral support for the Nuvoton NPCM845 Evaluation Board by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, I2C controllers, and PECI interface. Include MDIO nodes for Ethernet PHYs, reserved memory for TIP, and aliases for device access. Signed-off-by: Tomer Maimon --- .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 439 ++++++++++++++++++ 1 file changed, 439 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm= 64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts index 2638ee1c3846..145a2e599600 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts @@ -10,6 +10,42 @@ / { =20 aliases { serial0 =3D &serial0; + ethernet1 =3D &gmac1; + ethernet2 =3D &gmac2; + ethernet3 =3D &gmac3; + mdio-gpio0 =3D &mdio0; + mdio-gpio1 =3D &mdio1; + fiu0 =3D &fiu0; + fiu1 =3D &fiu3; + fiu2 =3D &fiux; + fiu3 =3D &fiu1; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + i2c7 =3D &i2c7; + i2c8 =3D &i2c8; + i2c9 =3D &i2c9; + i2c10 =3D &i2c10; + i2c11 =3D &i2c11; + i2c12 =3D &i2c12; + i2c13 =3D &i2c13; + i2c14 =3D &i2c14; + i2c15 =3D &i2c15; + i2c16 =3D &i2c16; + i2c17 =3D &i2c17; + i2c18 =3D &i2c18; + i2c19 =3D &i2c19; + i2c20 =3D &i2c20; + i2c21 =3D &i2c21; + i2c22 =3D &i2c22; + i2c23 =3D &i2c23; + i2c24 =3D &i2c24; + i2c25 =3D &i2c25; + i2c26 =3D &i2c26; }; =20 chosen { @@ -25,12 +61,415 @@ refclk: refclk-25mhz { clock-frequency =3D <25000000>; #clock-cells =3D <0>; }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + tip_reserved: tip@0 { + reg =3D <0x0 0x0 0x0 0x6200000>; + }; + }; + + mdio0: mdio-0 { + compatible =3D "virtual,mdio-gpio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + gpios =3D <&gpio1 25 GPIO_ACTIVE_HIGH>, + <&gpio1 26 GPIO_ACTIVE_HIGH>; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; + + mdio1: mdio-1 { + compatible =3D "virtual,mdio-gpio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + gpios =3D <&gpio2 27 GPIO_ACTIVE_HIGH>, + <&gpio2 28 GPIO_ACTIVE_HIGH>; + + phy1: ethernet-phy@0 { + reg =3D <0>; + }; + }; +}; + +&gmac1 { + phy-mode =3D "rgmii-id"; + snps,eee-force-disable; + status =3D "okay"; +}; + +&gmac2 { + phy-mode =3D "rmii"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&r1_pins + &r1oen_pins>; + phy-handle =3D <&phy0>; + status =3D "okay"; +}; + +&gmac3 { + phy-mode =3D "rmii"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&r2_pins + &r2oen_pins>; + phy-handle =3D <&phy1>; + status =3D "okay"; }; =20 &serial0 { status =3D "okay"; }; =20 +&fiu0 { + status =3D "okay"; + spi-nor@0 { + compatible =3D "jedec,spi-nor"; + spi-rx-bus-width =3D <1>; + reg =3D <0>; + spi-max-frequency =3D <5000000>; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + bbuboot1@0 { + label =3D "bb-uboot-1"; + reg =3D <0x0000000 0x80000>; + read-only; + }; + bbuboot2@80000 { + label =3D "bb-uboot-2"; + reg =3D <0x0080000 0x80000>; + read-only; + }; + envparam@100000 { + label =3D "env-param"; + reg =3D <0x0100000 0x40000>; + read-only; + }; + spare@140000 { + label =3D "spare"; + reg =3D <0x0140000 0xC0000>; + }; + kernel@200000 { + label =3D "kernel"; + reg =3D <0x0200000 0x400000>; + }; + rootfs@600000 { + label =3D "rootfs"; + reg =3D <0x0600000 0x700000>; + }; + spare1@D00000 { + label =3D "spare1"; + reg =3D <0x0D00000 0x200000>; + }; + spare2@F00000 { + label =3D "spare2"; + reg =3D <0x0F00000 0x200000>; + }; + spare3@1100000 { + label =3D "spare3"; + reg =3D <0x1100000 0x200000>; + }; + spare4@1300000 { + label =3D "spare4"; + reg =3D <0x1300000 0x0>; + }; + }; + }; +}; + +&fiu1 { + status =3D "okay"; + spi-nor@0 { + compatible =3D "jedec,spi-nor"; + spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <2>; + reg =3D <0>; + spi-max-frequency =3D <5000000>; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + system1@0 { + label =3D "spi1-system1"; + reg =3D <0x0 0x0>; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 =3D <&spi3_pins>, <&spi3quad_pins>; + status =3D "okay"; + spi-nor@0 { + compatible =3D "jedec,spi-nor"; + spi-rx-bus-width =3D <1>; + reg =3D <0>; + spi-max-frequency =3D <5000000>; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + system1@0 { + label =3D "spi3-system1"; + reg =3D <0x0 0x0>; + }; + }; + }; +}; + +&fiux { + spix-mode; +}; + +&sdhci { + status =3D "okay"; +}; + +&udc0 { + status =3D "okay"; +}; + +&udc1 { + status =3D "okay"; +}; + +&udc2 { + status =3D "okay"; +}; + +&udc3 { + status =3D "okay"; +}; + +&udc4 { + status =3D "okay"; +}; + +&udc5 { + status =3D "okay"; +}; + +&udc6 { + status =3D "okay"; +}; + +&udc7 { + status =3D "okay"; +}; + +&mc { + status =3D "okay"; +}; + +&peci { + status =3D "okay"; +}; + +&rng { + status =3D "okay"; +}; + +&adc { + #io-channel-cells =3D <1>; + status =3D "okay"; +}; + &watchdog1 { status =3D "okay"; }; + +&pwm_fan { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm0_pins &pwm1_pins + &pwm2_pins &pwm3_pins + &pwm4_pins &pwm5_pins + &pwm6_pins &pwm7_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins>; + #address-cells =3D <1>; + #size-cells =3D <0>; + fan@0 { + reg =3D <0x00>; + fan-tach-ch =3D /bits/ 8 <0x00 0x01>; + cooling-levels =3D <127 255>; + }; + fan@1 { + reg =3D <0x01>; + fan-tach-ch =3D /bits/ 8 <0x02 0x03>; + cooling-levels =3D <127 255>; + }; + fan@2 { + reg =3D <0x02>; + fan-tach-ch =3D /bits/ 8 <0x04 0x05>; + cooling-levels =3D <127 255>; + }; + fan@3 { + reg =3D <0x03>; + fan-tach-ch =3D /bits/ 8 <0x06 0x07>; + cooling-levels =3D <127 255>; + }; + fan@4 { + reg =3D <0x04>; + fan-tach-ch =3D /bits/ 8 <0x08 0x09>; + cooling-levels =3D <127 255>; + }; + fan@5 { + reg =3D <0x05>; + fan-tach-ch =3D /bits/ 8 <0x0A 0x0B>; + cooling-levels =3D <127 255>; + }; + fan@6 { + reg =3D <0x06>; + fan-tach-ch =3D /bits/ 8 <0x0C 0x0D>; + cooling-levels =3D <127 255>; + }; + fan@7 { + reg =3D <0x07>; + fan-tach-ch =3D /bits/ 8 <0x0E 0x0F>; + cooling-levels =3D <127 255>; + }; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + eeprom@50 { + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + }; +}; + +&i2c2 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + ipmb@10 { + compatible =3D "ipmb-dev"; + reg =3D <0x10>; + i2c-protocol; + }; +}; + +&i2c3 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + ipmb@11 { + compatible =3D "ipmb-dev"; + reg =3D <0x11>; + i2c-protocol; + }; +}; + +&i2c4 { + status =3D "okay"; +}; + +&i2c5 { + status =3D "okay"; +}; + +&i2c6 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + tmp100@48 { + compatible =3D "tmp100"; + reg =3D <0x48>; + status =3D "okay"; + }; +}; + +&i2c7 { + status =3D "okay"; +}; + +&i2c8 { + status =3D "okay"; +}; + +&i2c9 { + status =3D "okay"; +}; + +&i2c10 { + status =3D "okay"; +}; + +&i2c11 { + status =3D "okay"; +}; + +&i2c12 { + status =3D "okay"; +}; + +&i2c13 { + status =3D "okay"; +}; + +&i2c14 { + status =3D "okay"; +}; + +&i2c15 { + status =3D "okay"; +}; + +&i2c16 { + status =3D "okay"; +}; + +&i2c17 { + status =3D "okay"; +}; + +&i2c18 { + status =3D "okay"; +}; + +&i2c19 { + status =3D "okay"; +}; + +&i2c20 { + status =3D "okay"; +}; + +&i2c21 { + status =3D "okay"; +}; + +&i2c22 { + status =3D "okay"; +}; + +&i2c23 { + status =3D "okay"; +}; + +&i2c24 { + status =3D "okay"; +}; + +&i2c25 { + status =3D "okay"; +}; + +&i2c26 { + status =3D "okay"; +}; --=20 2.34.1