From nobody Wed Sep 10 05:52:53 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4DB92FABFE; Mon, 8 Sep 2025 11:48:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757332139; cv=none; b=N6IwOJTfHOkfqdjvyVjvjUXvuNr7xXrCYEYhQG8XJGyEruI6S6JC4dAJroL9HbcUbkk4HnAOqgJgwHklG2+/UzUpGRdUWoa0yK67C/QMKw7YKc6VG1N8RIcljo/OJaooI7nE9afbClkOpm94d2zfjMJqWtS8WjXDT2pJkSilFZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757332139; c=relaxed/simple; bh=fKTa6YCaaBumc82npv2gUD3y7Mci5DJDAQ4IQFBtl2k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WK2cVFUj3XkMKoPR+Vwz9IfEiKP4IRoWgxZ7zHCzmaJwFRBeNUg8vm32pBLxpSnnhjf4Jbjy259yyXdowkZp/SZIMifTJWHaBVHGqwgBuunNwhtsGXX5RdRwG0SGwuvGDk/aPFsm+QSmFx6MKfwcq52b6OHos80TnHDHSeDBrYA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=HicQmQli; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="HicQmQli" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1757332137; x=1788868137; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fKTa6YCaaBumc82npv2gUD3y7Mci5DJDAQ4IQFBtl2k=; b=HicQmQli78VDvBn0tAleLuUou3qkXf0LbHTGjnM4RXYIzxK4Yvkj1U+v 7m73cIiWicslMV/yyh/g1x2xE3pZGkg+sqo2epk3ACTbcuj7kgdk49Rx4 IL8BA5YT1Qb9mY5u/EVYAUMltgqGAo8ivlhZdzPW18qfS61wqnEQJ7KNT 9DUukP7mBW4M3AqMn0U/AW9YCW+YDzY0+izv/zw7GC3inQEvDW6t2teEn StVQCd/Ia+lov/ZZUWIhy63Rt8q8gVEVrU/bgBjA+rFvdIqRUdanZ44++ FBoENnQPuYsrs6ZFHDu8ywUjKwhNBC5XoOWWFH4jj59/iMH82al93WYK9 Q==; X-CSE-ConnectionGUID: vDOPHTnsQiaqmkXt9yltVw== X-CSE-MsgGUID: 1LiFos11Rp2I2DFuSCaZqA== X-IronPort-AV: E=Sophos;i="6.18,248,1751266800"; d="scan'208";a="45634882" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 Sep 2025 04:48:55 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 8 Sep 2025 04:48:51 -0700 Received: from valentina.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 8 Sep 2025 04:48:48 -0700 From: Valentina Fernandez To: , , , , , , , , CC: , , Subject: [PATCH v3 6/6] riscv: dts: microchip: add a device tree for Discovery Kit Date: Mon, 8 Sep 2025 12:57:32 +0100 Message-ID: <20250908115732.31092-7-valentina.fernandezalanis@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908115732.31092-1-valentina.fernandezalanis@microchip.com> References: <20250908115732.31092-1-valentina.fernandezalanis@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a minimal device tree for the Microchip PolarFire SoC Discovery Kit. The Discovery Kit is a cost-optimized board based on PolarFire SoC MPFS095T and features: - 1 GB DDR4x16 - 1x Gigabit Ethernet - 3x UARTs - Raspberry Pi connector - mikroBus connector - microSD card connector Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit Signed-off-by: Valentina Fernandez --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-disco-kit-fabric.dtsi | 58 ++++++ .../boot/dts/microchip/mpfs-disco-kit.dts | 190 ++++++++++++++++++ 3 files changed, 249 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index 1e2f4e41bf0d..345ed7a48cc1 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-beaglev-fire.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-disco-kit.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit-prod.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) +=3D mpfs-m100pfsevp.dtb diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi b/arc= h/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi new file mode 100644 index 000000000000..ae8be7d6f392 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2025 Microchip Technology Inc */ + +/ { + core_pwm0: pwm@40000000 { + compatible =3D "microchip,corepwm-rtl-v4"; + reg =3D <0x0 0x40000000 0x0 0xF0>; + microchip,sync-update-mask =3D /bits/ 32 <0>; + #pwm-cells =3D <3>; + clocks =3D <&ccc_sw CLK_CCC_PLL0_OUT3>; + status =3D "disabled"; + }; + + i2c2: i2c@40000200 { + compatible =3D "microchip,corei2c-rtl-v7"; + reg =3D <0x0 0x40000200 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&ccc_sw CLK_CCC_PLL0_OUT3>; + interrupt-parent =3D <&plic>; + interrupts =3D <122>; + clock-frequency =3D <100000>; + status =3D "disabled"; + }; + + ihc: mailbox { + compatible =3D "microchip,sbi-ipc"; + interrupt-parent =3D <&plic>; + interrupts =3D <180>, <179>, <178>, <177>; + interrupt-names =3D "hart-1", "hart-2", "hart-3", "hart-4"; + #mbox-cells =3D <1>; + status =3D "disabled"; + }; + + mailbox@50000000 { + compatible =3D "microchip,miv-ihc-rtl-v2"; + reg =3D <0x0 0x50000000 0x0 0x1c000>; + interrupt-parent =3D <&plic>; + interrupts =3D <180>, <179>, <178>, <177>; + interrupt-names =3D "hart-1", "hart-2", "hart-3", "hart-4"; + #mbox-cells =3D <1>; + microchip,ihc-chan-disabled-mask =3D /bits/ 16 <0>; + status =3D "disabled"; + }; + + refclk_ccc: clock-cccref { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; +}; + +&ccc_sw { + clocks =3D <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names =3D "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts b/arch/riscv/= boot/dts/microchip/mpfs-disco-kit.dts new file mode 100644 index 000000000000..c068b9bb5bfd --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2025 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-disco-kit-fabric.dtsi" +#include +#include + +/ { + model =3D "Microchip PolarFire-SoC Discovery Kit"; + compatible =3D "microchip,mpfs-disco-kit-reference-rtl-v2507", + "microchip,mpfs-disco-kit", + "microchip,mpfs"; + + aliases { + ethernet0 =3D &mac0; + serial4 =3D &mmuart4; + }; + + chosen { + stdout-path =3D "serial4:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-1 { + gpios =3D <&gpio2 17 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led1"; + }; + + led-2 { + gpios =3D <&gpio2 18 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led2"; + }; + + led-3 { + gpios =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led3"; + }; + + led-4 { + gpios =3D <&gpio2 20 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led4"; + }; + + led-5 { + gpios =3D <&gpio2 21 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led5"; + }; + + led-6 { + gpios =3D <&gpio2 22 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led6"; + }; + + led-7 { + gpios =3D <&gpio2 23 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led7"; + }; + + led-8 { + gpios =3D <&gpio1 9 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led8"; + }; + }; + + ddrc_cache_lo: memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hss_payload: region@bfc00000 { + reg =3D <0x0 0xbfc00000 0x0 0x400000>; + no-map; + }; + }; +}; + +&core_pwm0 { + status =3D "okay"; +}; + +&gpio1 { + interrupts =3D <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <47>, + <35>, <36>, <37>, <38>, + <39>, <40>, <41>, <42>, + <43>, <44>, <45>, <46>, + <47>, <48>, <49>, <50>; + status =3D "okay"; +}; + +&gpio2 { + interrupts =3D <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; +}; + +&ihc { + status =3D "okay"; +}; + +&mac0 { + phy-mode =3D "sgmii"; + phy-handle =3D <&phy0>; + status =3D "okay"; + + phy0: ethernet-phy@b { + reg =3D <0xb>; + }; +}; + +&mbox { + status =3D "okay"; +}; + +&mmc { + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-1-8-v; + status =3D "okay"; +}; + +&mmuart1 { + status =3D "okay"; +}; + +&mmuart4 { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&refclk_ccc { + clock-frequency =3D <50000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; + +&spi1 { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; --=20 2.34.1