From nobody Wed Sep 10 05:52:53 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CB9521B9DA; Mon, 8 Sep 2025 11:48:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757332136; cv=none; b=AbF1CFcdYS7QNQthlKDElZA3M7s+fvYf1bMwcoySL1DoFy2ZvUjtMW+BljI79+wY98gIHiOqc7WjenRjBeLkK/nAXkITACMC4Hz5P7VMxLwrxquqpRrMSA+6SiuqqAIkGCyO7QPyzKsusIgqdxRUJ6ugD/IHTijSloE5A8TIxzs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757332136; c=relaxed/simple; bh=TB1dOd76PEJ5mgVTi3H1IPzDArXUmTgjE1tKSSsdtws=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=S3/t5SnS/IW64B+qZ4tBYpMXPcrL/78CTTh/BaKiTW+0FJG8/YGgZI3JxEmiaiH4H51rz16jP3Bcja/lRPDdulCni2UV/BkbRfYe9FjNldnLemfpZCu35vUvamAEd4zEymLpv/5RA5balCWk3+uRpOtBNlBBqLi+cKaoPsi96nw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=f1oMNSY7; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="f1oMNSY7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1757332134; x=1788868134; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TB1dOd76PEJ5mgVTi3H1IPzDArXUmTgjE1tKSSsdtws=; b=f1oMNSY7HH2uZaHMtdWm40U6stBNytnNRTOEjtNIf7ZELNXxaFjJhUJI WQ4r333woY8p5NLlnW5GJ5uAhL1pKHvWtsFb4+FT2lDEPoBc8/DiiRJty gqxvueon6SdDaNZQ5JrxnmoKQGA7NlivPhPNISPnmnGJOd1PB9MHUxsvl NEHn6KDm7ksZbzR8MUskmN1iZcL4ijnJg8CRj9/8dy1PD2+6h6OL2cJ4n /EejweMqER9i/8s4StN9uxkSOm2y0iktOk5iz2dRwVudi1dWmys7KXhaJ PBS0l3RiCtFXDiyb485q769GlS0tV9xlDtrc3U1r9Z+balcMGzsDvnJde A==; X-CSE-ConnectionGUID: vDOPHTnsQiaqmkXt9yltVw== X-CSE-MsgGUID: GG+dxavVTLWTh8ASbpZspA== X-IronPort-AV: E=Sophos;i="6.18,248,1751266800"; d="scan'208";a="45634875" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 Sep 2025 04:48:52 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 8 Sep 2025 04:48:37 -0700 Received: from valentina.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 8 Sep 2025 04:48:34 -0700 From: Valentina Fernandez To: , , , , , , , , CC: , , Subject: [PATCH v3 1/6] riscv: dts: microchip: add common board dtsi for icicle kit variants Date: Mon, 8 Sep 2025 12:57:27 +0100 Message-ID: <20250908115732.31092-2-valentina.fernandezalanis@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908115732.31092-1-valentina.fernandezalanis@microchip.com> References: <20250908115732.31092-1-valentina.fernandezalanis@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for supporting the Icicle Kit with production silicon, add a common board dtsi for the icicle kit with hardware shared by both the engineering sample and production versions. Signed-off-by: Valentina Fernandez --- .../dts/microchip/mpfs-icicle-kit-common.dtsi | 247 ++++++++++++++++++ .../boot/dts/microchip/mpfs-icicle-kit.dts | 241 +---------------- 2 files changed, 248 insertions(+), 240 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dt= si diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi new file mode 100644 index 000000000000..eafea3b69cd7 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2025 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-icicle-kit-fabric.dtsi" +#include +#include + +/ { + aliases { + ethernet0 =3D &mac1; + serial0 =3D &mmuart0; + serial1 =3D &mmuart1; + serial2 =3D &mmuart2; + serial3 =3D &mmuart3; + serial4 =3D &mmuart4; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + led-1 { + gpios =3D <&gpio2 16 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led1"; + }; + + led-2 { + gpios =3D <&gpio2 17 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led2"; + }; + + led-3 { + gpios =3D <&gpio2 18 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led3"; + }; + + led-4 { + gpios =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + color =3D ; + label =3D "led4"; + }; + }; + + ddrc_cache_lo: memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x40000000>; + status =3D "okay"; + }; + + ddrc_cache_hi: memory@1040000000 { + device_type =3D "memory"; + reg =3D <0x10 0x40000000 0x0 0x40000000>; + status =3D "okay"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hss_payload: region@BFC00000 { + reg =3D <0x0 0xBFC00000 0x0 0x400000>; + no-map; + }; + }; +}; + +&core_pwm0 { + status =3D "okay"; +}; + +&gpio2 { + interrupts =3D <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; + + power-monitor@10 { + compatible =3D "microchip,pac1934"; + reg =3D <0x10>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@1 { + reg =3D <0x1>; + shunt-resistor-micro-ohms =3D <10000>; + label =3D "VDDREG"; + }; + + channel@2 { + reg =3D <0x2>; + shunt-resistor-micro-ohms =3D <10000>; + label =3D "VDDA25"; + }; + + channel@3 { + reg =3D <0x3>; + shunt-resistor-micro-ohms =3D <10000>; + label =3D "VDD25"; + }; + + channel@4 { + reg =3D <0x4>; + shunt-resistor-micro-ohms =3D <10000>; + label =3D "VDDA_REG"; + }; + }; +}; + +&i2c2 { + status =3D "okay"; +}; + +&mac0 { + phy-mode =3D "sgmii"; + phy-handle =3D <&phy0>; + status =3D "okay"; +}; + +&mac1 { + phy-mode =3D "sgmii"; + phy-handle =3D <&phy1>; + status =3D "okay"; + + phy1: ethernet-phy@9 { + reg =3D <9>; + }; + + phy0: ethernet-phy@8 { + reg =3D <8>; + }; +}; + +&mbox { + status =3D "okay"; +}; + +&mmc { + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status =3D "okay"; +}; + +&mmuart1 { + status =3D "okay"; +}; + +&mmuart2 { + status =3D "okay"; +}; + +&mmuart3 { + status =3D "okay"; +}; + +&mmuart4 { + status =3D "okay"; +}; + +&pcie { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&refclk_ccc { + clock-frequency =3D <50000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; + +&spi1 { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; + +&syscontroller_qspi { + /* + * The flash *is* there, but Icicle kits that have engineering sample + * silicon (write?) access to this flash to non-functional. The system + * controller itself can actually access it, but the MSS cannot write + * an image there. Instantiating a coreQSPI in the fabric & connecting + * it to the flash instead should work though. Pre-production or later + * silicon does not have this issue. + */ + status =3D "disabled"; + + sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT + compatible =3D "jedec,spi-nor"; + #address-cells =3D <1>; + #size-cells =3D <1>; + spi-max-frequency =3D <20000000>; + spi-rx-bus-width =3D <1>; + reg =3D <0>; + }; +}; + +&usb { + status =3D "okay"; + dr_mode =3D "host"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index f80df225f72b..2cb08ed0946d 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -3,249 +3,10 @@ =20 /dts-v1/; =20 -#include "mpfs.dtsi" -#include "mpfs-icicle-kit-fabric.dtsi" -#include -#include +#include "mpfs-icicle-kit-common.dtsi" =20 / { model =3D "Microchip PolarFire-SoC Icicle Kit"; compatible =3D "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpf= s-icicle-kit", "microchip,mpfs"; - - aliases { - ethernet0 =3D &mac1; - serial0 =3D &mmuart0; - serial1 =3D &mmuart1; - serial2 =3D &mmuart2; - serial3 =3D &mmuart3; - serial4 =3D &mmuart4; - }; - - chosen { - stdout-path =3D "serial1:115200n8"; - }; - - leds { - compatible =3D "gpio-leds"; - - led-1 { - gpios =3D <&gpio2 16 GPIO_ACTIVE_HIGH>; - color =3D ; - label =3D "led1"; - }; - - led-2 { - gpios =3D <&gpio2 17 GPIO_ACTIVE_HIGH>; - color =3D ; - label =3D "led2"; - }; - - led-3 { - gpios =3D <&gpio2 18 GPIO_ACTIVE_HIGH>; - color =3D ; - label =3D "led3"; - }; - - led-4 { - gpios =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; - color =3D ; - label =3D "led4"; - }; - }; - - ddrc_cache_lo: memory@80000000 { - device_type =3D "memory"; - reg =3D <0x0 0x80000000 0x0 0x40000000>; - status =3D "okay"; - }; - - ddrc_cache_hi: memory@1040000000 { - device_type =3D "memory"; - reg =3D <0x10 0x40000000 0x0 0x40000000>; - status =3D "okay"; - }; - - reserved-memory { - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges; - - hss_payload: region@BFC00000 { - reg =3D <0x0 0xBFC00000 0x0 0x400000>; - no-map; - }; - }; -}; - -&core_pwm0 { - status =3D "okay"; -}; - -&gpio2 { - interrupts =3D <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; - status =3D "okay"; -}; - -&i2c0 { - status =3D "okay"; -}; - -&i2c1 { - status =3D "okay"; - - power-monitor@10 { - compatible =3D "microchip,pac1934"; - reg =3D <0x10>; - - #address-cells =3D <1>; - #size-cells =3D <0>; - - channel@1 { - reg =3D <0x1>; - shunt-resistor-micro-ohms =3D <10000>; - label =3D "VDDREG"; - }; - - channel@2 { - reg =3D <0x2>; - shunt-resistor-micro-ohms =3D <10000>; - label =3D "VDDA25"; - }; - - channel@3 { - reg =3D <0x3>; - shunt-resistor-micro-ohms =3D <10000>; - label =3D "VDD25"; - }; - - channel@4 { - reg =3D <0x4>; - shunt-resistor-micro-ohms =3D <10000>; - label =3D "VDDA_REG"; - }; - }; -}; - -&i2c2 { - status =3D "okay"; -}; - -&mac0 { - phy-mode =3D "sgmii"; - phy-handle =3D <&phy0>; - status =3D "okay"; -}; - -&mac1 { - phy-mode =3D "sgmii"; - phy-handle =3D <&phy1>; - status =3D "okay"; - - phy1: ethernet-phy@9 { - reg =3D <9>; - }; - - phy0: ethernet-phy@8 { - reg =3D <8>; - }; -}; - -&mbox { - status =3D "okay"; -}; - -&mmc { - bus-width =3D <4>; - disable-wp; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - status =3D "okay"; -}; - -&mmuart1 { - status =3D "okay"; -}; - -&mmuart2 { - status =3D "okay"; -}; - -&mmuart3 { - status =3D "okay"; -}; - -&mmuart4 { - status =3D "okay"; -}; - -&pcie { - status =3D "okay"; -}; - -&qspi { - status =3D "okay"; -}; - -&refclk { - clock-frequency =3D <125000000>; -}; - -&refclk_ccc { - clock-frequency =3D <50000000>; -}; - -&rtc { - status =3D "okay"; -}; - -&spi0 { - status =3D "okay"; -}; - -&spi1 { - status =3D "okay"; -}; - -&syscontroller { - status =3D "okay"; -}; - -&syscontroller_qspi { - /* - * The flash *is* there, but Icicle kits that have engineering sample - * silicon (write?) access to this flash to non-functional. The system - * controller itself can actually access it, but the MSS cannot write - * an image there. Instantiating a coreQSPI in the fabric & connecting - * it to the flash instead should work though. Pre-production or later - * silicon does not have this issue. - */ - status =3D "disabled"; - - sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT - compatible =3D "jedec,spi-nor"; - #address-cells =3D <1>; - #size-cells =3D <1>; - spi-max-frequency =3D <20000000>; - spi-rx-bus-width =3D <1>; - reg =3D <0>; - }; -}; - -&usb { - status =3D "okay"; - dr_mode =3D "host"; }; --=20 2.34.1