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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 11:57:29.3040 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70cad212-c978-468c-b470-08ddeecee2ed X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5905 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move `bitfield.h` from the CDX controller directory to `include/linux/cdx` to make them accessible to other drivers. As part of this refactoring, `mcdi.h` has been split into two headers: - `mcdi.h`: retains interface-level declarations - `mcdid.h`: contains internal definitions and macros This is in preparation for VersalNET EDAC driver that relies on it. Signed-off-by: Shubhrajyoti Datta --- Changes in v8: - Split `mcdi.h` into `mcdi.h` and `mcdid.h` - Removed common code from CDX headers - Used refactored versions from shared location Changes in v7: - add a minimal header instead moving them Changes in v6: - Patch added drivers/cdx/controller/cdx_controller.c | 2 +- drivers/cdx/controller/cdx_rpmsg.c | 2 +- drivers/cdx/controller/mcdi.c | 5 +- drivers/cdx/controller/mcdi_functions.c | 1 - drivers/cdx/controller/mcdi_functions.h | 3 +- drivers/cdx/controller/mcdid.h | 63 +++++++++++++++++++ .../linux/cdx}/bitfield.h | 0 .../controller =3D> include/linux/cdx}/mcdi.h | 52 +-------------- 8 files changed, 71 insertions(+), 57 deletions(-) create mode 100644 drivers/cdx/controller/mcdid.h rename {drivers/cdx/controller =3D> include/linux/cdx}/bitfield.h (100%) rename {drivers/cdx/controller =3D> include/linux/cdx}/mcdi.h (74%) diff --git a/drivers/cdx/controller/cdx_controller.c b/drivers/cdx/controll= er/cdx_controller.c index 5e3fd89b6b56..280f207735da 100644 --- a/drivers/cdx/controller/cdx_controller.c +++ b/drivers/cdx/controller/cdx_controller.c @@ -14,7 +14,7 @@ #include "cdx_controller.h" #include "../cdx.h" #include "mcdi_functions.h" -#include "mcdi.h" +#include "mcdid.h" =20 static unsigned int cdx_mcdi_rpc_timeout(struct cdx_mcdi *cdx, unsigned in= t cmd) { diff --git a/drivers/cdx/controller/cdx_rpmsg.c b/drivers/cdx/controller/cd= x_rpmsg.c index 61f1a290ff08..59aabd99fa8f 100644 --- a/drivers/cdx/controller/cdx_rpmsg.c +++ b/drivers/cdx/controller/cdx_rpmsg.c @@ -15,7 +15,7 @@ #include "../cdx.h" #include "cdx_controller.h" #include "mcdi_functions.h" -#include "mcdi.h" +#include "mcdid.h" =20 static struct rpmsg_device_id cdx_rpmsg_id_table[] =3D { { .name =3D "mcdi_ipc" }, diff --git a/drivers/cdx/controller/mcdi.c b/drivers/cdx/controller/mcdi.c index e760f8d347cc..90bf9f7c257b 100644 --- a/drivers/cdx/controller/mcdi.c +++ b/drivers/cdx/controller/mcdi.c @@ -23,9 +23,10 @@ #include #include #include +#include =20 -#include "bitfield.h" -#include "mcdi.h" +#include +#include "mcdid.h" =20 static void cdx_mcdi_cancel_cmd(struct cdx_mcdi *cdx, struct cdx_mcdi_cmd = *cmd); static void cdx_mcdi_wait_for_cleanup(struct cdx_mcdi *cdx); diff --git a/drivers/cdx/controller/mcdi_functions.c b/drivers/cdx/controll= er/mcdi_functions.c index 885c69e6ebe5..8ae2d99be81e 100644 --- a/drivers/cdx/controller/mcdi_functions.c +++ b/drivers/cdx/controller/mcdi_functions.c @@ -5,7 +5,6 @@ =20 #include =20 -#include "mcdi.h" #include "mcdi_functions.h" =20 int cdx_mcdi_get_num_buses(struct cdx_mcdi *cdx) diff --git a/drivers/cdx/controller/mcdi_functions.h b/drivers/cdx/controll= er/mcdi_functions.h index b9942affdc6b..57fd1bae706b 100644 --- a/drivers/cdx/controller/mcdi_functions.h +++ b/drivers/cdx/controller/mcdi_functions.h @@ -8,7 +8,8 @@ #ifndef CDX_MCDI_FUNCTIONS_H #define CDX_MCDI_FUNCTIONS_H =20 -#include "mcdi.h" +#include +#include "mcdid.h" #include "../cdx.h" =20 /** diff --git a/drivers/cdx/controller/mcdid.h b/drivers/cdx/controller/mcdid.h new file mode 100644 index 000000000000..7fc29f099265 --- /dev/null +++ b/drivers/cdx/controller/mcdid.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2008-2013 Solarflare Communications Inc. + * Copyright (C) 2022-2025, Advanced Micro Devices, Inc. + */ + +#ifndef CDX_MCDID_H +#define CDX_MCDID_H + +#include +#include +#include + +#include "mc_cdx_pcol.h" + +#ifdef DEBUG +#define CDX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x) +#define CDX_WARN_ON_PARANOID(x) WARN_ON(x) +#else +#define CDX_WARN_ON_ONCE_PARANOID(x) do {} while (0) +#define CDX_WARN_ON_PARANOID(x) do {} while (0) +#endif + +#define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX) + +static inline struct cdx_mcdi_iface *cdx_mcdi_if(struct cdx_mcdi *cdx) +{ + return cdx->mcdi ? &cdx->mcdi->iface : NULL; +} + +int cdx_mcdi_rpc_async(struct cdx_mcdi *cdx, unsigned int cmd, + const struct cdx_dword *inbuf, size_t inlen, + cdx_mcdi_async_completer *complete, + unsigned long cookie); +int cdx_mcdi_wait_for_quiescence(struct cdx_mcdi *cdx, + unsigned int timeout_jiffies); + +/* + * We expect that 16- and 32-bit fields in MCDI requests and responses + * are appropriately aligned, but 64-bit fields are only + * 32-bit-aligned. + */ +#define MCDI_BYTE(_buf, _field) \ + ((void)BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN !=3D 1), \ + *MCDI_PTR(_buf, _field)) +#define MCDI_WORD(_buf, _field) \ + ((void)BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN !=3D 2), \ + le16_to_cpu(*(__force const __le16 *)MCDI_PTR(_buf, _field))) +#define MCDI_POPULATE_DWORD_1(_buf, _field, _name1, _value1) \ + CDX_POPULATE_DWORD_1(*_MCDI_DWORD(_buf, _field), \ + MC_CMD_ ## _name1, _value1) +#define MCDI_SET_QWORD(_buf, _field, _value) \ + do { \ + CDX_POPULATE_DWORD_1(_MCDI_DWORD(_buf, _field)[0], \ + CDX_DWORD, (u32)(_value)); \ + CDX_POPULATE_DWORD_1(_MCDI_DWORD(_buf, _field)[1], \ + CDX_DWORD, (u64)(_value) >> 32); \ + } while (0) +#define MCDI_QWORD(_buf, _field) \ + (CDX_DWORD_FIELD(_MCDI_DWORD(_buf, _field)[0], CDX_DWORD) | \ + (u64)CDX_DWORD_FIELD(_MCDI_DWORD(_buf, _field)[1], CDX_DWORD) << 32) + +#endif /* CDX_MCDID_H */ diff --git a/drivers/cdx/controller/bitfield.h b/include/linux/cdx/bitfield= .h similarity index 100% rename from drivers/cdx/controller/bitfield.h rename to include/linux/cdx/bitfield.h diff --git a/drivers/cdx/controller/mcdi.h b/include/linux/cdx/mcdi.h similarity index 74% rename from drivers/cdx/controller/mcdi.h rename to include/linux/cdx/mcdi.h index 54a65e9760ae..46e3f63b062a 100644 --- a/drivers/cdx/controller/mcdi.h +++ b/include/linux/cdx/mcdi.h @@ -11,16 +11,7 @@ #include #include =20 -#include "bitfield.h" -#include "mc_cdx_pcol.h" - -#ifdef DEBUG -#define CDX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x) -#define CDX_WARN_ON_PARANOID(x) WARN_ON(x) -#else -#define CDX_WARN_ON_ONCE_PARANOID(x) do {} while (0) -#define CDX_WARN_ON_PARANOID(x) do {} while (0) -#endif +#include "linux/cdx/bitfield.h" =20 /** * enum cdx_mcdi_mode - MCDI transaction mode @@ -36,8 +27,6 @@ enum cdx_mcdi_mode { #define MCDI_RPC_LONG_TIMEOU (60 * HZ) #define MCDI_RPC_POST_RST_TIME (10 * HZ) =20 -#define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX) - /** * enum cdx_mcdi_cmd_state - State for an individual MCDI command * @MCDI_STATE_QUEUED: Command not started and is waiting to run. @@ -180,25 +169,6 @@ struct cdx_mcdi_data { u32 fn_flags; }; =20 -static inline struct cdx_mcdi_iface *cdx_mcdi_if(struct cdx_mcdi *cdx) -{ - return cdx->mcdi ? &cdx->mcdi->iface : NULL; -} - -int cdx_mcdi_init(struct cdx_mcdi *cdx); -void cdx_mcdi_finish(struct cdx_mcdi *cdx); - -void cdx_mcdi_process_cmd(struct cdx_mcdi *cdx, struct cdx_dword *outbuf, = int len); -int cdx_mcdi_rpc(struct cdx_mcdi *cdx, unsigned int cmd, - const struct cdx_dword *inbuf, size_t inlen, - struct cdx_dword *outbuf, size_t outlen, size_t *outlen_actual); -int cdx_mcdi_rpc_async(struct cdx_mcdi *cdx, unsigned int cmd, - const struct cdx_dword *inbuf, size_t inlen, - cdx_mcdi_async_completer *complete, - unsigned long cookie); -int cdx_mcdi_wait_for_quiescence(struct cdx_mcdi *cdx, - unsigned int timeout_jiffies); - /* * We expect that 16- and 32-bit fields in MCDI requests and responses * are appropriately aligned, but 64-bit fields are only @@ -215,28 +185,8 @@ int cdx_mcdi_wait_for_quiescence(struct cdx_mcdi *cdx, #define _MCDI_DWORD(_buf, _field) \ ((_buf) + (_MCDI_CHECK_ALIGN(MC_CMD_ ## _field ## _OFST, 4) >> 2)) =20 -#define MCDI_BYTE(_buf, _field) \ - ((void)BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN !=3D 1), \ - *MCDI_PTR(_buf, _field)) -#define MCDI_WORD(_buf, _field) \ - ((void)BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN !=3D 2), \ - le16_to_cpu(*(__force const __le16 *)MCDI_PTR(_buf, _field))) #define MCDI_SET_DWORD(_buf, _field, _value) \ CDX_POPULATE_DWORD_1(*_MCDI_DWORD(_buf, _field), CDX_DWORD, _value) #define MCDI_DWORD(_buf, _field) \ CDX_DWORD_FIELD(*_MCDI_DWORD(_buf, _field), CDX_DWORD) -#define MCDI_POPULATE_DWORD_1(_buf, _field, _name1, _value1) \ - CDX_POPULATE_DWORD_1(*_MCDI_DWORD(_buf, _field), \ - MC_CMD_ ## _name1, _value1) -#define MCDI_SET_QWORD(_buf, _field, _value) \ - do { \ - CDX_POPULATE_DWORD_1(_MCDI_DWORD(_buf, _field)[0], \ - CDX_DWORD, (u32)(_value)); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 11:57:14.5111 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73343d12-65cb-4c30-624b-08ddeeceda14 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D6.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9712 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cdx_mcdi_init, cdx_mcdi_process_cmd, and cdx_mcdi_rpc functions are needed by VersalNET EDAC modules that interact with the MCDI (Management Controller Direct Interface) framework. These functions facilitate communication between different hardware components by enabling command execution and status management. Signed-off-by: Shubhrajyoti Datta --- Changes in v9: - Add tabs - Replace "This function allocates" to Allocate similarly s/This function handles/Handle/ - Export cdx_mcdi_finish Changes in v7: - Add the kernel doc description - Add the prototype from first patch to here Changes in v6: - Update commit description Changes in v2: - Export the symbols for module compilation drivers/cdx/controller/mcdi.c | 38 +++++++++++++++++++++++++++++++++++ include/linux/cdx/mcdi.h | 7 +++++++ 2 files changed, 45 insertions(+) diff --git a/drivers/cdx/controller/mcdi.c b/drivers/cdx/controller/mcdi.c index 90bf9f7c257b..2e82ffc18d89 100644 --- a/drivers/cdx/controller/mcdi.c +++ b/drivers/cdx/controller/mcdi.c @@ -100,6 +100,19 @@ static unsigned long cdx_mcdi_rpc_timeout(struct cdx_m= cdi *cdx, unsigned int cmd return cdx->mcdi_ops->mcdi_rpc_timeout(cdx, cmd); } =20 +/** + * cdx_mcdi_init - Initialize MCDI (Management Controller Driver Interface= ) state + * @cdx: Handle to the CDX MCDI structure + * + * This function allocates and initializes internal MCDI structures and re= sources + * for the CDX device, including the workqueue, locking primitives, and co= mmand + * tracking mechanisms. It sets the initial operating mode and prepares th= e device + * for MCDI operations. + * + * Return: + * * 0 - on success + * * -ENOMEM - if memory allocation or workqueue creation fails + */ int cdx_mcdi_init(struct cdx_mcdi *cdx) { struct cdx_mcdi_iface *mcdi; @@ -129,7 +142,16 @@ int cdx_mcdi_init(struct cdx_mcdi *cdx) fail: return rc; } +EXPORT_SYMBOL_GPL(cdx_mcdi_init); =20 +/** + * cdx_mcdi_finish - Cleanup MCDI (Management Controller Driver Interface)= state + * @cdx: Handle to the CDX MCDI structure + * + * This function is responsible for cleaning up the MCDI (Management Contr= oller Driver Interface) + * resources associated with a cdx_mcdi structure. Also destroys the mcdi = workqueue. + * + */ void cdx_mcdi_finish(struct cdx_mcdi *cdx) { struct cdx_mcdi_iface *mcdi; @@ -144,6 +166,7 @@ void cdx_mcdi_finish(struct cdx_mcdi *cdx) kfree(cdx->mcdi); cdx->mcdi =3D NULL; } +EXPORT_SYMBOL_GPL(cdx_mcdi_finish); =20 static bool cdx_mcdi_flushed(struct cdx_mcdi_iface *mcdi, bool ignore_clea= nups) { @@ -554,6 +577,19 @@ static void cdx_mcdi_start_or_queue(struct cdx_mcdi_if= ace *mcdi, cdx_mcdi_cmd_start_or_queue(mcdi, cmd); } =20 +/** + * cdx_mcdi_process_cmd - Process an incoming MCDI response + * @cdx: Handle to the CDX MCDI structure + * @outbuf: Pointer to the response buffer received from the management co= ntroller + * @len: Length of the response buffer in bytes + * + * This function handles a response from the management controller. It loc= ates the + * corresponding command using the sequence number embedded in the header, + * completes the command if it is still pending, and initiates any necessa= ry cleanup. + * + * The function assumes that the response buffer is well-formed and at lea= st one + * dword in size. + */ void cdx_mcdi_process_cmd(struct cdx_mcdi *cdx, struct cdx_dword *outbuf, = int len) { struct cdx_mcdi_iface *mcdi; @@ -591,6 +627,7 @@ void cdx_mcdi_process_cmd(struct cdx_mcdi *cdx, struct = cdx_dword *outbuf, int le =20 cdx_mcdi_process_cleanup_list(mcdi->cdx, &cleanup_list); } +EXPORT_SYMBOL_GPL(cdx_mcdi_process_cmd); =20 static void cdx_mcdi_cmd_work(struct work_struct *context) { @@ -758,6 +795,7 @@ int cdx_mcdi_rpc(struct cdx_mcdi *cdx, unsigned int cmd, return cdx_mcdi_rpc_sync(cdx, cmd, inbuf, inlen, outbuf, outlen, outlen_actual, false); } +EXPORT_SYMBOL_GPL(cdx_mcdi_rpc); =20 /** * cdx_mcdi_rpc_async - Schedule an MCDI command to run asynchronously diff --git a/include/linux/cdx/mcdi.h b/include/linux/cdx/mcdi.h index 46e3f63b062a..74075305cba4 100644 --- a/include/linux/cdx/mcdi.h +++ b/include/linux/cdx/mcdi.h @@ -169,6 +169,13 @@ struct cdx_mcdi_data { u32 fn_flags; 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Mon, 8 Sep 2025 04:57:09 -0700 From: Shubhrajyoti Datta To: , , CC: , , , , Shubhrajyoti Datta , Krzysztof Kozlowski , "Rob Herring" , Conor Dooley , "Borislav Petkov" , Tony Luck , James Morse , Mauro Carvalho Chehab , "Robert Richter" , Nipun Gupta , Nikhil Agarwal Subject: [PATCH v9 3/5] ras: Export log_non_standard_event for External Usage Date: Mon, 8 Sep 2025 17:26:47 +0530 Message-ID: <20250908115649.22903-4-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250908115649.22903-1-shubhrajyoti.datta@amd.com> References: <20250908115649.22903-1-shubhrajyoti.datta@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E4:EE_|DS0PR12MB7876:EE_ X-MS-Office365-Filtering-Correlation-Id: 3a7a2604-dfec-42bb-bb75-08ddeecee61a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 11:57:34.6322 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a7a2604-dfec-42bb-bb75-08ddeecee61a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7876 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The function log_non_standard_event is responsible for logging platform-specific or vendor-defined RAS (Reliability, Availability, and Serviceability) events. Currently, this function is only available within the RAS subsystem, preventing external modules from leveraging its capabilities. Export log_non_standard_event to enable external drivers to log non-standard RAS events via EDAC. Signed-off-by: Shubhrajyoti Datta --- Changes in v9: Change the export log_non_standard_event wording Changes in v6: - Update the commit message. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 11:57:35.4447 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1438728-bb31-4804-9132-08ddeecee696 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6611 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for AMD Versal NET EDAC for DDR controller. Signed-off-by: Shubhrajyoti Datta Reviewed-by: Krzysztof Kozlowski --- (no changes since v7) Changes in v7: - Add the reviewed by tag Changes in v6: - update to the chip name as xlnx,versal-net - Correct indentation Changes in v5: - Update the binding Changes in v4: - Update the compatible - align the example - Enhance the description for rproc Changes in v2: - rename EDAC to memory controller - update the compatible name - Add remote proc handle - Read the data width from the registers - Remove the dwidth, rank and channel number the same is read from the RpMsg. .../xlnx,versal-net-ddrmc5.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xl= nx,versal-net-ddrmc5.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,vers= al-net-ddrmc5.yaml b/Documentation/devicetree/bindings/memory-controllers/x= lnx,versal-net-ddrmc5.yaml new file mode 100644 index 000000000000..479288567d0b --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-= ddrmc5.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-net-ddrm= c5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal NET Memory Controller + +maintainers: + - Shubhrajyoti Datta + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPD= DR5 + compact and extended memory interfaces. Versal NET DDR memory controller + has an optional ECC support which correct single bit ECC errors and dete= ct + double bit ECC errors. It also has support for reporting other errors li= ke + MMCM (Mixed-Mode Clock Manager) errors and General software errors. + +properties: + compatible: + const: xlnx,versal-net-ddrmc5 + + amd,rproc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the remoteproc_r5 rproc node using which APU interacts + with remote processor. APU primarily communicates with the RPU for + accessing the DDRMC address space and getting error notification. + +required: + - compatible + - amd,rproc + +additionalProperties: false + +examples: + - | + memory-controller { + compatible =3D "xlnx,versal-net-ddrmc5"; + amd,rproc =3D <&remoteproc_r5>; + }; --=20 2.34.1 From nobody Wed Sep 10 02:03:15 2025 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2066.outbound.protection.outlook.com [40.107.220.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E7401D5150; Mon, 8 Sep 2025 11:57:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.66 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757332658; cv=fail; b=dMwu7lSO6zMe9dGnh5TFSN4DfI1m3XZ3HE/V6nKzkZppmQa0AMkX2NLEcj2g6Lo+XroOEz6PNsnD/MbqsK9xVOULEV4/tCfqPBsPE9+6DlGLByNAP+cfC+pqvxfOmEKHXjZtefWdEwsviN0/26G19+T+V542OekOcbDRw/wfEfc= ARC-Message-Signature: i=2; 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Mon, 8 Sep 2025 04:57:21 -0700 From: Shubhrajyoti Datta To: , , CC: , , , , Shubhrajyoti Datta , Krzysztof Kozlowski , "Rob Herring" , Conor Dooley , "Borislav Petkov" , Tony Luck , James Morse , Mauro Carvalho Chehab , "Robert Richter" , Nipun Gupta , Nikhil Agarwal Subject: [PATCH v9 5/5] EDAC: Add a driver for the AMD Versal NET DDR controller Date: Mon, 8 Sep 2025 17:26:49 +0530 Message-ID: <20250908115649.22903-6-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250908115649.22903-1-shubhrajyoti.datta@amd.com> References: <20250908115649.22903-1-shubhrajyoti.datta@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AD:EE_|SJ2PR12MB8009:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f46e369-5334-4c5d-7f3d-08ddeecee260 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|7416014|36860700013|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 11:57:28.3778 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f46e369-5334-4c5d-7f3d-08ddeecee260 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8009 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a driver for the AMD Versal NET DDR memory controller which supports single bit error correction, double bit error detection and other system errors from various IP subsystems (e.g., RPU, NOCs, HNICX, PL). The driver listens for notifications from the NMC (Network management controller) using RPMsg (Remote Processor Messaging). The channel used for communicating to RPMsg is named "error_edac". Upon receipt of a notification, the driver sends a RAS event trace. [ bp: - Fixup title - Rewrite commit message - Fixup Kconfig text - Zap unused defines and align them - Simplify rpmsg_cb() considerably - Drop silly double-brackets in conditionals - Use proper void * type in mcdi_request() - Do not clear chinfo in rpmsg_probe() unnecessarily - Fix indentation - Do a proper err unwind path in init_versalnet() - Redo the error unwind path in mc_probe() properly - Fix the ordering in mc_remove() ] Signed-off-by: Shubhrajyoti Datta Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20250703173105.GLaGa-WQCESDNsqygm@fat_crate= .local --- Changes in v9: - Fixup title - Rewrite commit message - Fixup Kconfig text - Zap unused defines and align them - Simplify rpmsg_cb() considerably - Drop silly double-brackets in conditionals - Use proper void * type in mcdi_request() - Do not clear chinfo in rpmsg_probe() unnecessarily - Fix indentation - Do a proper err unwind path in init_versalnet() - Redo the error unwind path in mc_probe() properly - Fix the ordering in mc_remove() - call cdx_mcdi_finish Changes in v8: - Remove "EDAC" from macros and shoterned them - Removed redundant parentheses - Improved the description of the @i field in union ecc_error_info - Improved logging for memory_failure() - Merged init_csrows() into mc_init(): - Remove AMD-specific naming for static functions - Add MAINTAINERS file - Register all the controllers - Replace AMD_ERR use the snprintf in a function Changes in v7: - Update the header paths - merge edac_cdx_pcol.h Changes in v6: - Update to xlnx,versal-net-ddrmc5 - Update the kconfig message - Make the messages uniform - Add some more supported events - rename regval to reglo - combine/ reformat functions - remove trailing comments - Remove unneeded comments - make the amd_mcdi function void - rename versalnet_rpmsg_edac to versalnet_edac - Remove the column bit and use them directly - Update the comments - Update the mod_name to versalnet_edac - remove the global priv col and rows - rename edac_priv to mc_priv - Update the comment description for dwidth - Remove error_id enum - rename the variable par to parity - make get_ddr_config void - Fix memory leak of the mcdi structure - Update the spelling - Remove the workqueue Changes in v5: - Update the compatible - Update the handle_error documentation Changes in v4: - Update the compatible Changes in v3: - make remove void Changes in v2: - remove reset - Add the remote proc requests - remove probe_once - reorder the rpmsg registration - the data width , rank and number of channel is read from message. MAINTAINERS | 7 + drivers/edac/Kconfig | 8 + drivers/edac/Makefile | 1 + drivers/edac/versalnet_edac.c | 958 ++++++++++++++++++++++++++++++ include/linux/cdx/edac_cdx_pcol.h | 28 + 5 files changed, 1002 insertions(+) create mode 100644 drivers/edac/versalnet_edac.c create mode 100644 include/linux/cdx/edac_cdx_pcol.h diff --git a/MAINTAINERS b/MAINTAINERS index 77782f2e33b4..d51372cdf43e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27789,6 +27789,13 @@ S: Maintained F: Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-= edac.yaml F: drivers/edac/versal_edac.c =20 +XILINX VERSALNET EDAC DRIVER +M: Shubhrajyoti Datta +S: Maintained +F: Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-dd= rmc5.yaml +F: drivers/edac/versalnet_edac.c +F: include/linux/cdx/edac_cdx_pcol.h + XILINX WATCHDOG DRIVER M: Srinivas Neeli R: Shubhrajyoti Datta diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index b824472208c4..39352b9b7a7e 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -584,4 +584,12 @@ config EDAC_CORTEX_A72 The detected and reported errors are from reading CPU/L2 memory error syndrome registers. =20 +config EDAC_VERSALNET + tristate "AMD VersalNET DDR Controller" + depends on CDX_CONTROLLER && ARCH_ZYNQMP + help + Support for single bit error correction, double bit error detection + and other system errors from various IP subsystems like RPU, NOCs, + HNICX, PL on the AMD Versal NET DDR memory controller. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index c1736f264320..1c14796410a3 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -88,4 +88,5 @@ obj-$(CONFIG_EDAC_NPCM) +=3D npcm_edac.o obj-$(CONFIG_EDAC_ZYNQMP) +=3D zynqmp_edac.o obj-$(CONFIG_EDAC_VERSAL) +=3D versal_edac.o obj-$(CONFIG_EDAC_LOONGSON) +=3D loongson_edac.o +obj-$(CONFIG_EDAC_VERSALNET) +=3D versalnet_edac.o obj-$(CONFIG_EDAC_CORTEX_A72) +=3D a72_edac.o diff --git a/drivers/edac/versalnet_edac.c b/drivers/edac/versalnet_edac.c new file mode 100644 index 000000000000..66714fffa591 --- /dev/null +++ b/drivers/edac/versalnet_edac.c @@ -0,0 +1,958 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Versal NET memory controller driver + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "edac_module.h" + +/* Granularity of reported error in bytes */ +#define MC5_ERR_GRAIN 1 +#define MC_GET_DDR_CONFIG_IN_LEN 4 + +#define MC5_IRQ_CE_MASK GENMASK(18, 15) +#define MC5_IRQ_UE_MASK GENMASK(14, 11) + +#define MC5_RANK_1_MASK GENMASK(11, 6) +#define MASK_24 GENMASK(29, 24) +#define MASK_0 GENMASK(5, 0) + +#define MC5_LRANK_1_MASK GENMASK(11, 6) +#define MC5_LRANK_2_MASK GENMASK(17, 12) +#define MC5_BANK1_MASK GENMASK(11, 6) +#define MC5_GRP_0_MASK GENMASK(17, 12) +#define MC5_GRP_1_MASK GENMASK(23, 18) + +#define MC5_REGHI_ROW 7 +#define MC5_EACHBIT 1 +#define MC5_ERR_TYPE_CE 0 +#define MC5_ERR_TYPE_UE 1 +#define MC5_HIGH_MEM_EN BIT(20) +#define MC5_MEM_MASK GENMASK(19, 0) +#define MC5_X16_BASE 256 +#define MC5_X16_ECC 32 +#define MC5_X16_SIZE (MC5_X16_BASE + MC5_X16_ECC) +#define MC5_X32_SIZE 576 +#define MC5_HIMEM_BASE (256 * SZ_1M) +#define MC5_ILC_HIMEM_EN BIT(28) +#define MC5_ILC_MEM GENMASK(27, 0) +#define MC5_INTERLEAVE_SEL GENMASK(3, 0) +#define MC5_BUS_WIDTH_MASK GENMASK(19, 18) +#define MC5_NUM_CHANS_MASK BIT(17) +#define MC5_RANK_MASK GENMASK(15, 14) + +#define ERROR_LEVEL 2 +#define ERROR_ID 3 +#define TOTAL_ERR_LENGTH 5 +#define MSG_ERR_OFFSET 8 +#define MSG_ERR_LENGTH 9 +#define ERROR_DATA 10 +#define MCDI_RESPONSE 0xFF + +#define REG_MAX 152 +#define ADEC_MAX 152 +#define NUM_CONTROLLERS 8 +#define REGS_PER_CONTROLLER 19 +#define ADEC_NUM 19 +#define BUFFER_SZ 80 + +#define XDDR5_BUS_WIDTH_64 0 +#define XDDR5_BUS_WIDTH_32 1 +#define XDDR5_BUS_WIDTH_16 2 + +/** + * struct ecc_error_info - ECC error log information. + * @burstpos: Burst position. + * @lrank: Logical Rank number. + * @rank: Rank number. + * @group: Group number. + * @bank: Bank number. + * @col: Column number. + * @row: Row number. + * @rowhi: Row number higher bits. + * @i: Combined ECC error vector containing encoded values of burst posi= tion, + * rank, bank, column, and row information. + */ +union ecc_error_info { + struct { + u32 burstpos:3; + u32 lrank:4; + u32 rank:2; + u32 group:3; + u32 bank:2; + u32 col:11; + u32 row:7; + u32 rowhi; + }; + u64 i; +} __packed; + +/* Row and column bit positions in the address decoder (ADEC) registers. */ +union row_col_mapping { + struct { + u32 row0:6; + u32 row1:6; + u32 row2:6; + u32 row3:6; + u32 row4:6; + u32 reserved:2; + }; + struct { + u32 col1:6; + u32 col2:6; + u32 col3:6; + u32 col4:6; + u32 col5:6; + u32 reservedcol:2; + }; + u32 i; +} __packed; + +/** + * struct ecc_status - ECC status information to report. + * @ceinfo: Correctable errors. + * @ueinfo: Uncorrected errors. + * @channel: Channel number. + * @error_type: Error type. + */ +struct ecc_status { + union ecc_error_info ceinfo[2]; + union ecc_error_info ueinfo[2]; + u8 channel; + u8 error_type; +}; + +/** + * struct mc_priv - DDR memory controller private instance data. + * @message: Buffer for framing the event specific info. + * @stat: ECC status information. + * @error_id: The error id. + * @error_level: The error level. + * @dwidth: Width of data bus excluding ECC bits. + * @part_len: The support of the message received. + * @regs: The registers sent on the rpmsg. + * @adec: Address decode registers. + * @mci: Memory controller interface. + * @ept: rpmsg endpoint. + * @mcdi: The mcdi handle. + */ +struct mc_priv { + char message[256]; + struct ecc_status stat; + u32 error_id; + u32 error_level; + u32 dwidth; + u32 part_len; + u32 regs[REG_MAX]; + u32 adec[ADEC_MAX]; + struct mem_ctl_info *mci[NUM_CONTROLLERS]; + struct rpmsg_endpoint *ept; + struct cdx_mcdi *mcdi; +}; + +/* + * Address decoder (ADEC) registers to match the order in which the regist= er + * information is received from the firmware. + */ +enum adec_info { + CONF =3D 0, + ADEC0, + ADEC1, + ADEC2, + ADEC3, + ADEC4, + ADEC5, + ADEC6, + ADEC7, + ADEC8, + ADEC9, + ADEC10, + ADEC11, + ADEC12, + ADEC13, + ADEC14, + ADEC15, + ADEC16, + ADECILC, +}; + +enum reg_info { + ISR =3D 0, + IMR, + ECCR0_ERR_STATUS, + ECCR0_ADDR_LO, + ECCR0_ADDR_HI, + ECCR0_DATA_LO, + ECCR0_DATA_HI, + ECCR0_PAR, + ECCR1_ERR_STATUS, + ECCR1_ADDR_LO, + ECCR1_ADDR_HI, + ECCR1_DATA_LO, + ECCR1_DATA_HI, + ECCR1_PAR, + XMPU_ERR, + XMPU_ERR_ADDR_L0, + XMPU_ERR_ADDR_HI, + XMPU_ERR_AXI_ID, + ADEC_CHK_ERR_LOG, +}; + +static bool get_ddr_info(u32 *error_data, struct mc_priv *priv) +{ + u32 reglo, reghi, parity, eccr0_val, eccr1_val, isr; + struct ecc_status *p; + + isr =3D error_data[ISR]; + + if (!(isr & (MC5_IRQ_UE_MASK | MC5_IRQ_CE_MASK))) + return false; + + eccr0_val =3D error_data[ECCR0_ERR_STATUS]; + eccr1_val =3D error_data[ECCR1_ERR_STATUS]; + + if (!eccr0_val && !eccr1_val) + return false; + + p =3D &priv->stat; + + if (!eccr0_val) + p->channel =3D 1; + else + p->channel =3D 0; + + reglo =3D error_data[ECCR0_ADDR_LO]; + reghi =3D error_data[ECCR0_ADDR_HI]; + if (isr & MC5_IRQ_CE_MASK) + p->ceinfo[0].i =3D reglo | (u64)reghi << 32; + else if (isr & MC5_IRQ_UE_MASK) + p->ueinfo[0].i =3D reglo | (u64)reghi << 32; + + parity =3D error_data[ECCR0_PAR]; + edac_dbg(2, "ERR DATA: 0x%08X%08X PARITY: 0x%08X\n", + reghi, reglo, parity); + + reglo =3D error_data[ECCR1_ADDR_LO]; + reghi =3D error_data[ECCR1_ADDR_HI]; + if (isr & MC5_IRQ_CE_MASK) + p->ceinfo[1].i =3D reglo | (u64)reghi << 32; + else if (isr & MC5_IRQ_UE_MASK) + p->ueinfo[1].i =3D reglo | (u64)reghi << 32; + + parity =3D error_data[ECCR1_PAR]; + edac_dbg(2, "ERR DATA: 0x%08X%08X PARITY: 0x%08X\n", + reghi, reglo, parity); + + return true; +} + +/** + * convert_to_physical - Convert @error_data to a physical address. + * @priv: DDR memory controller private instance data. + * @pinf: ECC error info structure. + * @controller: Controller number of the MC5 + * @error_data: the DDRMC5 ADEC address decoder register data + * + * Return: physical address of the DDR memory. + */ +static unsigned long convert_to_physical(struct mc_priv *priv, + union ecc_error_info pinf, + int controller, int *error_data) +{ + u32 row, blk, rsh_req_addr, interleave, ilc_base_ctrl_add, ilc_himem_en, = reg, offset; + u64 high_mem_base, high_mem_offset, low_mem_offset, ilcmem_base; + unsigned long err_addr =3D 0, addr; + union row_col_mapping cols; + union row_col_mapping rows; + u32 col_bit_0; + + row =3D pinf.rowhi << MC5_REGHI_ROW | pinf.row; + offset =3D controller * ADEC_NUM; + + reg =3D error_data[ADEC6]; + rows.i =3D reg; + err_addr |=3D (row & BIT(0)) << rows.row0; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row1; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row2; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row3; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row4; + row >>=3D MC5_EACHBIT; + + reg =3D error_data[ADEC7]; + rows.i =3D reg; + err_addr |=3D (row & BIT(0)) << rows.row0; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row1; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row2; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row3; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row4; + row >>=3D MC5_EACHBIT; + + reg =3D error_data[ADEC8]; + rows.i =3D reg; + err_addr |=3D (row & BIT(0)) << rows.row0; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row1; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row2; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row3; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row4; + + reg =3D error_data[ADEC9]; + rows.i =3D reg; + + err_addr |=3D (row & BIT(0)) << rows.row0; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row1; + row >>=3D MC5_EACHBIT; + err_addr |=3D (row & BIT(0)) << rows.row2; + row >>=3D MC5_EACHBIT; + + col_bit_0 =3D FIELD_GET(MASK_24, error_data[ADEC9]); + pinf.col >>=3D 1; + err_addr |=3D (pinf.col & 1) << col_bit_0; + + cols.i =3D error_data[ADEC10]; + err_addr |=3D (pinf.col & 1) << cols.col1; + pinf.col >>=3D 1; + err_addr |=3D (pinf.col & 1) << cols.col2; + pinf.col >>=3D 1; + err_addr |=3D (pinf.col & 1) << cols.col3; + pinf.col >>=3D 1; + err_addr |=3D (pinf.col & 1) << cols.col4; + pinf.col >>=3D 1; + err_addr |=3D (pinf.col & 1) << cols.col5; + pinf.col >>=3D 1; + + cols.i =3D error_data[ADEC11]; + err_addr |=3D (pinf.col & 1) << cols.col1; + pinf.col >>=3D 1; + err_addr |=3D (pinf.col & 1) << cols.col2; + pinf.col >>=3D 1; + err_addr |=3D (pinf.col & 1) << cols.col3; + pinf.col >>=3D 1; + err_addr |=3D (pinf.col & 1) << cols.col4; + pinf.col >>=3D 1; + err_addr |=3D (pinf.col & 1) << cols.col5; + pinf.col >>=3D 1; + + reg =3D error_data[ADEC12]; + err_addr |=3D (pinf.bank & BIT(0)) << (reg & MASK_0); + pinf.bank >>=3D MC5_EACHBIT; + err_addr |=3D (pinf.bank & BIT(0)) << FIELD_GET(MC5_BANK1_MASK, reg); + pinf.bank >>=3D MC5_EACHBIT; + + err_addr |=3D (pinf.bank & BIT(0)) << FIELD_GET(MC5_GRP_0_MASK, reg); + pinf.group >>=3D MC5_EACHBIT; + err_addr |=3D (pinf.bank & BIT(0)) << FIELD_GET(MC5_GRP_1_MASK, reg); + pinf.group >>=3D MC5_EACHBIT; + err_addr |=3D (pinf.bank & BIT(0)) << FIELD_GET(MASK_24, reg); + pinf.group >>=3D MC5_EACHBIT; + + reg =3D error_data[ADEC4]; + err_addr |=3D (pinf.rank & BIT(0)) << (reg & MASK_0); + pinf.rank >>=3D MC5_EACHBIT; + err_addr |=3D (pinf.rank & BIT(0)) << FIELD_GET(MC5_RANK_1_MASK, reg); + pinf.rank >>=3D MC5_EACHBIT; + + reg =3D error_data[ADEC5]; + err_addr |=3D (pinf.lrank & BIT(0)) << (reg & MASK_0); + pinf.lrank >>=3D MC5_EACHBIT; + err_addr |=3D (pinf.lrank & BIT(0)) << FIELD_GET(MC5_LRANK_1_MASK, reg); + pinf.lrank >>=3D MC5_EACHBIT; + err_addr |=3D (pinf.lrank & BIT(0)) << FIELD_GET(MC5_LRANK_2_MASK, reg); + pinf.lrank >>=3D MC5_EACHBIT; + err_addr |=3D (pinf.lrank & BIT(0)) << FIELD_GET(MASK_24, reg); + pinf.lrank >>=3D MC5_EACHBIT; + + high_mem_base =3D (priv->adec[ADEC2 + offset] & MC5_MEM_MASK) * MC5_HIMEM= _BASE; + interleave =3D priv->adec[ADEC13 + offset] & MC5_INTERLEAVE_SEL; + + high_mem_offset =3D priv->adec[ADEC3 + offset] & MC5_MEM_MASK; + low_mem_offset =3D priv->adec[ADEC1 + offset] & MC5_MEM_MASK; + reg =3D priv->adec[ADEC14 + offset]; + ilc_himem_en =3D !!(reg & MC5_ILC_HIMEM_EN); + ilcmem_base =3D (reg & MC5_ILC_MEM) * SZ_1M; + if (ilc_himem_en) + ilc_base_ctrl_add =3D ilcmem_base - high_mem_offset; + else + ilc_base_ctrl_add =3D ilcmem_base - low_mem_offset; + + if (priv->dwidth =3D=3D DEV_X16) { + blk =3D err_addr / MC5_X16_SIZE; + rsh_req_addr =3D (blk << 8) + ilc_base_ctrl_add; + err_addr =3D rsh_req_addr * interleave * 2; + } else { + blk =3D err_addr / MC5_X32_SIZE; + rsh_req_addr =3D (blk << 9) + ilc_base_ctrl_add; + err_addr =3D rsh_req_addr * interleave * 2; + } + + if ((priv->adec[ADEC2 + offset] & MC5_HIGH_MEM_EN) && err_addr >=3D high_= mem_base) + addr =3D err_addr - high_mem_offset; + else + addr =3D err_addr - low_mem_offset; + + return addr; +} + +/** + * handle_error - Handle errors. + * @priv: DDR memory controller private instance data. + * @stat: ECC status structure. + * @ctl_num: Controller number of the MC5 + * @error_data: the MC5 ADEC address decoder register data + * + * Handles ECC correctable and uncorrectable errors. + */ +static void handle_error(struct mc_priv *priv, struct ecc_status *stat, + int ctl_num, int *error_data) +{ + union ecc_error_info pinf; + struct mem_ctl_info *mci; + unsigned long pa; + phys_addr_t pfn; + int err; + + if (WARN_ON_ONCE(ctl_num > NUM_CONTROLLERS)) + return; + + mci =3D priv->mci[ctl_num]; + + if (stat->error_type =3D=3D MC5_ERR_TYPE_CE) { + pinf =3D stat->ceinfo[stat->channel]; + snprintf(priv->message, sizeof(priv->message), + "Error type:%s Controller %d Addr at %lx\n", + "CE", ctl_num, convert_to_physical(priv, pinf, ctl_num, error_data)); + + edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, + 1, 0, 0, 0, 0, 0, -1, + priv->message, ""); + } + + if (stat->error_type =3D=3D MC5_ERR_TYPE_UE) { + pinf =3D stat->ueinfo[stat->channel]; + snprintf(priv->message, sizeof(priv->message), + "Error type:%s controller %d Addr at %lx\n", + "UE", ctl_num, convert_to_physical(priv, pinf, ctl_num, error_data)); + + edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, + 1, 0, 0, 0, 0, 0, -1, + priv->message, ""); + pa =3D convert_to_physical(priv, pinf, ctl_num, error_data); + pfn =3D PHYS_PFN(pa); + + if (IS_ENABLED(CONFIG_MEMORY_FAILURE)) { + err =3D memory_failure(pfn, MF_ACTION_REQUIRED); + if (err) + edac_dbg(2, "memory_failure() error: %d", err); + else + edac_dbg(2, "Poison page at PA 0x%lx\n", pa); + } + } +} + +static void mc_init(struct mem_ctl_info *mci, struct device *dev) +{ + struct mc_priv *priv =3D mci->pvt_info; + struct csrow_info *csi; + struct dimm_info *dimm; + u32 row; + int ch; + + /* Initialize controller capabilities and configuration */ + mci->mtype_cap =3D MEM_FLAG_DDR5; + mci->edac_ctl_cap =3D EDAC_FLAG_NONE | EDAC_FLAG_SECDED; + mci->scrub_cap =3D SCRUB_HW_SRC; + mci->scrub_mode =3D SCRUB_NONE; + + mci->edac_cap =3D EDAC_FLAG_SECDED; + mci->ctl_name =3D "VersalNET DDR5"; + mci->dev_name =3D dev_name(dev); + mci->mod_name =3D "versalnet_edac"; + + edac_op_state =3D EDAC_OPSTATE_INT; + + for (row =3D 0; row < mci->nr_csrows; row++) { + csi =3D mci->csrows[row]; + for (ch =3D 0; ch < csi->nr_channels; ch++) { + dimm =3D csi->channels[ch]->dimm; + dimm->edac_mode =3D EDAC_SECDED; + dimm->mtype =3D MEM_DDR5; + dimm->grain =3D MC5_ERR_GRAIN; + dimm->dtype =3D priv->dwidth; + } + } +} + +#define to_mci(k) container_of(k, struct mem_ctl_info, dev) + +static unsigned int mcdi_rpc_timeout(struct cdx_mcdi *cdx, unsigned int cm= d) +{ + return MCDI_RPC_TIMEOUT; +} + +static void mcdi_request(struct cdx_mcdi *cdx, + const struct cdx_dword *hdr, size_t hdr_len, + const struct cdx_dword *sdu, size_t sdu_len) +{ + void *send_buf; + int ret; + + send_buf =3D kzalloc(hdr_len + sdu_len, GFP_KERNEL); + if (!send_buf) + return; + + memcpy(send_buf, hdr, hdr_len); + memcpy(send_buf + hdr_len, sdu, sdu_len); + + ret =3D rpmsg_send(cdx->ept, send_buf, hdr_len + sdu_len); + if (ret) + dev_err(&cdx->rpdev->dev, "Failed to send rpmsg data: %d\n", ret); + + kfree(send_buf); +} + +static const struct cdx_mcdi_ops mcdi_ops =3D { + .mcdi_rpc_timeout =3D mcdi_rpc_timeout, + .mcdi_request =3D mcdi_request, +}; + +static void get_ddr_config(u32 index, u32 *buffer, struct cdx_mcdi *amd_mc= di) +{ + size_t outlen; + int ret; + + MCDI_DECLARE_BUF(inbuf, MC_GET_DDR_CONFIG_IN_LEN); + MCDI_DECLARE_BUF(outbuf, BUFFER_SZ); + + MCDI_SET_DWORD(inbuf, EDAC_GET_DDR_CONFIG_IN_CONTROLLER_INDEX, index); + + ret =3D cdx_mcdi_rpc(amd_mcdi, MC_CMD_EDAC_GET_DDR_CONFIG, inbuf, sizeof(= inbuf), + outbuf, sizeof(outbuf), &outlen); + if (!ret) + memcpy(buffer, MCDI_PTR(outbuf, GET_DDR_CONFIG), + (ADEC_NUM * 4)); +} + +static int setup_mcdi(struct mc_priv *mc_priv) +{ + struct cdx_mcdi *amd_mcdi; + int ret, i; + + amd_mcdi =3D kzalloc(sizeof(*amd_mcdi), GFP_KERNEL); + if (!amd_mcdi) + return -ENOMEM; + + amd_mcdi->mcdi_ops =3D &mcdi_ops; + ret =3D cdx_mcdi_init(amd_mcdi); + if (ret) { + kfree(amd_mcdi); + return ret; + } + + amd_mcdi->ept =3D mc_priv->ept; + mc_priv->mcdi =3D amd_mcdi; + + for (i =3D 0; i < NUM_CONTROLLERS; i++) + get_ddr_config(i, &mc_priv->adec[ADEC_NUM * i], amd_mcdi); + + return 0; +} + +static const guid_t amd_versalnet_guid =3D GUID_INIT(0x82678888, 0xa556, 0= x44f2, + 0xb8, 0xb4, 0x45, 0x56, 0x2e, + 0x8c, 0x5b, 0xec); + +static int rpmsg_cb(struct rpmsg_device *rpdev, void *data, + int len, void *priv, u32 src) +{ + struct mc_priv *mc_priv =3D dev_get_drvdata(&rpdev->dev); + const guid_t *sec_type =3D &guid_null; + u32 length, offset, error_id; + u32 *result =3D (u32 *)data; + struct ecc_status *p; + int i, j, k, sec_sev; + const char *err_str; + u32 *adec_data; + + if (*(u8 *)data =3D=3D MCDI_RESPONSE) { + cdx_mcdi_process_cmd(mc_priv->mcdi, (struct cdx_dword *)data, len); + return 0; + } + + sec_sev =3D result[ERROR_LEVEL]; + error_id =3D result[ERROR_ID]; + length =3D result[MSG_ERR_LENGTH]; + offset =3D result[MSG_ERR_OFFSET]; + + if (result[TOTAL_ERR_LENGTH] > length) { + if (!mc_priv->part_len) + mc_priv->part_len =3D length; + else + mc_priv->part_len +=3D length; + /* + * The data can come in 2 stretches. Construct the regs from 2 + * messages the offset indicates the offset from which the data is to + * be taken + */ + for (i =3D 0 ; i < length; i++) { + k =3D offset + i; + j =3D ERROR_DATA + i; + mc_priv->regs[k] =3D result[j]; + } + if (mc_priv->part_len < result[TOTAL_ERR_LENGTH]) + return 0; + mc_priv->part_len =3D 0; + } + + mc_priv->error_id =3D error_id; + mc_priv->error_level =3D result[ERROR_LEVEL]; + + switch (error_id) { + case 5: err_str =3D "General Software Non-Correctable error"; break; + case 6: err_str =3D "CFU error"; break; + case 7: err_str =3D "CFRAME error"; break; + case 10: err_str =3D "DDRMC Microblaze Correctable ECC error"; break; + case 11: err_str =3D "DDRMC Microblaze Non-Correctable ECC error"; break; + case 15: err_str =3D "MMCM error"; break; + case 16: err_str =3D "HNICX Correctable error"; break; + case 17: err_str =3D "HNICX Non-Correctable error"; break; + + case 18: + p =3D &mc_priv->stat; + memset(p, 0, sizeof(struct ecc_status)); + p->error_type =3D MC5_ERR_TYPE_CE; + for (i =3D 0 ; i < NUM_CONTROLLERS; i++) { + if (get_ddr_info(&mc_priv->regs[i * REGS_PER_CONTROLLER], mc_priv)) { + adec_data =3D mc_priv->adec + ADEC_NUM * i; + handle_error(mc_priv, &mc_priv->stat, i, adec_data); + } + } + return 0; + case 19: + p =3D &mc_priv->stat; + memset(p, 0, sizeof(struct ecc_status)); + p->error_type =3D MC5_ERR_TYPE_UE; + for (i =3D 0 ; i < NUM_CONTROLLERS; i++) { + if (get_ddr_info(&mc_priv->regs[i * REGS_PER_CONTROLLER], mc_priv)) { + adec_data =3D mc_priv->adec + ADEC_NUM * i; + handle_error(mc_priv, &mc_priv->stat, i, adec_data); + } + } + return 0; + + case 21: err_str =3D "GT Non-Correctable error"; break; + case 22: err_str =3D "PL Sysmon Correctable error"; break; + case 23: err_str =3D "PL Sysmon Non-Correctable error"; break; + case 111: err_str =3D "LPX unexpected dfx activation error"; break; + case 114: err_str =3D "INT_LPD Non-Correctable error"; break; + case 116: err_str =3D "INT_OCM Non-Correctable error"; break; + case 117: err_str =3D "INT_FPD Correctable error"; break; + case 118: err_str =3D "INT_FPD Non-Correctable error"; break; + case 120: err_str =3D "INT_IOU Non-Correctable error"; break; + case 123: err_str =3D "err_int_irq from APU GIC Distributor"; break; + case 124: err_str =3D "fault_int_irq from APU GIC Distribute"; break; + case 132 ... 139: err_str =3D "FPX SPLITTER error"; break; + case 140: err_str =3D "APU Cluster 0 error"; break; + case 141: err_str =3D "APU Cluster 1 error"; break; + case 142: err_str =3D "APU Cluster 2 error"; break; + case 143: err_str =3D "APU Cluster 3 error"; break; + case 145: err_str =3D "WWDT1 LPX error"; break; + case 147: err_str =3D "IPI error"; break; + case 152 ... 153: err_str =3D "AFIFS error"; break; + case 154 ... 155: err_str =3D "LPX glitch error"; break; + case 185 ... 186: err_str =3D "FPX AFIFS error"; break; + case 195 ... 199: err_str =3D "AFIFM error"; break; + case 108: err_str =3D "PSM Correctable error"; break; + case 59: err_str =3D "PMC correctable error"; break; + case 60: err_str =3D "PMC Un correctable error"; break; + case 43 ... 47: err_str =3D "PMC Sysmon error"; break; + case 163 ... 184: err_str =3D "RPU error"; break; + case 148: err_str =3D "OCM0 correctable error"; break; + case 149: err_str =3D "OCM1 correctable error"; break; + case 150: err_str =3D "OCM0 Un-correctable error"; break; + case 151: err_str =3D "OCM1 Un-correctable error"; break; + case 189: err_str =3D "PSX_CMN_3 PD block consolidated error"; break; + case 191: err_str =3D "FPD_INT_WRAP PD block consolidated error"; break; + case 232: err_str =3D "CRAM Un-Correctable error"; break; + default: err_str =3D "VERSAL_EDAC_ERR_ID: %d"; break; + } + + snprintf(mc_priv->message, + sizeof(mc_priv->message), + "[VERSAL_EDAC_ERR_ID: %d] Error type: %s", error_id, err_str); + + /* Convert to bytes */ + length =3D result[TOTAL_ERR_LENGTH] * 4; + log_non_standard_event(sec_type, &amd_versalnet_guid, mc_priv->message, + sec_sev, (void *)&result[ERROR_DATA], length); + + return 0; +} + +static struct rpmsg_device_id amd_rpmsg_id_table[] =3D { + { .name =3D "error_ipc" }, + { }, +}; +MODULE_DEVICE_TABLE(rpmsg, amd_rpmsg_id_table); + +static int rpmsg_probe(struct rpmsg_device *rpdev) +{ + struct rpmsg_channel_info chinfo; + struct mc_priv *pg; + + pg =3D (struct mc_priv *)amd_rpmsg_id_table[0].driver_data; + chinfo.src =3D RPMSG_ADDR_ANY; + chinfo.dst =3D rpdev->dst; + strscpy(chinfo.name, amd_rpmsg_id_table[0].name, + strlen(amd_rpmsg_id_table[0].name)); + + pg->ept =3D rpmsg_create_ept(rpdev, rpmsg_cb, NULL, chinfo); + if (!pg->ept) + return dev_err_probe(&rpdev->dev, -ENXIO, "Failed to create ept for chan= nel %s\n", + chinfo.name); + + dev_set_drvdata(&rpdev->dev, pg); + + return 0; +} + +static void rpmsg_remove(struct rpmsg_device *rpdev) +{ + struct mc_priv *mc_priv =3D dev_get_drvdata(&rpdev->dev); + + rpmsg_destroy_ept(mc_priv->ept); + dev_set_drvdata(&rpdev->dev, NULL); +} + +static struct rpmsg_driver amd_rpmsg_driver =3D { + .drv.name =3D KBUILD_MODNAME, + .probe =3D rpmsg_probe, + .remove =3D rpmsg_remove, + .callback =3D rpmsg_cb, + .id_table =3D amd_rpmsg_id_table, +}; + +static void versal_edac_release(struct device *dev) +{ + kfree(dev); +} + +static int init_versalnet(struct mc_priv *priv, struct platform_device *pd= ev) +{ + u32 num_chans, rank, dwidth, config; + struct edac_mc_layer layers[2]; + struct mem_ctl_info *mci; + struct device *dev; + enum dev_type dt; + char *name; + int rc, i; + + for (i =3D 0; i < NUM_CONTROLLERS; i++) { + config =3D priv->adec[CONF + i * ADEC_NUM]; + num_chans =3D FIELD_GET(MC5_NUM_CHANS_MASK, config); + rank =3D 1 << FIELD_GET(MC5_RANK_MASK, config); + dwidth =3D FIELD_GET(MC5_BUS_WIDTH_MASK, config); + + switch (dwidth) { + case XDDR5_BUS_WIDTH_16: + dt =3D DEV_X16; + break; + case XDDR5_BUS_WIDTH_32: + dt =3D DEV_X32; + break; + case XDDR5_BUS_WIDTH_64: + dt =3D DEV_X64; + break; + default: + dt =3D DEV_UNKNOWN; + } + + if (dt =3D=3D DEV_UNKNOWN) + continue; + + /* Find the first enabled device and register that one. */ + layers[0].type =3D EDAC_MC_LAYER_CHIP_SELECT; + layers[0].size =3D rank; + layers[0].is_virt_csrow =3D true; + layers[1].type =3D EDAC_MC_LAYER_CHANNEL; + layers[1].size =3D num_chans; + layers[1].is_virt_csrow =3D false; + + rc =3D -ENOMEM; + mci =3D edac_mc_alloc(i, ARRAY_SIZE(layers), layers, + sizeof(struct mc_priv)); + if (!mci) { + edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for MC%d\n", i= ); + goto err_alloc; + } + + priv->mci[i] =3D mci; + priv->dwidth =3D dt; + + dev =3D kzalloc(sizeof(*dev), GFP_KERNEL); + dev->release =3D versal_edac_release; + name =3D kmalloc(32, GFP_KERNEL); + sprintf(name, "versal-net-ddrmc5-edac-%d", i); + dev->init_name =3D name; + rc =3D device_register(dev); + if (rc) + goto err_alloc; + + mci->pdev =3D dev; + + platform_set_drvdata(pdev, priv); + + mc_init(mci, dev); + rc =3D edac_mc_add_mc(mci); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, "Failed to register MC%d with EDAC core\= n", i); + goto err_alloc; + } + } + return 0; + +err_alloc: + while (i--) { + mci =3D priv->mci[i]; + if (!mci) + continue; + + if (mci->pdev) { + device_unregister(mci->pdev); + edac_mc_del_mc(mci->pdev); + } + + edac_mc_free(mci); + } + + return rc; +} + +static void remove_versalnet(struct mc_priv *priv) +{ + struct mem_ctl_info *mci; + int i; + + for (i =3D 0; i < NUM_CONTROLLERS; i++) { + device_unregister(priv->mci[i]->pdev); + mci =3D edac_mc_del_mc(priv->mci[i]->pdev); + if (!mci) + return; + + edac_mc_free(mci); + } +} + +static int mc_probe(struct platform_device *pdev) +{ + struct device_node *r5_core_node; + struct mc_priv *priv; + struct rproc *rp; + int rc; + + r5_core_node =3D of_parse_phandle(pdev->dev.of_node, "amd,rproc", 0); + if (!r5_core_node) { + dev_err(&pdev->dev, "amd,rproc: invalid phandle\n"); + return -EINVAL; + } + + rp =3D rproc_get_by_phandle(r5_core_node->phandle); + if (!rp) + return -EPROBE_DEFER; + + rc =3D rproc_boot(rp); + if (rc) { + dev_err(&pdev->dev, "Failed to attach to remote processor\n"); + goto err_rproc_boot; + } + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + goto err_alloc; + + amd_rpmsg_id_table[0].driver_data =3D (kernel_ulong_t)priv; + + rc =3D register_rpmsg_driver(&amd_rpmsg_driver); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, "Failed to register RPMsg driver: %d\n", = rc); + goto err_alloc; + } + + rc =3D setup_mcdi(priv); + if (rc) + goto err_unreg; + + priv->mcdi->r5_rproc =3D rp; + + rc =3D init_versalnet(priv, pdev); + if (rc) + goto err_init; + + return 0; + +err_init: + cdx_mcdi_finish(priv->mcdi); + +err_unreg: + unregister_rpmsg_driver(&amd_rpmsg_driver); + +err_alloc: + rproc_shutdown(rp); + +err_rproc_boot: + rproc_put(rp); + + return rc; +} + +static void mc_remove(struct platform_device *pdev) +{ + struct mc_priv *priv =3D platform_get_drvdata(pdev); + + unregister_rpmsg_driver(&amd_rpmsg_driver); + remove_versalnet(priv); + rproc_shutdown(priv->mcdi->r5_rproc); + cdx_mcdi_finish(priv->mcdi); +} + +static const struct of_device_id amd_edac_match[] =3D { + { .compatible =3D "xlnx,versal-net-ddrmc5", }, + {} +}; +MODULE_DEVICE_TABLE(of, amd_edac_match); + +static struct platform_driver amd_ddr_edac_mc_driver =3D { + .driver =3D { + .name =3D "versal-net-edac", + .of_match_table =3D amd_edac_match, + }, + .probe =3D mc_probe, + .remove =3D mc_remove, +}; + +module_platform_driver(amd_ddr_edac_mc_driver); + +MODULE_AUTHOR("AMD Inc"); +MODULE_DESCRIPTION("Versal NET EDAC driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/cdx/edac_cdx_pcol.h b/include/linux/cdx/edac_cdx= _pcol.h new file mode 100644 index 000000000000..749db33bb482 --- /dev/null +++ b/include/linux/cdx/edac_cdx_pcol.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Driver for AMD network controllers and boards + * + * Copyright (C) 2021, Xilinx, Inc. + * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. + */ + +#ifndef MC_CDX_PCOL_H +#define MC_CDX_PCOL_H +#include + +#define MC_CMD_EDAC_GET_DDR_CONFIG_OUT_WORD_LENGTH_LEN 4 +/* Number of registers for the DDR controller */ +#define MC_CMD_GET_DDR_CONFIG_OFST 4 +#define MC_CMD_GET_DDR_CONFIG_LEN 4 + +/***********************************/ +/* MC_CMD_EDAC_GET_DDR_CONFIG + * Provides detailed configuration for the DDR controller of the given ind= ex. + */ +#define MC_CMD_EDAC_GET_DDR_CONFIG 0x3 + +/* MC_CMD_EDAC_GET_DDR_CONFIG_IN msgrequest */ +#define MC_CMD_EDAC_GET_DDR_CONFIG_IN_CONTROLLER_INDEX_OFST 0 +#define MC_CMD_EDAC_GET_DDR_CONFIG_IN_CONTROLLER_INDEX_LEN 4 + +#endif /* MC_CDX_PCOL_H */ --=20 2.34.1