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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 11:21:44.0021 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4f743bb-292a-49d7-84d8-08ddeec9e433 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB8429 Content-Type: text/plain; charset="utf-8" Add device tree binding documentation for the AMD I3C master controller. Signed-off-by: Manikanta Guntupalli --- Changes for V2: Updated commit subject and description. Moved allOf to after required. Removed xlnx,num-targets property. Changes for V3: Updated commit description. Corrected the order of properties and removed resets property. Added compatible to required list. Added interrupts to example. Changes for V4: Added h/w documentation details. Changes for V5: Renamed the xlnx,axi-i3c.yaml file into xlnx,axi-i3c-1.0.yaml. --- .../bindings/i3c/xlnx,axi-i3c-1.0.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.= yaml diff --git a/Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml b/= Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml new file mode 100644 index 000000000000..1daeb20205ac --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i3c/xlnx,axi-i3c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD I3C master + +maintainers: + - Manikanta Guntupalli + +description: + The AXI-I3C IP is an I3C Controller with an AXI4-Lite interface, compati= ble + with the MIPI I3C Specification v1.1.1. The design includes bidirectiona= l I/O + buffers that implement open collector drivers for the SDA and SCL signal= s. + External pull-up resistors are required to properly hold the bus at a Lo= gic-1 + level when the drivers are released. + + For more details, please see https://docs.amd.com/r/en-US/pg439-axi-i3c + +properties: + compatible: + const: xlnx,axi-i3c-1.0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +allOf: + - $ref: i3c.yaml# + +unevaluatedProperties: false + +examples: + - | + i3c@80000000 { + compatible =3D "xlnx,axi-i3c-1.0"; + reg =3D <0x80000000 0x10000>; + clocks =3D <&zynqmp_clk 71>; + interrupt-parent =3D <&imux>; + interrupts =3D <0 89 4>; + #address-cells =3D <3>; + #size-cells =3D <0>; + }; +... --=20 2.34.1