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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Philipp Zabel , Russell King , Geert Uytterhoeven , Magnus Damm , Vladimir Oltean , Giuseppe Cavallaro , Jose Abreu Cc: netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v3 1/3] dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/T2H and RZ/N2H SoCs Date: Mon, 8 Sep 2025 11:58:59 +0100 Message-ID: <20250908105901.3198975-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250908105901.3198975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250908105901.3198975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add device tree binding support for the Gigabit Ethernet MAC (GMAC) IP on Renesas RZ/T2H and RZ/N2H SoCs. While these SoCs use the same Synopsys DesignWare MAC version 5.20 as RZ/V2H, they are synthesized with different hardware configurations. Add new compatible strings "renesas,r9a09g077-gbeth" for RZ/T2H and "renesas,r9a09g087-gbeth" for RZ/N2H, with the latter using RZ/T2H as fallback since they share identical GMAC IP. Update the schema to handle hardware differences between SoC variants. RZ/T2H requires only 3 clocks compared to 7 on RZ/V2H, supports 8 RX/TX queue pairs instead of 4, and needs 2 reset controls with reset-names property versus a single unnamed reset. RZ/T2H also has the split header feature enabled which is disabled on RZ/V2H. Add support for an optional pcs-handle property to connect the GMAC to the MIIC PCS converter on RZ/T2H. Use conditional schema validation to enforce the correct clock, reset, and interrupt configurations per SoC variant. Extend the base snps,dwmac.yaml schema to accommodate the increased interrupt count, supporting up to 19 interrupts and extending the rx-queue and tx-queue interrupt name patterns to cover queues 0-7. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski --- v2->v3: - No changes. v1->v2: - Squshed incerasing interrupt count changes to snps,dwmac.yaml into this p= atch. - Dropped un-necessary blank lines. - Switched using "renesas,r9a09g077-gbeth" compatible string for RZ/T2H instead of "renesas,rzt2h-gbeth" and used it as a fallback for RZ/N2H. - Added pcs-handle property required for RZ/T2H. - Updated description for reset property. - Updated commit message to reflect changes. --- .../bindings/net/renesas,rzv2h-gbeth.yaml | 178 ++++++++++++++---- .../devicetree/bindings/net/snps,dwmac.yaml | 9 +- 2 files changed, 143 insertions(+), 44 deletions(-) diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml= b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml index 23e39bcea96b..bd53ab300f50 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml @@ -17,63 +17,111 @@ select: - renesas,r9a09g047-gbeth - renesas,r9a09g056-gbeth - renesas,r9a09g057-gbeth + - renesas,r9a09g077-gbeth + - renesas,r9a09g087-gbeth - renesas,rzv2h-gbeth required: - compatible =20 properties: compatible: - items: - - enum: - - renesas,r9a09g047-gbeth # RZ/G3E - - renesas,r9a09g056-gbeth # RZ/V2N - - renesas,r9a09g057-gbeth # RZ/V2H(P) - - const: renesas,rzv2h-gbeth - - const: snps,dwmac-5.20 + oneOf: + - items: + - enum: + - renesas,r9a09g047-gbeth # RZ/G3E + - renesas,r9a09g056-gbeth # RZ/V2N + - renesas,r9a09g057-gbeth # RZ/V2H(P) + - const: renesas,rzv2h-gbeth + - const: snps,dwmac-5.20 + - items: + - const: renesas,r9a09g077-gbeth # RZ/T2H + - const: snps,dwmac-5.20 + - items: + - const: renesas,r9a09g087-gbeth # RZ/N2H + - const: renesas,r9a09g077-gbeth + - const: snps,dwmac-5.20 =20 reg: maxItems: 1 =20 clocks: - items: - - description: CSR clock - - description: AXI system clock - - description: PTP clock - - description: TX clock - - description: RX clock - - description: TX clock phase-shifted by 180 degrees - - description: RX clock phase-shifted by 180 degrees + oneOf: + - items: + - description: CSR clock + - description: AXI system clock + - description: PTP clock + - description: TX clock + - description: RX clock + - description: TX clock phase-shifted by 180 degrees + - description: RX clock phase-shifted by 180 degrees + - items: + - description: CSR clock + - description: AXI system clock + - description: TX clock =20 clock-names: - items: - - const: stmmaceth - - const: pclk - - const: ptp_ref - - const: tx - - const: rx - - const: tx-180 - - const: rx-180 - - interrupts: - minItems: 11 + oneOf: + - items: + - const: stmmaceth + - const: pclk + - const: ptp_ref + - const: tx + - const: rx + - const: tx-180 + - const: rx-180 + - items: + - const: stmmaceth + - const: pclk + - const: tx =20 interrupt-names: - items: - - const: macirq - - const: eth_wake_irq - - const: eth_lpi - - const: rx-queue-0 - - const: rx-queue-1 - - const: rx-queue-2 - - const: rx-queue-3 - - const: tx-queue-0 - - const: tx-queue-1 - - const: tx-queue-2 - - const: tx-queue-3 + oneOf: + - items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + - items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: rx-queue-4 + - const: rx-queue-5 + - const: rx-queue-6 + - const: rx-queue-7 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + - const: tx-queue-4 + - const: tx-queue-5 + - const: tx-queue-6 + - const: tx-queue-7 =20 resets: - items: - - description: AXI power-on system reset + oneOf: + - items: + - description: AXI power-on system reset + - items: + - description: AXI power-on system reset + - description: AHB reset + + pcs-handle: + description: + phandle pointing to a PCS sub-node compatible with + Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml# + (Refer RZ/T2H portion in the DT-binding file) =20 required: - compatible @@ -87,6 +135,56 @@ required: allOf: - $ref: snps,dwmac.yaml# =20 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-gbeth + then: + properties: + clocks: + maxItems: 3 + + clock-names: + maxItems: 3 + + interrupts: + minItems: 19 + + interrupt-names: + minItems: 19 + + resets: + minItems: 2 + + reset-names: + minItems: 2 + + required: + - reset-names + else: + properties: + clocks: + minItems: 7 + + clock-names: + minItems: 7 + + interrupts: + minItems: 11 + maxItems: 11 + + interrupt-names: + minItems: 11 + maxItems: 11 + + resets: + maxItems: 1 + + pcs-handle: false + + reset-names: false + unevaluatedProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index 4e3cbaa06229..658c004e6a5c 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -75,6 +75,7 @@ properties: - qcom,sc8280xp-ethqos - qcom,sm8150-ethqos - renesas,r9a06g032-gmac + - renesas,r9a09g077-gbeth - renesas,rzn1-gmac - renesas,rzv2h-gbeth - rockchip,px30-gmac @@ -118,11 +119,11 @@ properties: =20 interrupts: minItems: 1 - maxItems: 11 + maxItems: 19 =20 interrupt-names: minItems: 1 - maxItems: 11 + maxItems: 19 items: oneOf: - description: Combined signal for various interrupt events @@ -134,9 +135,9 @@ properties: - description: The interrupt that occurs when HW safety error trig= gered const: sfty - description: Per channel receive completion interrupt - pattern: '^rx-queue-[0-3]$' + pattern: '^rx-queue-[0-7]$' - description: Per channel transmit completion interrupt - pattern: '^tx-queue-[0-3]$' + pattern: '^tx-queue-[0-7]$' =20 clocks: minItems: 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Philipp Zabel , Russell King , Geert Uytterhoeven , Magnus Damm , Vladimir Oltean , Giuseppe Cavallaro , Jose Abreu Cc: netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v3 2/3] net: stmmac: dwmac-renesas-gbeth: Use OF data for configuration Date: Mon, 8 Sep 2025 11:59:00 +0100 Message-ID: <20250908105901.3198975-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250908105901.3198975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250908105901.3198975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Prepare for adding RZ/T2H SoC support by making the driver configuration selectable via OF match data. While the RZ/V2H(P) and RZ/T2H use the same version of the Synopsys DesignWare MAC (version 5.20), the hardware is synthesized with different options. To accommodate these differences, introduce a struct holding per-SoC configuration such as clock list, number of clocks, TX clock rate control, and STMMAC flags, and retrieve it from the device tree match entry during probe. Signed-off-by: Lad Prabhakar --- v2->v3: - Made sure STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP flag is always set for all the SoCs. v1->v2: - No changes. --- .../stmicro/stmmac/dwmac-renesas-gbeth.c | 57 +++++++++++++++---- 1 file changed, 47 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c b/dr= ivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c index df4ca897a60c..50be944ee37b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c @@ -16,12 +16,34 @@ #include #include #include +#include #include #include +#include =20 #include "stmmac_platform.h" =20 +/** + * struct renesas_gbeth_of_data - OF data for Renesas GBETH + * + * @clks: Array of clock names + * @num_clks: Number of clocks + * @stmmac_flags: Flags for the stmmac driver + * @handle_reset: Flag to indicate if reset control is + * handled by the glue driver or core driver. + * @set_clk_tx_rate: Flag to indicate if Tx clock is fixed or + * set_clk_tx_rate is needed. + */ +struct renesas_gbeth_of_data { + const char * const *clks; + u8 num_clks; + u32 stmmac_flags; + bool handle_reset; + bool set_clk_tx_rate; +}; + struct renesas_gbeth { + const struct renesas_gbeth_of_data *of_data; struct plat_stmmacenet_data *plat_dat; struct reset_control *rstc; struct device *dev; @@ -70,6 +92,7 @@ static void renesas_gbeth_exit(struct platform_device *pd= ev, void *priv) =20 static int renesas_gbeth_probe(struct platform_device *pdev) { + const struct renesas_gbeth_of_data *of_data; struct plat_stmmacenet_data *plat_dat; struct stmmac_resources stmmac_res; struct device *dev =3D &pdev->dev; @@ -91,14 +114,17 @@ static int renesas_gbeth_probe(struct platform_device = *pdev) if (!gbeth) return -ENOMEM; =20 - plat_dat->num_clks =3D ARRAY_SIZE(renesas_gbeth_clks); + of_data =3D of_device_get_match_data(&pdev->dev); + gbeth->of_data =3D of_data; + + plat_dat->num_clks =3D of_data->num_clks; plat_dat->clks =3D devm_kcalloc(dev, plat_dat->num_clks, sizeof(*plat_dat->clks), GFP_KERNEL); if (!plat_dat->clks) return -ENOMEM; =20 for (i =3D 0; i < plat_dat->num_clks; i++) - plat_dat->clks[i].id =3D renesas_gbeth_clks[i]; + plat_dat->clks[i].id =3D of_data->clks[i]; =20 err =3D devm_clk_bulk_get(dev, plat_dat->num_clks, plat_dat->clks); if (err < 0) @@ -109,25 +135,36 @@ static int renesas_gbeth_probe(struct platform_device= *pdev) return dev_err_probe(dev, -EINVAL, "error finding tx clock\n"); =20 - gbeth->rstc =3D devm_reset_control_get_exclusive(dev, NULL); - if (IS_ERR(gbeth->rstc)) - return PTR_ERR(gbeth->rstc); + if (of_data->handle_reset) { + gbeth->rstc =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(gbeth->rstc)) + return PTR_ERR(gbeth->rstc); + } =20 gbeth->dev =3D dev; gbeth->plat_dat =3D plat_dat; plat_dat->bsp_priv =3D gbeth; - plat_dat->set_clk_tx_rate =3D stmmac_set_clk_tx_rate; + if (of_data->set_clk_tx_rate) + plat_dat->set_clk_tx_rate =3D stmmac_set_clk_tx_rate; plat_dat->init =3D renesas_gbeth_init; plat_dat->exit =3D renesas_gbeth_exit; - plat_dat->flags |=3D STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY | - STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP | - STMMAC_FLAG_SPH_DISABLE; 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Mon, 08 Sep 2025 03:59:14 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:393b:4605:1f6c:eea1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45ddfe0b654sm91063195e9.3.2025.09.08.03.59.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:59:14 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Philipp Zabel , Russell King , Geert Uytterhoeven , Magnus Damm , Vladimir Oltean , Giuseppe Cavallaro , Jose Abreu Cc: netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v3 3/3] net: stmmac: dwmac-renesas-gbeth: Add support for RZ/T2H SoC Date: Mon, 8 Sep 2025 11:59:01 +0100 Message-ID: <20250908105901.3198975-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250908105901.3198975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250908105901.3198975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Extend the Renesas GBETH stmmac glue driver to support the RZ/T2H SoC, where the GMAC is connected through a MIIC PCS. Introduce a new `has_pcs` flag in `struct renesas_gbeth_of_data` to indicate when PCS handling is required. When enabled, the driver parses the `pcs-handle` phandle, creates a PCS instance with `miic_create()`, and wires it into phylink. Proper cleanup is done with `miic_destroy()`. New init/exit/select hooks are added to `plat_stmmacenet_data` for PCS integration. Update Kconfig to select `PCS_RZN1_MIIC` when building the Renesas GBETH driver so the PCS support is always available. Signed-off-by: Lad Prabhakar Reported-by: Linux Kernel Functional Testing --- v2->v3: - Dropped passing STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP flag in stmmac_flags as it is always set for all the SoCs. - Updated Kconfig to include RZ/T2H and RZ/N2H. v1->v2: - No changes. --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 +++-- .../stmicro/stmmac/dwmac-renesas-gbeth.c | 51 +++++++++++++++++++ 2 files changed, 58 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 67fa879b1e52..91d9a14362bf 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -133,15 +133,17 @@ config DWMAC_QCOM_ETHQOS stmmac device driver. =20 config DWMAC_RENESAS_GBETH - tristate "Renesas RZ/V2H(P) GBETH support" + tristate "Renesas RZ/V2H(P) GBETH and RZ/T2H, RZ/N2H GMAC support" default ARCH_RENESAS depends on OF && (ARCH_RENESAS || COMPILE_TEST) + select PCS_RZN1_MIIC help - Support for Gigabit Ethernet Interface (GBETH) on Renesas - RZ/V2H(P) SoCs. + Support for Gigabit Ethernet Interface (GBETH)/ Ethernet MAC (GMAC) + on Renesas SoCs. =20 - This selects the Renesas RZ/V2H(P) Soc specific glue layer support - for the stmmac device driver. + This selects Renesas SoC glue layer support for the stmmac device + driver. This driver is used for the RZ/V2H(P) family, RZ/T2H and + RZ/N2H SoCs. =20 config DWMAC_ROCKCHIP tristate "Rockchip dwmac support" diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c b/dr= ivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c index 50be944ee37b..bc7bb975803c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,7 @@ * handled by the glue driver or core driver. * @set_clk_tx_rate: Flag to indicate if Tx clock is fixed or * set_clk_tx_rate is needed. + * @has_pcs: Flag to indicate if the MAC has a PCS */ struct renesas_gbeth_of_data { const char * const *clks; @@ -40,6 +42,7 @@ struct renesas_gbeth_of_data { u32 stmmac_flags; bool handle_reset; bool set_clk_tx_rate; + bool has_pcs; }; =20 struct renesas_gbeth { @@ -53,6 +56,41 @@ static const char *const renesas_gbeth_clks[] =3D { "tx", "tx-180", "rx", "rx-180", }; =20 +static const char *const renesas_gmac_clks[] =3D { + "tx", +}; + +static int renesas_gmac_pcs_init(struct stmmac_priv *priv) +{ + struct device_node *np =3D priv->device->of_node; + struct device_node *pcs_node; + struct phylink_pcs *pcs; + + pcs_node =3D of_parse_phandle(np, "pcs-handle", 0); + if (pcs_node) { + pcs =3D miic_create(priv->device, pcs_node); + of_node_put(pcs_node); + if (IS_ERR(pcs)) + return PTR_ERR(pcs); + + priv->hw->phylink_pcs =3D pcs; + } + + return 0; +} + +static void renesas_gmac_pcs_exit(struct stmmac_priv *priv) +{ + if (priv->hw->phylink_pcs) + miic_destroy(priv->hw->phylink_pcs); +} + +static struct phylink_pcs *renesas_gmac_select_pcs(struct stmmac_priv *pri= v, + phy_interface_t interface) +{ + return priv->hw->phylink_pcs; +} + static int renesas_gbeth_init(struct platform_device *pdev, void *priv) { struct plat_stmmacenet_data *plat_dat; @@ -150,6 +188,11 @@ static int renesas_gbeth_probe(struct platform_device = *pdev) plat_dat->exit =3D renesas_gbeth_exit; plat_dat->flags |=3D STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP | gbeth->of_data->stmmac_flags; + if (of_data->has_pcs) { + plat_dat->pcs_init =3D renesas_gmac_pcs_init; + plat_dat->pcs_exit =3D renesas_gmac_pcs_exit; + plat_dat->select_pcs =3D renesas_gmac_select_pcs; + } =20 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } @@ -163,7 +206,15 @@ static const struct renesas_gbeth_of_data renesas_gbet= h_of_data =3D { STMMAC_FLAG_SPH_DISABLE, }; =20 +static const struct renesas_gbeth_of_data renesas_gmac_of_data =3D { + .clks =3D renesas_gmac_clks, + .num_clks =3D ARRAY_SIZE(renesas_gmac_clks), + .stmmac_flags =3D STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY, + .has_pcs =3D true, +}; + static const struct of_device_id renesas_gbeth_match[] =3D { + { .compatible =3D "renesas,r9a09g077-gbeth", .data =3D &renesas_gmac_of_d= ata }, { .compatible =3D "renesas,rzv2h-gbeth", .data =3D &renesas_gbeth_of_data= }, { /* Sentinel */ } }; --=20 2.51.0