From nobody Fri Oct 3 01:59:34 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54A3D2F90DC; Mon, 8 Sep 2025 10:41:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757328093; cv=none; b=kYvzsX+OtJTL+kyGJECyuXCb3c4fVYH9tIeS0Pyisq1aMHMdeMG47p+4z6wyrgOADO9bOuf0uCr0oFQzNykt/qDsrsg5xpiNdrVMT0ZsqxpCnIfOzXfQM8tGnPpw4wyGi0YNLFSMiJ6tLTDXTFAU4dCsl3jJ/TnXR96qdy6Olok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757328093; c=relaxed/simple; bh=j7T4RCmlTXgVKzLCcUgiXlV4EZ/RVhIa7wLCrX0oMds=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sggLf/+ZO6edf96opdePkuOJNhfeqHj6nDlrO3og86BZZOlWA1W7QI8+J1N7pMFmqWyR3TP9KaVdcAE485oHSAUzGV4evedswp8fiPaUXA0tNze6nEOLQKm53AafkV5TuiMCZL+6uwxEr9xxCrn9ye63CTsQ1h6Dk41NSzqKRoE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=XXF38VAA; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="XXF38VAA" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588918C1007291; Mon, 8 Sep 2025 10:41:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=8vsxZBlhE5Z Q93p3zKECfKGTMVUpC6yACQ9x1b1vKpI=; b=XXF38VAAFaH56CthbXC8ctBYEn2 a9voBaDAGyLg1DCHRoPlxPsbGRV+puAB78U7qIbpL2d3QTVpVylimTNapqi8OXQL hwkIFXeeYQkSCjcieWXun1U1ZOxZ/sd1PpK9SKEmnpziiF2gex0zLRvUkTrZS1jA ahUlDRNErwlJLhu/MfszRfBgMeI5OyO/EEPQV0tbw6ueLbMf6sWyyKlZLiurjogB pcnryRWDe18WR6jjbXamPzTnBEB0Dd/PIvuKF9zkyYLKMhAaVUJipAAz6hxyJRop uq8eiGOrsWrxHcEvQr7lGCYqu1EXo/x8in0sRXLXyVLozQVcnfeeTO2Rsww== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 490e8a45xp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 10:41:28 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 588AfP4h011943; Mon, 8 Sep 2025 10:41:25 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 490e1kh0p7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 10:41:25 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 588AfP5h011937; Mon, 8 Sep 2025 10:41:25 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-sartgarg-hyd.qualcomm.com [10.147.242.251]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 588AfPnd011931 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 10:41:25 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 2339771) id 874725C9; Mon, 8 Sep 2025 16:11:24 +0530 (+0530) From: Sarthak Garg To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com, Sarthak Garg Subject: [PATCH V6 1/4] mmc: sdhci-msm: Enable tuning for SDR50 mode for SD card Date: Mon, 8 Sep 2025 16:11:19 +0530 Message-Id: <20250908104122.2062653-2-quic_sartgarg@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908104122.2062653-1-quic_sartgarg@quicinc.com> References: <20250908104122.2062653-1-quic_sartgarg@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=H7Dbw/Yi c=1 sm=1 tr=0 ts=68beb2d9 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=QyXUC8HyAAAA:8 a=nNGJRMnCL2qTWb1COHkA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: IboPzgCpELFk0LUG0c3m8SFRCeEuvsYO X-Proofpoint-ORIG-GUID: IboPzgCpELFk0LUG0c3m8SFRCeEuvsYO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAzOSBTYWx0ZWRfX4bA3Faubdllo 2WOmzH6H50yUjHtRg49pcfcCFjLn6FjKzkHMt8wozzbpupUU/DJkYyikRi1jtQp9ZlldxWeamrK ro3/7Sjnmm13nnuxKtVWtM6uXwyKg+I5wE1ZOsCyciXOLS4jM0ixwNKHWKghtfMEzj1pJo4Wpix pCXp0l866L92yNFGWg1RmsN7RU1Tk1Dxok7kA9OVJrJi9rNW57kNupgFBTtDDdtBo/jZZK+CNIw M/slv4s8sRvWH8RnJDnDckiObm+XQ2qCM+CjxR5mkg+jk7fgV0LI1/vK7aFz989Q3JiQJmr82jQ 5Z1TaqhlZ27ngcsfHx9l9qU3W//liujwDok65QQ81GerTgrbTdX0BGfPRiUd+Uyrq7ZJFed/vEl ydX+3jeZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_04,2025-09-08_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 impostorscore=0 adultscore=0 phishscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060039 Content-Type: text/plain; charset="utf-8" For Qualcomm SoCs which needs level shifter for SD card, extra delay is seen on receiver data path. To compensate this delay enable tuning for SDR50 mode for targets which has level shifter. SDHCI_SDR50_NEEDS_TUNING caps will be set for targets with level shifter on Qualcomm SOC's. Signed-off-by: Sarthak Garg Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-msm.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 66c0d1ba2a33..bf91cb96a0ea 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -81,6 +81,7 @@ #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15) #define CORE_IO_PAD_PWR_SWITCH BIT(16) #define CORE_HC_SELECT_IN_EN BIT(18) +#define CORE_HC_SELECT_IN_SDR50 (4 << 19) #define CORE_HC_SELECT_IN_HS400 (6 << 19) #define CORE_HC_SELECT_IN_MASK (7 << 19) =20 @@ -1133,6 +1134,10 @@ static bool sdhci_msm_is_tuning_needed(struct sdhci_= host *host) { struct mmc_ios *ios =3D &host->mmc->ios; =20 + if (ios->timing =3D=3D MMC_TIMING_UHS_SDR50 && + host->flags & SDHCI_SDR50_NEEDS_TUNING) + return true; + /* * Tuning is required for SDR104, HS200 and HS400 cards and * if clock frequency is greater than 100MHz in these modes. @@ -1201,6 +1206,8 @@ static int sdhci_msm_execute_tuning(struct mmc_host *= mmc, u32 opcode) struct mmc_ios ios =3D host->mmc->ios; struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + const struct sdhci_msm_offset *msm_offset =3D msm_host->offset; + u32 config; =20 if (!sdhci_msm_is_tuning_needed(host)) { msm_host->use_cdr =3D false; @@ -1217,6 +1224,14 @@ static int sdhci_msm_execute_tuning(struct mmc_host = *mmc, u32 opcode) */ msm_host->tuning_done =3D 0; =20 + if (ios.timing =3D=3D MMC_TIMING_UHS_SDR50 && + host->flags & SDHCI_SDR50_NEEDS_TUNING) { + config =3D readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); + config &=3D ~CORE_HC_SELECT_IN_MASK; + config |=3D CORE_HC_SELECT_IN_EN | CORE_HC_SELECT_IN_SDR50; + writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); + } + /* * For HS400 tuning in HS200 timing requires: * - select MCLK/2 in VENDOR_SPEC --=20 2.34.1 From nobody Fri Oct 3 01:59:34 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF14C2FF156; Mon, 8 Sep 2025 10:41:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757328100; cv=none; b=cA6X4v2viBSwNUMim8iz8Qz9eWBbG6zfs9ayD5z+HrOP4fLNkfGuGXB/O6/RX3c2Jfh9aeEmrN7/IBHxA6tL6xS6aA+3i2KO0KWuwxmYBiMzaBN7vojtYF4ZY0/qGMYa1uGStKsa1rJuAHqRTVgmNLRKwF6u7F0vFjRi/SblBtQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757328100; c=relaxed/simple; bh=uHbqBMASMEUeoLXv6a+wtLom/UknT3Is6tYXBjdurDA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=olcBv1GCHCHKLQ+/0fr8tAwzd06kyISLYL8qpkGpPXoQdHQLX+yzQgHCpIuPjXyLCOgqNO8fYhAmYP5bMtYIoX3jX0kgPRMG/Z1bxEa/nBv/3tbVzm6B01xeKVX18bvzt20dymn7ux0e9fo2I8NbiuF2Wd9yZSFBh2iKtlRi68k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=b3SL2IlO; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="b3SL2IlO" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588AXAYR013496; Mon, 8 Sep 2025 10:41:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=Zshuamdq2d2 s4GWDk/VefMB5jHdHIlBqew5eHum2enI=; b=b3SL2IlO+iBeFM6KfR3qMUmLLtS AbTHZEw4qshjcV9zsoIxX0gnn0LjxUFKjYYEqemyRUNANcwv4u59y+Df6WBKw7bl M8Eb6fit3vW7Be+Yx1F8sbOTP4MN4Z/awvjm2Nqoh6O3rOs5bfHR0wBz3X+cmH13 GrOxb+ArkKTCa3PfHkhiZ3ODfkwSAlfL4rzIUYwuBDoYpbtHhABPBB+2n97gAJBI E9ZQa4Wa081JGgTnIY1f5TXxTWYShmIV9I0JP2h6oQXrusgYwReWrFMJPqeXUWWT kDOdyM2npxgrlqXya0pj0MtSHGEvq1jjUJXHIXprg6e8O6ckgXh2JelNowQ== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 491qhds434-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 10:41:29 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 588AadZB005906; Mon, 8 Sep 2025 10:41:26 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 490e1kh0pe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 10:41:26 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 588AfQkj011949; Mon, 8 Sep 2025 10:41:26 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-sartgarg-hyd.qualcomm.com [10.147.242.251]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 588AfPP3011942 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 10:41:26 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 2339771) id ED2F75CB; Mon, 8 Sep 2025 16:11:24 +0530 (+0530) From: Sarthak Garg To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com, Sarthak Garg Subject: [PATCH V6 2/4] dt-bindings: mmc: controller: Add max-sd-hs-hz property Date: Mon, 8 Sep 2025 16:11:20 +0530 Message-Id: <20250908104122.2062653-3-quic_sartgarg@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908104122.2062653-1-quic_sartgarg@quicinc.com> References: <20250908104122.2062653-1-quic_sartgarg@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: OITx_P8SCXaxzcIoZJUllc6jMtcFQYx1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA4MDAzNCBTYWx0ZWRfX251i4Wye5WVJ kUtHNx/3hChrrC2lHJ7bHfi2WJ3e3IolZ6UQoIsBmVpHm6Z5CkMel138p35GZtPufZiCNjrskAh gE5ALbL37sXlUDIkMmL/jH1k0WqTum9adpa8k94NZGYzPxx9K78SMAg65hUmF/mp8M71m06yjpL 1SKyCHyAQxQlx5ZgnujonMw6HtNN3ioBXCSNOrtP4ixcgRLylf+JMK72pP0Ho1DPywYQKvJuLm3 vQscAEfR9lZhS0q3lHh/68Eldjc3Zlh/+nl6RTevHyhZ8txQBq0cnV01YvH7qLsnnogra1wKo7V fn6sXaQqkbzlkCmrySa6rI/23WoF9TC0SqOt+C2lztU3GXV/Nc61LxGo7JamN7tVRyNbrihfNps n3CNgzo7 X-Authority-Analysis: v=2.4 cv=YOCfyQGx c=1 sm=1 tr=0 ts=68beb2d9 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=mO_P381atgLiKTSE1XwA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: OITx_P8SCXaxzcIoZJUllc6jMtcFQYx1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_04,2025-09-08_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509080034 Content-Type: text/plain; charset="utf-8" Introduce a new optional device tree property max-sd-hs-hz to limit the maximum frequency (in Hz) used for SD cards operating in High-Speed (HS) mode due to any board electrical limitations. Signed-off-by: Sarthak Garg Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/mmc/mmc-controller-common.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.ya= ml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml index 9a7235439759..7414d5522dfe 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml @@ -93,6 +93,14 @@ properties: minimum: 400000 maximum: 384000000 =20 + max-sd-hs-hz: + description: | + Maximum frequency (in Hz) to be used for SD cards operating in + High-Speed (HS) mode. + minimum: 400000 + maximum: 50000000 + default: 50000000 + disable-wp: $ref: /schemas/types.yaml#/definitions/flag description: --=20 2.34.1 From nobody Fri Oct 3 01:59:34 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19F882FB0BD; Mon, 8 Sep 2025 10:41:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757328095; cv=none; b=Ia+GLaKq0fo6pM/QJzsWCTE/3A7c+ktqIp+Mn4k8PTO2BlM2KfvSd58h/YjwtBOzX202B7X0bP0zVzhkisBydShKC5Ty4pyV2NheKhoaFkI/7aC3v5mgoOTLKLmnAseMX5ffpWtkcIZbWhUn4rr8lVDEac62rWHCsMSgqcR8CqE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757328095; c=relaxed/simple; bh=FUARRciX/lPOwb+u/k38sbdjrKuteCm6oV+eHj81ni8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uA6inEc2/C7FfGO7udqs/z9fcLmUwc3UchB0NvbXhqKnQjEkFeBCbrs4LdMR+mDJ6B/mT+5VcuBUDo8EeKvsq5hg5COWpnOrlwZGFp5h6C2Rou0pYvnqmm0edoeiakb8BvnMb9xxZ/SV5wD0KalE8bFXGc0XktLHPsTIC0WCmDk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Nfgjh4OA; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Nfgjh4OA" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5883kcRW012371; Mon, 8 Sep 2025 10:41:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=z5Pg/8OyOGs N0BbJ4qq7Ha+TDpVFClfhMtzwnjCGRQY=; b=Nfgjh4OAQ2hYJ48IeYWkNdhKXQv 3qoTVGhUZJbOd6/fu72Qfwd4WqDgI7CcJXQrB8dpCy/jl8GNfdL1XrkOizqtzu+Y pgtodsLyh+tCsxlxZpgrzD0PQmqHlGHQ539bwPYze+wMOT+7rAHHCQCIf4QUGvI0 GdtEPkKVNz8zkAcIgOhcVAKSAjBzJcLSbzu49ejcnceNhMM/nmxNHb1RQDtc0rNm Sm1NLzqXsB+PNKhp041HCnCsfjP7xcfDxh8YjRmcWS7I4KJUTf+zlLvsGPk4Fbh/ oi848vxE0GyTE6jfJnJ1SHMUi9SDTfGtYgjvIWu1/yLRSNpecAWVliCXoJA== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 491qhds435-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 10:41:29 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 588Aadep005911; Mon, 8 Sep 2025 10:41:26 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 490e1kh0pj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 10:41:26 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 588AfQdF011965; Mon, 8 Sep 2025 10:41:26 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-sartgarg-hyd.qualcomm.com [10.147.242.251]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 588AfQdK011956 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 10:41:26 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 2339771) id 899505C5; Mon, 8 Sep 2025 16:11:25 +0530 (+0530) From: Sarthak Garg To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com, Sarthak Garg Subject: [PATCH V6 3/4] mmc: core: Introduce a new flag max-sd-hs-hz Date: Mon, 8 Sep 2025 16:11:21 +0530 Message-Id: <20250908104122.2062653-4-quic_sartgarg@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908104122.2062653-1-quic_sartgarg@quicinc.com> References: <20250908104122.2062653-1-quic_sartgarg@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: AOVhWyhSPIrpS9ddr-EgXNTtYzPNhrd2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA4MDAzNCBTYWx0ZWRfXz7ccATqxzyIj b/8eVnF1WLv0+FSqlIdW1MQ1lwi9MPYwX216/O2Ru7n6OA6T1xR7ge9tWu2OAnQkaPk1U/ChmIg KVAbz9gzqtXCZTlsVz1l9x3yGbYuwoiBENwRh5/dGOU1bLnemhirzySPMlQ7mx3qbQk2JIDOkC5 o2vhnQfGMqdW3vZ6ZzeUGEZJohw0pDnBIA6UpfIeT7eeHHrYu3OVIHtbrBGYMDH/87zTg6cChra FTJ9Qxlzz4XcO8GY0VYRsBcb+Ru1TdBWfhNa7Xcaq2fJWcTKvec8VIExO31Mwyr0Zvesb3cnSYH Q5mlh2T7ztCFTBNtip3udKYb//8X2NJ1fd8PX7KJJqjE4Fvtiqn+H5Oc/jOTRK5NAqcKbz5ewlT wlEh2CBB X-Authority-Analysis: v=2.4 cv=YOCfyQGx c=1 sm=1 tr=0 ts=68beb2da cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=Takt5cPIvt0sc2LuolQA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: AOVhWyhSPIrpS9ddr-EgXNTtYzPNhrd2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_04,2025-09-08_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 clxscore=1015 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509080034 Content-Type: text/plain; charset="utf-8" Introduce a new device tree flag to cap the maximum High-Speed (HS) mode frequency for SD cards, accommodating board-specific electrical limitations which cannot support the default 50Mhz HS frequency and others. Signed-off-by: Sarthak Garg --- drivers/mmc/core/host.c | 2 ++ drivers/mmc/core/sd.c | 2 +- include/linux/mmc/host.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index dacb5bd9bb71..3fe6ae56a6ae 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -302,6 +302,8 @@ int mmc_of_parse(struct mmc_host *host) /* f_max is obtained from the optional "max-frequency" property */ device_property_read_u32(dev, "max-frequency", &host->f_max); =20 + device_property_read_u32(dev, "max-sd-hs-hz", &host->max_sd_hs_hz); + /* * Configure CD and WP pins. They are both by default active low to * match the SDHCI spec. If GPIOs are provided for CD and / or WP, the diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index ec02067f03c5..67cd63004829 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -359,7 +359,7 @@ static int mmc_read_switch(struct mmc_card *card) } =20 if (status[13] & SD_MODE_HIGH_SPEED) - card->sw_caps.hs_max_dtr =3D HIGH_SPEED_MAX_DTR; + card->sw_caps.hs_max_dtr =3D card->host->max_sd_hs_hz ?: HIGH_SPEED_MAX_= DTR; =20 if (card->scr.sda_spec3) { card->sw_caps.sd3_bus_mode =3D status[13]; diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 68f09a955a90..a698b4b02d95 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -565,6 +565,7 @@ struct mmc_host { int hsq_depth; =20 u32 err_stats[MMC_ERR_MAX]; + unsigned int max_sd_hs_hz; unsigned long private[] ____cacheline_aligned; }; =20 --=20 2.34.1 From nobody Fri Oct 3 01:59:34 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83DF22FB98A; Mon, 8 Sep 2025 10:41:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757328096; cv=none; b=KAMEQV9D5gvDe01qvky5IgjLhYfiXYvTms/xIkTStfUjEDLB5O0ILpb/GivZnIb43NsYqmWe7OduGBmTbBD68/UYJdUH4lBLUD5+7i4azi506t1U7NpNvBPQ9fGUjnNWQEIk+tLYC2XEbRZ6aFromWCGqZg+VYLqBxz/BIKIvyU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757328096; c=relaxed/simple; bh=n37k02mn7bPQP7PANpV1lLKMpq4zNqjUT50z3+gM40s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gETYKgsCSlfrMAVKA3zmt5+Owiqcve++X0cWbkr2Osq8NBo4LRI6Ij7PIs0sXtT6JCVF+D2ZqKxvOIFZm2v+Z/gQNZ/s81ovRl5E3YWBdBU5uPPAlKskFlTYc9gg/LXk0tMx6/l2vGpTgH0a9MMbfF9daAybS94zNTJpF8FfWus= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=PJrcDL2q; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="PJrcDL2q" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 588915GG014127; Mon, 8 Sep 2025 10:41:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=iBjxeWvAjAp E7aIj6/oJL+rBWTiwT1U/SGuSGTnVP8k=; b=PJrcDL2q1mYVpgfD8zOz6/ZEAL4 tbw/KAqHq333dxrVKZC3XsseCXg6vwAUAJtaWnAnSoZ0JCOgRvkxyXp7wOWGxEGv rzA+GuqaWJ6GYKg9TNiuwfWRXzE3uFuJ8eh4uInHObJiuohc6EdL/mG0J5rR2Yrq EdX3heqZ8BlCMHsyaWgC9TSRo/hD7tWCGb90rynLskGY5vRe4xeOMf5zZT4PMAhr fX+Lk2YkVN131mq10JFbzbd5Qpbd9ukddWkopY1O7NAKGdg+dbxaFJ3wTr9V8Fsb 6+QM9EB00wwmRXUBVthofXFwxds/LHQm66Rxc8C1FD0wbkHi2kPv2H2Ck4g== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 490bws4dpr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 10:41:30 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 588AfSUJ011988; Mon, 8 Sep 2025 10:41:28 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 490e1kh0pq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 10:41:28 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 588AfRHq011981; Mon, 8 Sep 2025 10:41:27 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-sartgarg-hyd.qualcomm.com [10.147.242.251]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 588AfR1j011980 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Sep 2025 10:41:27 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 2339771) id AA8655C9; Mon, 8 Sep 2025 16:11:26 +0530 (+0530) From: Sarthak Garg To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com, Sarthak Garg Subject: [PATCH V6 4/4] arm64: dts: qcom: sm8550: Limit max SD HS mode frequency by default Date: Mon, 8 Sep 2025 16:11:22 +0530 Message-Id: <20250908104122.2062653-5-quic_sartgarg@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250908104122.2062653-1-quic_sartgarg@quicinc.com> References: <20250908104122.2062653-1-quic_sartgarg@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: vkxSwZXmKg0HvN-mCKZ6pq06Lse7xra6 X-Proofpoint-GUID: vkxSwZXmKg0HvN-mCKZ6pq06Lse7xra6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAxOCBTYWx0ZWRfX7VJaxySX45/j IoxT0irY6V6Pm0UWM85jC56fP4EvZwMu9gEjrUdXkEL76Vk8eSKwxnY19gpX6xak1cc3ZAKM2Hp qbV5LGkkzOd1MR1EJdgGlQCwtK7uTeRblchPXRmATEdrsvvNUEhL/6NpXD0b+Lh4VMOrc4fqP7C MPYWRpuyVzSnIRLUhCbjymWvRx+wCrRwmPRg9h5EwQySgyoSI1x/oQZK5/Y4w96h/3RaKaOr3P9 HNQVIrpfAU0gTPp/SrGJEpPbHILmWwcSJfIqS7x9Y2EyvNXRZjaY6ha2iYxWRxAUoPICeyv78Uc jgc2QhpHIntC1jLE7jfHJrrAxnrBMJPVettJj3ixjnGmHvRomDI8/GXUz/OPJUKH28JlPR6ZhSc pHfGJDtl X-Authority-Analysis: v=2.4 cv=G4kcE8k5 c=1 sm=1 tr=0 ts=68beb2db cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=gsFUoJjdds26VcGjwbYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_04,2025-09-08_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 bulkscore=0 suspectscore=0 clxscore=1015 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060018 Content-Type: text/plain; charset="utf-8" Due to an implementation detail in this SoC, additional passive electrical components are required to achieve the maximum rated speed of the SD controller when paired with a High-Speed SD Card. Without them, the clock frequency must be limited to 37.5 MHz for link stability. Because the reference design does not contain these components, most (derivative) boards do not have them either. To accommodate for that, apply the frequency limit by default and delegate lifting it to the odd boards that do contain the necessary onboard hardware. Signed-off-by: Sarthak Garg Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 82cabf777cd2..3692a3a49634 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3189,6 +3189,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; bus-width =3D <4>; + max-sd-hs-hz =3D <37500000>; dma-coherent; =20 /* Forbid SDR104/SDR50 - broken hw! */ --=20 2.34.1