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This brings the MCA init flow closer to what is described in the x86 docs. x86 docs: AMD Intel MCG_CTL MCA_CONFIG MCG_EXT_CTL MCi_CTL MCi_CTL MCG_CTL CR4.MCE CR4.MCE Current Linux: AMD Intel CR4.MCE CR4.MCE MCG_CTL MCG_CTL MCA_CONFIG MCG_EXT_CTL MCi_CTL MCi_CTL Updated Linux: AMD Intel MCG_CTL MCG_CTL MCA_CONFIG MCG_EXT_CTL MCi_CTL MCi_CTL CR4.MCE CR4.MCE The new init flow will match Intel's docs, but there will still be a mismatch for AMD regarding MCG_CTL. However, there is no known issue with this ordering, so leave it for now. Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-7-865768a2eef8@am= d.com =20 v5->v6: * Only move CR4.MCE programming. * Update commit message to match the new change. =20 v4->v5: * New in v5. arch/x86/kernel/cpu/mce/core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 0326fbb83adc..9e31834b3542 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1850,8 +1850,6 @@ static void __mcheck_cpu_init_generic(void) { u64 cap; =20 - cr4_set_bits(X86_CR4_MCE); - rdmsrq(MSR_IA32_MCG_CAP, cap); if (cap & MCG_CTL_P) wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); @@ -2276,6 +2274,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) __mcheck_cpu_init_vendor(c); __mcheck_cpu_init_prepare_banks(); __mcheck_cpu_setup_timer(); + cr4_set_bits(X86_CR4_MCE); } =20 /* @@ -2443,6 +2442,7 @@ static void mce_syscore_resume(void) __mcheck_cpu_init_generic(); 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However, a number of MCA initialization tasks only need to be done once. Define a function to collect all 'global' init tasks and call this from the BSP only. Start with CPU features. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-8-865768a2eef8@am= d.com =20 v5->v6: * No change. =20 v4->v5: * No change. =20 v3->v4: * Change cpu_mca_init() to mca_bsp_init(). * Drop code comment. =20 v2->v3: * Add tags from Qiuxu and Tony. =20 v1->v2: * New in v2. arch/x86/include/asm/mce.h | 2 ++ arch/x86/kernel/cpu/common.c | 1 + arch/x86/kernel/cpu/mce/amd.c | 3 --- arch/x86/kernel/cpu/mce/core.c | 28 +++++++++++++++++++++------- 4 files changed, 24 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 3224f3862dc8..31e3cb550fb3 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -241,12 +241,14 @@ struct cper_ia_proc_ctx; =20 #ifdef CONFIG_X86_MCE int mcheck_init(void); +void mca_bsp_init(struct cpuinfo_x86 *c); void mcheck_cpu_init(struct cpuinfo_x86 *c); void mcheck_cpu_clear(struct cpuinfo_x86 *c); int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id); #else static inline int mcheck_init(void) { return 0; } +static inline void mca_bsp_init(struct cpuinfo_x86 *c) {} static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {} static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_= info, diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 34a054181c4d..8bbfde05f04f 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1784,6 +1784,7 @@ static void __init early_identify_cpu(struct cpuinfo_= x86 *c) setup_clear_cpu_cap(X86_FEATURE_LA57); =20 detect_nopl(); + mca_bsp_init(c); } =20 void __init init_cpu_devs(void) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index aa13c9304ad8..3c6c19eb0a18 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -653,9 +653,6 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) u32 low =3D 0, high =3D 0, address =3D 0; int offset =3D -1; =20 - mce_flags.overflow_recov =3D cpu_feature_enabled(X86_FEATURE_OVERFLOW_REC= OV); - mce_flags.succor =3D cpu_feature_enabled(X86_FEATURE_SUCCOR); - mce_flags.smca =3D cpu_feature_enabled(X86_FEATURE_SMCA); mce_flags.amd_threshold =3D 1; =20 for (bank =3D 0; bank < this_cpu_read(mce_num_banks); ++bank) { diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 9e31834b3542..79f3dd7f7851 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1837,13 +1837,6 @@ static void __mcheck_cpu_cap_init(void) this_cpu_write(mce_num_banks, b); =20 __mcheck_cpu_mce_banks_init(); - - /* Use accurate RIP reporting if available. */ - if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >=3D 9) - mca_cfg.rip_msr =3D MSR_IA32_MCG_EIP; - - if (cap & MCG_SER_P) - mca_cfg.ser =3D 1; } =20 static void __mcheck_cpu_init_generic(void) @@ -2240,6 +2233,27 @@ DEFINE_IDTENTRY_RAW(exc_machine_check) } #endif =20 +void mca_bsp_init(struct cpuinfo_x86 *c) +{ + u64 cap; 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Mon, 8 Sep 2025 08:40:56 -0700 From: Yazen Ghannam Date: Mon, 8 Sep 2025 15:40:32 +0000 Subject: [PATCH v6 03/15] x86/mce: Define BSP-only SMCA init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250908-wip-mca-updates-v6-3-eef5d6c74b9c@amd.com> References: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> In-Reply-To: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> To: , Tony Luck , "Rafael J. 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However, the functions only need to be set once for the whole system. Assign the handlers only during BSP init. Do so only for SMCA systems to maintain the old behavior for legacy systems. Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-9-865768a2eef8@am= d.com =20 v5->v6: * No change. =20 v4->v5: * No change. =20 v3->v4: * Change mce_smca_cpu_init() to smca_bsp_init(). =20 v2->v3: * No change. =20 v1->v2: * New in v2. arch/x86/kernel/cpu/mce/amd.c | 6 ++++++ arch/x86/kernel/cpu/mce/core.c | 3 +++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ 3 files changed, 11 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 3c6c19eb0a18..7345e24bf658 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -684,6 +684,12 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) deferred_error_interrupt_enable(c); } =20 +void smca_bsp_init(void) +{ + mce_threshold_vector =3D amd_threshold_interrupt; + deferred_error_int_vector =3D amd_deferred_error_interrupt; +} + /* * DRAM ECC errors are reported in the Northbridge (bank 4) with * Extended Error Code 8. diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 79f3dd7f7851..a8cb7ff53e32 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2244,6 +2244,9 @@ void mca_bsp_init(struct cpuinfo_x86 *c) mce_flags.succor =3D cpu_feature_enabled(X86_FEATURE_SUCCOR); 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Mon, 8 Sep 2025 08:40:56 -0700 From: Yazen Ghannam Date: Mon, 8 Sep 2025 15:40:33 +0000 Subject: [PATCH v6 04/15] x86/mce: Do 'UNKNOWN' vendor check early Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250908-wip-mca-updates-v6-4-eef5d6c74b9c@amd.com> References: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> In-Reply-To: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> To: , Tony Luck , "Rafael J. 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However, all CPUs are expected to have the same vendor. Move the 'UNKNOWN' vendor check to the BSP-only init so it is done early and once. Remove the unnecessary return value from the quirks check. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-10-865768a2eef8@a= md.com =20 v5->v6: * No change. =20 v4->v5: * No change. =20 v3->v4: * No change. =20 v2->v3: * Add tags from Qiuxu and Tony. =20 v1->v2: * New in v2. arch/x86/kernel/cpu/mce/core.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index a8cb7ff53e32..515942cbfeb5 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1977,14 +1977,11 @@ static void apply_quirks_zhaoxin(struct cpuinfo_x86= *c) } =20 /* Add per CPU specific workarounds here */ -static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) +static void __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) { struct mca_config *cfg =3D &mca_cfg; =20 switch (c->x86_vendor) { - case X86_VENDOR_UNKNOWN: - pr_info("unknown CPU type - not enabling MCE support\n"); - return false; case X86_VENDOR_AMD: apply_quirks_amd(c); break; @@ -2000,8 +1997,6 @@ static bool __mcheck_cpu_apply_quirks(struct cpuinfo_= x86 *c) cfg->monarch_timeout =3D 0; if (cfg->bootlog !=3D 0) cfg->panic_timeout =3D 30; - - return true; } =20 static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) @@ -2240,6 +2235,12 @@ void mca_bsp_init(struct cpuinfo_x86 *c) if (!mce_available(c)) return; =20 + if (c->x86_vendor =3D=3D X86_VENDOR_UNKNOWN) { + mca_cfg.disabled =3D 1; + pr_info("unknown CPU type - not enabling MCE support\n"); + return; + } + mce_flags.overflow_recov =3D cpu_feature_enabled(X86_FEATURE_OVERFLOW_REC= OV); mce_flags.succor =3D cpu_feature_enabled(X86_FEATURE_SUCCOR); mce_flags.smca =3D cpu_feature_enabled(X86_FEATURE_SMCA); @@ -2274,10 +2275,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) =20 __mcheck_cpu_cap_init(); =20 - if (!__mcheck_cpu_apply_quirks(c)) { - mca_cfg.disabled =3D 1; - return; - } + __mcheck_cpu_apply_quirks(c); =20 if (!mce_gen_pool_init()) { mca_cfg.disabled =3D 1; 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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH3PEPF0000000E.mail.protection.outlook.com (10.167.244.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9115.13 via Frontend Transport; Mon, 8 Sep 2025 15:40:59 +0000 Received: from [127.0.1.1] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 8 Sep 2025 08:40:57 -0700 From: Yazen Ghannam Date: Mon, 8 Sep 2025 15:40:34 +0000 Subject: [PATCH v6 05/15] x86/mce: Separate global and per-CPU quirks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250908-wip-mca-updates-v6-5-eef5d6c74b9c@amd.com> References: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> In-Reply-To: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> To: , Tony Luck , "Rafael J. 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Move the per-CPU quirks to vendor init to execute them on each online CPU. Set the global quirks during BSP-only init so they're only executed once and early. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-11-865768a2eef8@a= md.com =20 v5->v6: * No change. =20 v4->v5: * Apply consistent naming to quirk functions. =20 v3->v4: * Add newline in mce_amd_feature_init(). * Remove __mcheck_cpu_apply_quirks(). * Update code comment ref. __mcheck_cpu_apply_quirks(). =20 v2->v3: * Update code comment. * Add tags from Qiuxu and Tony. =20 v1->v2: * New in v2. arch/x86/kernel/cpu/mce/amd.c | 24 ++++++++++++ arch/x86/kernel/cpu/mce/core.c | 85 +++++++++++--------------------------= ---- arch/x86/kernel/cpu/mce/intel.c | 18 +++++++++ 3 files changed, 65 insertions(+), 62 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 7345e24bf658..b8aed0ac765c 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -646,6 +646,28 @@ static void disable_err_thresholding(struct cpuinfo_x8= 6 *c, unsigned int bank) wrmsrq(MSR_K7_HWCR, hwcr); } =20 +static void amd_apply_cpu_quirks(struct cpuinfo_x86 *c) +{ + struct mce_bank *mce_banks =3D this_cpu_ptr(mce_banks_array); + + /* This should be disabled by the BIOS, but isn't always */ + if (c->x86 =3D=3D 15 && this_cpu_read(mce_num_banks) > 4) { + /* + * disable GART TBL walk error reporting, which + * trips off incorrectly with the IOMMU & 3ware + * & Cerberus: + */ + clear_bit(10, (unsigned long *)&mce_banks[4].ctl); + } + + /* + * Various K7s with broken bank 0 around. Always disable + * by default. + */ + if (c->x86 =3D=3D 6 && this_cpu_read(mce_num_banks)) + mce_banks[0].ctl =3D 0; +} + /* cpu init entry point, called from mce.c with preempt off */ void mce_amd_feature_init(struct cpuinfo_x86 *c) { @@ -653,6 +675,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) u32 low =3D 0, high =3D 0, address =3D 0; int offset =3D -1; =20 + amd_apply_cpu_quirks(c); + mce_flags.amd_threshold =3D 1; =20 for (bank =3D 0; bank < this_cpu_read(mce_num_banks); ++bank) { diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 515942cbfeb5..7fd86c8006ba 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1807,8 +1807,9 @@ static void __mcheck_cpu_mce_banks_init(void) struct mce_bank *b =3D &mce_banks[i]; =20 /* - * Init them all, __mcheck_cpu_apply_quirks() is going to apply - * the required vendor quirks before + * Init them all by default. + * + * The required vendor quirks will be applied before * __mcheck_cpu_init_prepare_banks() does the final bank setup. */ b->ctl =3D -1ULL; @@ -1880,20 +1881,8 @@ static void __mcheck_cpu_init_prepare_banks(void) } } =20 -static void apply_quirks_amd(struct cpuinfo_x86 *c) +static void amd_apply_global_quirks(struct cpuinfo_x86 *c) { - struct mce_bank *mce_banks =3D this_cpu_ptr(mce_banks_array); - - /* This should be disabled by the BIOS, but isn't always */ - if (c->x86 =3D=3D 15 && this_cpu_read(mce_num_banks) > 4) { - /* - * disable GART TBL walk error reporting, which - * trips off incorrectly with the IOMMU & 3ware - * & Cerberus: - */ - clear_bit(10, (unsigned long *)&mce_banks[4].ctl); - } - if (c->x86 < 0x11 && mca_cfg.bootlog < 0) { /* * Lots of broken BIOS around that don't clear them @@ -1902,13 +1891,6 @@ static void apply_quirks_amd(struct cpuinfo_x86 *c) mca_cfg.bootlog =3D 0; } =20 - /* - * Various K7s with broken bank 0 around. Always disable - * by default. - */ - if (c->x86 =3D=3D 6 && this_cpu_read(mce_num_banks)) - mce_banks[0].ctl =3D 0; - /* * overflow_recov is supported for F15h Models 00h-0fh * even though we don't have a CPUID bit for it. @@ -1920,25 +1902,12 @@ static void apply_quirks_amd(struct cpuinfo_x86 *c) mce_flags.zen_ifu_quirk =3D 1; } =20 -static void apply_quirks_intel(struct cpuinfo_x86 *c) +static void intel_apply_global_quirks(struct cpuinfo_x86 *c) { - struct mce_bank *mce_banks =3D this_cpu_ptr(mce_banks_array); - /* Older CPUs (prior to family 6) don't need quirks. */ if (c->x86_vfm < INTEL_PENTIUM_PRO) return; =20 - /* - * SDM documents that on family 6 bank 0 should not be written - * because it aliases to another special BIOS controlled - * register. - * But it's not aliased anymore on model 0x1a+ - * Don't ignore bank 0 completely because there could be a - * valid event later, merely don't write CTL0. - */ - if (c->x86_vfm < INTEL_NEHALEM_EP && this_cpu_read(mce_num_banks)) - mce_banks[0].init =3D false; - /* * All newer Intel systems support MCE broadcasting. Enable * synchronization with a one second timeout. @@ -1964,7 +1933,7 @@ static void apply_quirks_intel(struct cpuinfo_x86 *c) mce_flags.skx_repmov_quirk =3D 1; } =20 -static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c) +static void zhaoxin_apply_global_quirks(struct cpuinfo_x86 *c) { /* * All newer Zhaoxin CPUs support MCE broadcasting. Enable @@ -1976,29 +1945,6 @@ static void apply_quirks_zhaoxin(struct cpuinfo_x86 = *c) } } =20 -/* Add per CPU specific workarounds here */ -static void __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) -{ - struct mca_config *cfg =3D &mca_cfg; - - switch (c->x86_vendor) { - case X86_VENDOR_AMD: - apply_quirks_amd(c); - break; - case X86_VENDOR_INTEL: - apply_quirks_intel(c); - break; - case X86_VENDOR_ZHAOXIN: - apply_quirks_zhaoxin(c); - break; - } - - if (cfg->monarch_timeout < 0) - cfg->monarch_timeout =3D 0; - if (cfg->bootlog !=3D 0) - cfg->panic_timeout =3D 30; -} - static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) { if (c->x86 !=3D 5) @@ -2256,6 +2202,23 @@ void mca_bsp_init(struct cpuinfo_x86 *c) =20 if (cap & MCG_SER_P) mca_cfg.ser =3D 1; + + switch (c->x86_vendor) { + case X86_VENDOR_AMD: + amd_apply_global_quirks(c); + break; + case X86_VENDOR_INTEL: + intel_apply_global_quirks(c); + break; + case X86_VENDOR_ZHAOXIN: + zhaoxin_apply_global_quirks(c); + break; + } + + if (mca_cfg.monarch_timeout < 0) + mca_cfg.monarch_timeout =3D 0; + if (mca_cfg.bootlog !=3D 0) + mca_cfg.panic_timeout =3D 30; } =20 /* @@ -2275,8 +2238,6 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) =20 __mcheck_cpu_cap_init(); =20 - __mcheck_cpu_apply_quirks(c); - if (!mce_gen_pool_init()) { mca_cfg.disabled =3D 1; pr_emerg("Couldn't allocate MCE records pool!\n"); diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/inte= l.c index 9b149b9c4109..4655223ba560 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -468,8 +468,26 @@ static void intel_imc_init(struct cpuinfo_x86 *c) } } =20 +static void intel_apply_cpu_quirks(struct cpuinfo_x86 *c) +{ + /* + * SDM documents that on family 6 bank 0 should not be written + * because it aliases to another special BIOS controlled + * register. + * But it's not aliased anymore on model 0x1a+ + * Don't ignore bank 0 completely because there could be a + * valid event later, merely don't write CTL0. + * + * Older CPUs (prior to family 6) can't reach this point and already + * return early due to the check of __mcheck_cpu_ancient_init(). + */ + if (c->x86_vfm < INTEL_NEHALEM_EP && this_cpu_read(mce_num_banks)) + this_cpu_ptr(mce_banks_array)[0].init =3D false; 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These are used to determine if an error should be skipped. Move these into helper functions. Future vendor-specific checks will be added to the helpers. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-12-865768a2eef8@a= md.com =20 v5->v6: * No change. =20 v4->v5: * No change. =20 v3->v4: * No change. =20 v2->v3: * Add tags from Qiuxu and Tony. =20 v1->v2: * Change log_poll_error() to should_log_poll_error(). * Keep code comment. arch/x86/kernel/cpu/mce/core.c | 88 +++++++++++++++++++++++---------------= ---- 1 file changed, 48 insertions(+), 40 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 7fd86c8006ba..5dec0da6169e 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -714,6 +714,52 @@ static noinstr void mce_read_aux(struct mce_hw_err *er= r, int i) =20 DEFINE_PER_CPU(unsigned, mce_poll_count); =20 +/* + * Newer Intel systems that support software error + * recovery need to make additional checks. Other + * CPUs should skip over uncorrected errors, but log + * everything else. + */ +static bool ser_should_log_poll_error(struct mce *m) +{ + /* Log "not enabled" (speculative) errors */ + if (!(m->status & MCI_STATUS_EN)) + return true; + + /* + * Log UCNA (SDM: 15.6.3 "UCR Error Classification") + * UC =3D=3D 1 && PCC =3D=3D 0 && S =3D=3D 0 + */ + if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S)) + return true; + + return false; +} + +static bool should_log_poll_error(enum mcp_flags flags, struct mce_hw_err = *err) +{ + struct mce *m =3D &err->m; + + /* If this entry is not valid, ignore it. */ + if (!(m->status & MCI_STATUS_VAL)) + return false; + + /* + * If we are logging everything (at CPU online) or this + * is a corrected error, then we must log it. + */ + if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC)) + return true; + + if (mca_cfg.ser) + return ser_should_log_poll_error(m); + + if (m->status & MCI_STATUS_UC) + return false; + + return true; +} + /* * Poll for corrected events or events that happened before reset. * Those are just logged through /dev/mcelog. @@ -765,48 +811,10 @@ void machine_check_poll(enum mcp_flags flags, mce_ban= ks_t *b) if (!mca_cfg.cmci_disabled) mce_track_storm(m); =20 - /* If this entry is not valid, ignore it */ - if (!(m->status & MCI_STATUS_VAL)) + /* Verify that the error should be logged based on hardware conditions. = */ + if (!should_log_poll_error(flags, &err)) continue; =20 - /* - * If we are logging everything (at CPU online) or this - * is a corrected error, then we must log it. - */ - if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC)) - goto log_it; - - /* - * Newer Intel systems that support software error - * recovery need to make additional checks. Other - * CPUs should skip over uncorrected errors, but log - * everything else. - */ - if (!mca_cfg.ser) { - if (m->status & MCI_STATUS_UC) - continue; - goto log_it; - } - - /* Log "not enabled" (speculative) errors */ - if (!(m->status & MCI_STATUS_EN)) - goto log_it; - - /* - * Log UCNA (SDM: 15.6.3 "UCR Error Classification") - * UC =3D=3D 1 && PCC =3D=3D 0 && S =3D=3D 0 - */ - if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S)) - goto log_it; - - /* - * Skip anything else. Presumption is that our read of this - * bank is racing with a machine check. Leave the log alone - * for do_machine_check() to deal with it. - */ - continue; - -log_it: mce_read_aux(&err, i); m->severity =3D mce_severity(m, NULL, NULL, false); /* --=20 2.51.0 From nobody Wed Sep 10 01:54:43 2025 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2068.outbound.protection.outlook.com [40.107.220.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D796230F541; Mon, 8 Sep 2025 15:41:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.68 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757346065; cv=fail; b=Ns0Fq5g9MbDx8LBKpSaVAJ4VslyTq+2c9juKe+tiR3UYauzy5MRJPFi5WBD4qISTX5+rA4t0r0/sAZTWzcXHyvduiGLh7iB4JlD1D0ScitL8RFiJehwe7JX2ZqXuMUGZWwEPu3IP+f2CjTzydDp1pH/Fgqj1IHBmAFrxd6imwQI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757346065; 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Start with a basic skeleton for now. Actions for AMD thresholding and deferred errors will be added later. Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250903094859.GGaLgPC_eWQgAqpHHb@fat_crate.l= ocal =20 v5->v6: * New in v6. arch/x86/kernel/cpu/mce/amd.c | 5 +++++ arch/x86/kernel/cpu/mce/core.c | 12 ++++++++++-- arch/x86/kernel/cpu/mce/internal.h | 3 +++ 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index b8aed0ac765c..d6906442f49b 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -955,6 +955,11 @@ static void amd_threshold_interrupt(void) } } =20 +void amd_clear_bank(struct mce *m) +{ + mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0); +} + /* * Sysfs Interface */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 5dec0da6169e..06645f56b564 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -423,7 +423,7 @@ noinstr u64 mce_rdmsrq(u32 msr) return EAX_EDX_VAL(val, low, high); } =20 -static noinstr void mce_wrmsrq(u32 msr, u64 v) +noinstr void mce_wrmsrq(u32 msr, u64 v) { u32 low, high; =20 @@ -760,6 +760,14 @@ static bool should_log_poll_error(enum mcp_flags flags= , struct mce_hw_err *err) return true; } =20 +static void clear_bank(struct mce *m) +{ + if (m->cpuvendor =3D=3D X86_VENDOR_AMD) + return amd_clear_bank(m); + + mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0); +} + /* * Poll for corrected events or events that happened before reset. * Those are just logged through /dev/mcelog. @@ -834,7 +842,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks= _t *b) /* * Clear state for this bank. */ - mce_wrmsrq(mca_msr_reg(i, MCA_STATUS), 0); + clear_bank(m); } =20 /* diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/i= nternal.h index 6cb2995f0ec1..b0e00ec5cc8c 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -269,6 +269,7 @@ void mce_threshold_create_device(unsigned int cpu); void mce_threshold_remove_device(unsigned int cpu); extern bool amd_filter_mce(struct mce *m); bool amd_mce_usable_address(struct mce *m); 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Mon, 8 Sep 2025 08:40:59 -0700 From: Yazen Ghannam Date: Mon, 8 Sep 2025 15:40:37 +0000 Subject: [PATCH v6 08/15] x86/mce: Unify AMD THR handler with MCA Polling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250908-wip-mca-updates-v6-8-eef5d6c74b9c@amd.com> References: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> In-Reply-To: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> To: , Tony Luck , "Rafael J. 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The interrupt should be used as another signal to trigger MCA polling. This is similar to how the Intel Corrected Machine Check interrupt (CMCI) is handled. AMD MCA thresholding is managed using the MCA_MISC registers within an MCA bank. The OS will need to modify the hardware error count field in order to reset the threshold limit and rearm the interrupt. Management of the MCA_MISC register should be done as a follow up to the basic MCA polling flow. It should not be the main focus of the interrupt handler. Furthermore, future systems will have the ability to send an MCA thresholding interrupt to the OS even when the OS does not manage the feature, i.e. MCA_MISC registers are Read-as-Zero/Locked. Call the common MCA polling function when handling the MCA thresholding interrupt. This will allow the OS to find any valid errors whether or not the MCA thresholding feature is OS-managed. Also, this allows the common MCA polling options and kernel parameters to apply to AMD systems. Add a callback to the MCA polling function to check and reset any threshold blocks that have reached their threshold limit. Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-13-865768a2eef8@a= md.com =20 v5->v6: * Move bank/block reset code to new helper. =20 v4->v5: * No change. =20 v3->v4: * No change. =20 v2->v3: * Add tags from Qiuxu and Tony. =20 v1->v2: * Start collecting per-CPU items in a struct. * Keep and use mce_flags.amd_threshold. arch/x86/kernel/cpu/mce/amd.c | 51 +++++++++++++++++++--------------------= ---- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index d6906442f49b..ac6a98aa7bc2 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -54,6 +54,12 @@ =20 static bool thresholding_irq_en; =20 +struct mce_amd_cpu_data { + mce_banks_t thr_intr_banks; +}; + +static DEFINE_PER_CPU_READ_MOSTLY(struct mce_amd_cpu_data, mce_amd_data); + static const char * const th_names[] =3D { "load_store", "insn_fetch", @@ -556,6 +562,7 @@ prepare_threshold_block(unsigned int bank, unsigned int= block, u32 addr, if (!b.interrupt_capable) goto done; =20 + __set_bit(bank, this_cpu_ptr(&mce_amd_data)->thr_intr_banks); b.interrupt_enable =3D 1; =20 if (!mce_flags.smca) { @@ -896,12 +903,7 @@ static void amd_deferred_error_interrupt(void) log_error_deferred(bank); } =20 -static void log_error_thresholding(unsigned int bank, u64 misc) -{ - _log_error_deferred(bank, misc); -} - -static void log_and_reset_block(struct threshold_block *block) +static void reset_block(struct threshold_block *block) { struct thresh_restart tr; u32 low =3D 0, high =3D 0; @@ -915,23 +917,14 @@ static void log_and_reset_block(struct threshold_bloc= k *block) if (!(high & MASK_OVERFLOW_HI)) return; =20 - /* Log the MCE which caused the threshold event. */ - log_error_thresholding(block->bank, ((u64)high << 32) | low); - - /* Reset threshold block after logging error. */ memset(&tr, 0, sizeof(tr)); tr.b =3D block; threshold_restart_block(&tr); } =20 -/* - * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The int= errupt - * goes off when error_count reaches threshold_limit. - */ -static void amd_threshold_interrupt(void) +static void amd_reset_thr_limit(unsigned int bank) { - struct threshold_bank **bp =3D this_cpu_read(threshold_banks), *thr_bank; - unsigned int bank, cpu =3D smp_processor_id(); + struct threshold_bank **bp =3D this_cpu_read(threshold_banks); struct threshold_block *block, *tmp; =20 /* @@ -939,24 +932,26 @@ static void amd_threshold_interrupt(void) * handler is installed at boot time, but on a hotplug event the * interrupt might fire before the data has been initialized. */ - if (!bp) + if (!bp || !bp[bank]) return; =20 - for (bank =3D 0; bank < this_cpu_read(mce_num_banks); ++bank) { - if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank))) - continue; - - thr_bank =3D bp[bank]; - if (!thr_bank) - continue; + list_for_each_entry_safe(block, tmp, &bp[bank]->miscj, miscj) + reset_block(block); +} =20 - list_for_each_entry_safe(block, tmp, &thr_bank->miscj, miscj) - log_and_reset_block(block); - } +/* + * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250908-wip-mca-updates-v6-9-eef5d6c74b9c@amd.com> References: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> In-Reply-To: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> To: , Tony Luck , "Rafael J. Wysocki" CC: , , , Qiuxu Zhuo , Nikolay Borisov , , "Yazen Ghannam" X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000E:EE_|DM4PR12MB6351:EE_ X-MS-Office365-Filtering-Correlation-Id: 67a47138-fff9-4e27-18f2-08ddeeee20cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013|13003099007; X-Microsoft-Antispam-Message-Info: =?utf-8?B?Nm9oWThmNys4V2Vwd3hybFk1c1JoRGFGY00wbHFnOW1VRnd1Y2xGS2tTNkNJ?= =?utf-8?B?VjlxbGFEYkx5ZXpRRXkvSUVrdFZPRnZQWXNOakZyVWYyMGtkRm1MemdvVitu?= =?utf-8?B?QlFWSFVoVExkdW9iQTM1ZWxnYm1kZlpocHZOZmExMDUzTE1jY01sM1ZKS3Q4?= =?utf-8?B?VXdzNVYwV0VoZ2VRK3NyUWhLeVJVWkJxdlpRYk5XNGozQWNFUHVrRVhOL2RT?= =?utf-8?B?RTNjY3JEZTJuL1J1WEVaejk3ZHM0bWFzWTNnK3Vad0orY0dvbE43dDlzQzRL?= =?utf-8?B?cGg5K1hoeWtWeVdTTktPZFpkd3cvVkk1V2tEQnVrS3kwc1RqNm92Z3ovZWZv?= =?utf-8?B?Mko2UmpYNzNHQlJFWXhFWjJsUmZDamxDYml1T3FNZTdVUmI1eWxvQ21iVWxk?= =?utf-8?B?b2s5Rk4rcm1iZ0lGTmJ6dW5Oc3BocC9zK0N5Qlgxc2c0ZGlYcGpWMkE5bmh3?= =?utf-8?B?aHN3NGI0TjBDUXRzWWJybVB1aGN4OHVMbGc5OEk0YnRHSlNKRmJZc2Q3TWxl?= =?utf-8?B?VDRmdFhvVW8vaC83bXBscHZHL052V2lXaitZYit5TXNQVzMzZVdTLzR2OEdQ?= =?utf-8?B?dTBlWlBmbTVzQ1pxSllYT05uOHBDbXQ0TTF1L2FvTTBoN0FvZisxeUZ4MEZI?= =?utf-8?B?Ui9MNkg1MUgwK1ZqcjJNZDczYVhYSzBhN1hqQS9uelh5TnBmRmhXb2dIZTA1?= =?utf-8?B?UmZmMkw4SzMrVjEzQXBjSUZkR01Wd2lCWldGbU5tNUYvdHNyNFJleUZxeTRC?= =?utf-8?B?RGZuVEx2SWxxaFZVWkpIWFZSYnpkMFRuLzZWOVpoemdOS2txRDhlQzJEWWdt?= =?utf-8?B?MnkyTHEvRWJFekFJVXhiVkl1bjFZNjVkaGZvN1RwK29GbVlrU05LVmVsSzhN?= =?utf-8?B?S1RFc1ZOVXB1UGhGMzFvMWNDa0llRDRXOWtmbCtHMHBSWW5RRStCSkY1QWJP?= =?utf-8?B?c3pCSDVPWWJKSlI1RFpkT21ZcER2enV6RWlNSVlQRFZlRk5va2hJd29YcmF0?= =?utf-8?B?S2czVXdUb1RKOTRCZFZGMlJmR0lqdUx1VEhyWXdVdDRSUUloVkpQMHdlODk0?= =?utf-8?B?dElBVktUbnovbkhFMEVkN1dTWFRGTFZwbjF6Rmk4WWRPV1EzUWwrRzkxWXZy?= =?utf-8?B?MllFOU1HcnVMNlhLaDREcURNalppdVRqcGFlMlJKeDhRN0t2QThjVWEzNW1a?= =?utf-8?B?bDZrTDFPbUlzOXVvVkNXZXRzeDBiMy9nUFhtTnRrWnZZaThSMTZIZ0UvRmN2?= =?utf-8?B?WjRLUGNQQlhnU2lZTlpQM1dCN1pwT0p4d1A1S0JzME4vaDNkYi9jdVNVVzFu?= =?utf-8?B?bU4wSFUwWGlqVVhIdlpzYmRwRHYyMitzN0VRUVhyVDlSdktLOXRhemVQdXgv?= =?utf-8?B?SEJzeEVxUmtPZ1lLUkh5ZkNwaDBGMmtwZDI2ZlVJL1p0VkhCdTdONGkyRFhl?= =?utf-8?B?MXJXUmU3a1Y0ZzQ3dWVTNDEzU2QxUVlieWk2YVNHUnpkZlVRbFd4S01IS0x5?= =?utf-8?B?OUwxWXplMVRmZEh1NlpHU2hZU0RKYVZycSs2NDF6VDhVQzdTYUZlUmNRdisr?= =?utf-8?B?cHgxUW5FRUNXaXZwV0Z4RU1URzU4b3VERnV1Y0x4MWN2VzhXYllJRDAxRWZX?= =?utf-8?B?UjhEdzdnY29ENUl5SWRDK1ErbS90bFV0NHN3dWd0NVo1bnllQzBiUWh4eVRL?= =?utf-8?B?dDlUV3JzaUFaRGpmSWh0Y3diYUtKc3Vzb011NFc5R252c3ZKYjBNNnVMamE4?= =?utf-8?B?ak16NEpTYzJVNkgyYmY2OEFoZnB6d0xzYi9iV0E5L09tTlM4NXk4Vm5qcCt2?= =?utf-8?B?TXRpMkZSczEzakdYNlFoNEtxcXhOS3BhbFI3Rnh0TDB3eC9SVzRNNm1BekhO?= =?utf-8?B?MU9DdFIzbDU4R0MxVWEyWnpoSlBLUkZwSGxZNFMrYzJpbHN5MHBxMHFNdTZF?= =?utf-8?B?aVFnZ1kvbUlleVhYakJydTJub0hka3FYcEZ1SG9NU2hHRjFvWlkrdXFqUGdy?= =?utf-8?B?SkIxbFpUSDBxUnhXQzgyd0RwYUg4ckJXNmc5UzFQa2dwbXF5UldmTDZXNGNr?= =?utf-8?B?NEF5ZDExb3R6NExDcStidmtzUnhvMmErQVp6Zz09?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 15:41:07.5804 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 67a47138-fff9-4e27-18f2-08ddeeee20cc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6351 AMD systems optionally support a deferred error interrupt. The interrupt should be used as another signal to trigger MCA polling. This is similar to how other MCA interrupts are handled. Deferred errors do not require any special handling related to the interrupt, e.g. resetting or rearming the interrupt, etc. However, Scalable MCA systems include a pair of registers, MCA_DESTAT and MCA_DEADDR, that should be checked for valid errors. This check should be done whenever MCA registers are polled. Currently, the deferred error interrupt does this check, but the MCA polling function does not. Call the MCA polling function when handling the deferred error interrupt. This keeps all "polling" cases in a common function. Call the polling function only for banks that have the deferred error interrupt enabled. Add an SMCA status check helper. This will do the same status check and register clearing that the interrupt handler has done. And it extends the common polling flow to find AMD deferred errors. Remove old code whose functionality is already covered in the common MCA code. Reviewed-by: Qiuxu Zhuo Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-14-865768a2eef8@a= md.com =20 v5->v6: * Move status clearing code to new helper. =20 v4->v5: * No change. =20 v3->v4: * Add kflag for checking DFR registers. =20 v2->v3: * Add tags from Qiuxu and Tony. =20 v1->v2: * Keep code comment. * Log directly from helper function rather than pass values. =20 Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-13-3636547fe05f@a= md.com =20 v2->v3: * Add tags from Qiuxu and Tony. =20 v1->v2: * Keep code comment. * Log directly from helper function rather than pass values. arch/x86/include/asm/mce.h | 6 +++ arch/x86/kernel/cpu/mce/amd.c | 108 ++++---------------------------------= ---- arch/x86/kernel/cpu/mce/core.c | 45 ++++++++++++++++- 3 files changed, 59 insertions(+), 100 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 31e3cb550fb3..7d6588195d56 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -165,6 +165,12 @@ */ #define MCE_IN_KERNEL_COPYIN BIT_ULL(7) =20 +/* + * Indicates that handler should check and clear Deferred error registers + * rather than common ones. + */ +#define MCE_CHECK_DFR_REGS BIT_ULL(8) + /* * This structure contains all data related to the MCE log. Also * carries a signature to make it easier to find from external diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index ac6a98aa7bc2..1b1b83b3aef9 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -56,6 +56,7 @@ static bool thresholding_irq_en; =20 struct mce_amd_cpu_data { mce_banks_t thr_intr_banks; + mce_banks_t dfr_intr_banks; }; =20 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_amd_cpu_data, mce_amd_data); @@ -300,8 +301,10 @@ static void smca_configure(unsigned int bank, unsigned= int cpu) * APIC based interrupt. First, check that no interrupt has been * set. */ - if ((low & BIT(5)) && !((high >> 5) & 0x3)) + if ((low & BIT(5)) && !((high >> 5) & 0x3)) { + __set_bit(bank, this_cpu_ptr(&mce_amd_data)->dfr_intr_banks); high |=3D BIT(5); + } =20 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status =3D !!(low & BIT(8)); =20 @@ -792,37 +795,6 @@ bool amd_mce_usable_address(struct mce *m) return false; } =20 -static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) -{ - struct mce_hw_err err; - struct mce *m =3D &err.m; - - mce_prep_record(&err); - - m->status =3D status; - m->misc =3D misc; - m->bank =3D bank; - m->tsc =3D rdtsc(); - - if (m->status & MCI_STATUS_ADDRV) { - m->addr =3D addr; - - smca_extract_err_addr(m); - } - - if (mce_flags.smca) { - rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid); - - if (m->status & MCI_STATUS_SYNDV) { - rdmsrq(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd); - rdmsrq(MSR_AMD64_SMCA_MCx_SYND1(bank), err.vendor.amd.synd1); - rdmsrq(MSR_AMD64_SMCA_MCx_SYND2(bank), err.vendor.amd.synd2); - } - } - - mce_log(&err); -} - DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) { trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); @@ -832,75 +804,10 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) apic_eoi(); } =20 -/* - * Returns true if the logged error is deferred. False, otherwise. - */ -static inline bool -_log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) -{ - u64 status, addr =3D 0; - - rdmsrq(msr_stat, status); - if (!(status & MCI_STATUS_VAL)) - return false; - - if (status & MCI_STATUS_ADDRV) - rdmsrq(msr_addr, addr); - - __log_error(bank, status, addr, misc); - - wrmsrq(msr_stat, 0); - - return status & MCI_STATUS_DEFERRED; -} - -static bool _log_error_deferred(unsigned int bank, u32 misc) -{ - if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), - mca_msr_reg(bank, MCA_ADDR), misc)) - return false; - - /* - * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers. - * Return true here to avoid accessing these registers. - */ - if (!mce_flags.smca) - return true; - - /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */ - wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); - return true; -} - -/* - * We have three scenarios for checking for Deferred errors: - * - * 1) Non-SMCA systems check MCA_STATUS and log error if found. - * 2) SMCA systems check MCA_STATUS. If error is found then log it and also - * clear MCA_DESTAT. - * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS,= and - * log it. - */ -static void log_error_deferred(unsigned int bank) -{ - if (_log_error_deferred(bank, 0)) - return; - - /* - * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check - * for a valid error. - */ - _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), - MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); -} - /* APIC interrupt handler for deferred errors */ static void amd_deferred_error_interrupt(void) { - unsigned int bank; - - for (bank =3D 0; bank < this_cpu_read(mce_num_banks); ++bank) - log_error_deferred(bank); + machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->dfr_intr_= banks); } =20 static void reset_block(struct threshold_block *block) @@ -952,7 +859,10 @@ void amd_clear_bank(struct mce *m) { amd_reset_thr_limit(m->bank); =20 - mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0); + if (m->kflags & MCE_CHECK_DFR_REGS) + mce_wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0); + else + mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0); } =20 /* diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 06645f56b564..e2d51609d2cb 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -687,7 +687,10 @@ static noinstr void mce_read_aux(struct mce_hw_err *er= r, int i) m->misc =3D mce_rdmsrq(mca_msr_reg(i, MCA_MISC)); =20 if (m->status & MCI_STATUS_ADDRV) { - m->addr =3D mce_rdmsrq(mca_msr_reg(i, MCA_ADDR)); + if (m->kflags & MCE_CHECK_DFR_REGS) + m->addr =3D mce_rdmsrq(MSR_AMD64_SMCA_MCx_DEADDR(i)); + else + m->addr =3D mce_rdmsrq(mca_msr_reg(i, MCA_ADDR)); =20 /* * Mask the reported address by the reported granularity. @@ -714,6 +717,43 @@ static noinstr void mce_read_aux(struct mce_hw_err *er= r, int i) =20 DEFINE_PER_CPU(unsigned, mce_poll_count); =20 +/* + * We have three scenarios for checking for Deferred errors: + * + * 1) Non-SMCA systems check MCA_STATUS and log error if found. + * 2) SMCA systems check MCA_STATUS. If error is found then log it and also + * clear MCA_DESTAT. + * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS,= and + * log it. + */ +static bool smca_should_log_poll_error(enum mcp_flags flags, struct mce_hw= _err *err) +{ + struct mce *m =3D &err->m; + + /* + * If this is a deferred error found in MCA_STATUS, then clear + * the redundant data from the MCA_DESTAT register. + */ + if (m->status & MCI_STATUS_VAL) { + if (m->status & MCI_STATUS_DEFERRED) + mce_wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0); + + return true; + } + + /* + * If the MCA_DESTAT register has valid data, then use + * it as the status register. + */ + m->status =3D mce_rdmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank)); + + if (!(m->status & MCI_STATUS_VAL)) + return false; + + m->kflags |=3D MCE_CHECK_DFR_REGS; + return true; +} + /* * Newer Intel systems that support software error * recovery need to make additional checks. Other @@ -740,6 +780,9 @@ static bool should_log_poll_error(enum mcp_flags flags,= struct mce_hw_err *err) { struct mce *m =3D &err->m; =20 + if (mce_flags.smca) + return smca_should_log_poll_error(flags, err); + /* If this entry is not valid, ignore it. */ if (!(m->status & MCI_STATUS_VAL)) return false; --=20 2.51.0 From nobody Wed Sep 10 01:54:43 2025 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2046.outbound.protection.outlook.com [40.107.212.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A75FE30F94A; Mon, 8 Sep 2025 15:41:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.212.46 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757346073; cv=fail; b=NuDSAGlHF4tDeejOGbq3JfW9dUyJeOcg/tSb3Up0UXTIvXvcTluKrzqHYM6n9VI3wD1CuTIRMlFHvXWKNog6d3oCjL5EVbtrCqVDbX+uW6oS9QNG8EoQ8qttyJtemyYgqiP37vBiqMR0bT9EcYJFqRZD3K2O68nZbJFfgBb7Inc= ARC-Message-Signature: i=2; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250908-wip-mca-updates-v6-10-eef5d6c74b9c@amd.com> References: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> In-Reply-To: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> To: , Tony Luck , "Rafael J. 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Currently, this register is read once to set up the deferred error interrupt and then read again for each thresholding block. Furthermore, the APIC LVT registers are configured each time, but they only need to be configured once per-CPU. Move the APIC LVT setup to the early part of CPU init, so that the registers are set up once. Also, this ensures that the kernel is ready to service the interrupts before the individual error sources (each MCA bank) are enabled. Apply this change only to SMCA systems to avoid breaking any legacy behavior. The deferred error interrupt is technically advertised by the SUCCOR feature. However, this was first made available on SMCA systems. Therefore, only set up the deferred error interrupt on SMCA systems and simplify the code. Guidance from hardware designers is that the LVT offsets provided from the platform should be used. The kernel should not try to enforce specific values. However, the kernel should check that an LVT offset is not reused for multiple sources. Therefore, remove the extra checking and value enforcement from the MCE code. The "reuse/conflict" case is already handled in setup_APIC_eilvt(). Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-15-865768a2eef8@a= md.com =20 v5->v6: * Applied "bools to flags" and other fixups from Boris. =20 v4->v5: * Added back to set. * Updated commit message with more details. =20 v3->v4: * Dropped from set. =20 v2->v3: * Add tags from Tony. =20 v1->v2: * Use new per-CPU struct. * Don't set up interrupt vectors. arch/x86/kernel/cpu/mce/amd.c | 121 ++++++++++++++++++--------------------= ---- 1 file changed, 53 insertions(+), 68 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 1b1b83b3aef9..a6f5c9339d7c 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -43,9 +43,6 @@ /* Deferred error settings */ #define MSR_CU_DEF_ERR 0xC0000410 #define MASK_DEF_LVTOFF 0x000000F0 -#define MASK_DEF_INT_TYPE 0x00000006 -#define DEF_LVT_OFF 0x2 -#define DEF_INT_TYPE_APIC 0x2 =20 /* Scalable MCA: */ =20 @@ -57,6 +54,10 @@ static bool thresholding_irq_en; struct mce_amd_cpu_data { mce_banks_t thr_intr_banks; mce_banks_t dfr_intr_banks; + + u32 thr_intr_en: 1, + dfr_intr_en: 1, + __resv: 30; }; =20 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_amd_cpu_data, mce_amd_data); @@ -271,6 +272,7 @@ void (*deferred_error_int_vector)(void) =3D default_def= erred_error_interrupt; =20 static void smca_configure(unsigned int bank, unsigned int cpu) { + struct mce_amd_cpu_data *data =3D this_cpu_ptr(&mce_amd_data); u8 *bank_counts =3D this_cpu_ptr(smca_bank_counts); const struct smca_hwid *s_hwid; unsigned int i, hwid_mcatype; @@ -301,8 +303,8 @@ static void smca_configure(unsigned int bank, unsigned = int cpu) * APIC based interrupt. First, check that no interrupt has been * set. */ - if ((low & BIT(5)) && !((high >> 5) & 0x3)) { - __set_bit(bank, this_cpu_ptr(&mce_amd_data)->dfr_intr_banks); + if ((low & BIT(5)) && !((high >> 5) & 0x3) && data->dfr_intr_en) { + __set_bit(bank, data->dfr_intr_banks); high |=3D BIT(5); } =20 @@ -377,6 +379,14 @@ static bool lvt_off_valid(struct threshold_block *b, i= nt apic, u32 lo, u32 hi) { int msr =3D (hi & MASK_LVTOFF_HI) >> 20; =20 + /* + * On SMCA CPUs, LVT offset is programmed at a different MSR, and + * the BIOS provides the value. The original field where LVT offset + * was set is reserved. Return early here: + */ + if (mce_flags.smca) + return false; + if (apic < 0) { pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " "for bank %d, block %d (MSR%08X=3D0x%x%08x)\n", b->cpu, @@ -385,14 +395,6 @@ static bool lvt_off_valid(struct threshold_block *b, i= nt apic, u32 lo, u32 hi) } =20 if (apic !=3D msr) { - /* - * On SMCA CPUs, LVT offset is programmed at a different MSR, and - * the BIOS provides the value. The original field where LVT offset - * was set is reserved. Return early here: - */ - if (mce_flags.smca) - return false; - pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " "for bank %d, block %d (MSR%08X=3D0x%x%08x)\n", b->cpu, apic, b->bank, b->block, b->address, hi, lo); @@ -473,41 +475,6 @@ static int setup_APIC_mce_threshold(int reserved, int = new) return reserved; } =20 -static int setup_APIC_deferred_error(int reserved, int new) -{ - if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, - APIC_EILVT_MSG_FIX, 0)) - return new; - - return reserved; -} - -static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) -{ - u32 low =3D 0, high =3D 0; - int def_offset =3D -1, def_new; - - if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) - return; - - def_new =3D (low & MASK_DEF_LVTOFF) >> 4; - if (!(low & MASK_DEF_LVTOFF)) { - pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred e= rror IRQs correctly.\n"); - def_new =3D DEF_LVT_OFF; - low =3D (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); - } - - def_offset =3D setup_APIC_deferred_error(def_offset, def_new); - if ((def_offset =3D=3D def_new) && - (deferred_error_int_vector !=3D amd_deferred_error_interrupt)) - deferred_error_int_vector =3D amd_deferred_error_interrupt; - - if (!mce_flags.smca) - low =3D (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; - - wrmsr(MSR_CU_DEF_ERR, low, high); -} - static u32 get_block_address(u32 current_addr, u32 low, u32 high, unsigned int bank, unsigned int block, unsigned int cpu) @@ -543,12 +510,10 @@ static u32 get_block_address(u32 current_addr, u32 lo= w, u32 high, return addr; } =20 -static int -prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, - int offset, u32 misc_high) +static int prepare_threshold_block(unsigned int bank, unsigned int block, = u32 addr, + int offset, u32 misc_high) { unsigned int cpu =3D smp_processor_id(); - u32 smca_low, smca_high; struct threshold_block b; int new; =20 @@ -568,18 +533,10 @@ prepare_threshold_block(unsigned int bank, unsigned i= nt block, u32 addr, __set_bit(bank, this_cpu_ptr(&mce_amd_data)->thr_intr_banks); b.interrupt_enable =3D 1; =20 - if (!mce_flags.smca) { - new =3D (misc_high & MASK_LVTOFF_HI) >> 20; - goto set_offset; - } - - /* Gather LVT offset for thresholding: */ - if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) - goto out; - - new =3D (smca_low & SMCA_THR_LVT_OFF) >> 12; + if (mce_flags.smca) + goto done; =20 -set_offset: + new =3D (misc_high & MASK_LVTOFF_HI) >> 20; offset =3D setup_APIC_mce_threshold(offset, new); if (offset =3D=3D new) thresholding_irq_en =3D true; @@ -587,7 +544,6 @@ prepare_threshold_block(unsigned int bank, unsigned int= block, u32 addr, done: mce_threshold_block_init(&b, offset); =20 -out: return offset; } =20 @@ -678,6 +634,32 @@ static void amd_apply_cpu_quirks(struct cpuinfo_x86 *c) mce_banks[0].ctl =3D 0; } =20 +/* + * Enable the APIC LVT interrupt vectors once per-CPU. This should be done= before hardware is + * ready to send interrupts. + * + * Individual error sources are enabled later during per-bank init. + */ +static void smca_enable_interrupt_vectors(void) +{ + struct mce_amd_cpu_data *data =3D this_cpu_ptr(&mce_amd_data); + u64 mca_intr_cfg, offset; + + if (!mce_flags.smca || !mce_flags.succor) + return; + + if (rdmsrq_safe(MSR_CU_DEF_ERR, &mca_intr_cfg)) + return; + + offset =3D (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12; + if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_EILVT_MSG_FIX, = 0)) + data->thr_intr_en =3D 1; + + offset =3D (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4; + if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, = 0)) + data->dfr_intr_en =3D 1; +} + /* cpu init entry point, called from mce.c with preempt off */ void mce_amd_feature_init(struct cpuinfo_x86 *c) { @@ -689,10 +671,16 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) =20 mce_flags.amd_threshold =3D 1; =20 + smca_enable_interrupt_vectors(); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250908-wip-mca-updates-v6-11-eef5d6c74b9c@amd.com> References: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> In-Reply-To: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> To: , Tony Luck , "Rafael J. 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This feature counts errors of all severities, but it is commonly used to report correctable errors with an interrupt rather than polling. Scalable MCA systems allow the Platform to take control of this feature. In this case, the OS will not see the feature configuration and control bits in the MCA_MISC* registers. The OS will not receive the MCA thresholding interrupt, and it will need to poll for correctable errors. A "corrected error interrupt" will be available on Scalable MCA systems. This will be used in the same configuration where the Platform controls MCA thresholding. However, the Platform will now be able to send the MCA thresholding interrupt to the OS. Check for, and enable, this feature during per-CPU SMCA init. Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-16-865768a2eef8@a= md.com =20 v5->v6: * No change. =20 v4->v5: * No change. =20 v3->v4: * Add code comment describing bits. =20 v2->v3: * Add tags from Tony. =20 v1->v2: * Use new per-CPU struct. arch/x86/kernel/cpu/mce/amd.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index a6f5c9339d7c..34268940c88a 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -308,6 +308,23 @@ static void smca_configure(unsigned int bank, unsigned= int cpu) high |=3D BIT(5); } =20 + /* + * SMCA Corrected Error Interrupt + * + * MCA_CONFIG[IntPresent] is bit 10, and tells us if the bank can + * send an MCA Thresholding interrupt without the OS initializing + * this feature. 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So drop the redundant checks. Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-17-865768a2eef8@a= md.com =20 v5->v6: * No change. =20 v4->v5: * No change. =20 v3->v4: * New in v4. arch/x86/kernel/cpu/mce/amd.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 34268940c88a..9ca4079ff342 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -812,29 +812,11 @@ static void amd_deferred_error_interrupt(void) machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->dfr_intr_= banks); } =20 -static void reset_block(struct threshold_block *block) -{ - struct thresh_restart tr; - u32 low =3D 0, high =3D 0; - - if (!block) - return; - - if (rdmsr_safe(block->address, &low, &high)) - return; - - if (!(high & MASK_OVERFLOW_HI)) - return; - - memset(&tr, 0, sizeof(tr)); - tr.b =3D block; - threshold_restart_block(&tr); -} - static void amd_reset_thr_limit(unsigned int bank) { struct threshold_bank **bp =3D this_cpu_read(threshold_banks); struct threshold_block *block, *tmp; + struct thresh_restart tr; =20 /* * Validate that the threshold bank has been initialized already. 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Include a parameter to switch the interrupt enable. This will be used by the CMCI storm handling function. Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-18-865768a2eef8@a= md.com =20 v5->v6: * No change. =20 v4->v5: * No change. =20 v3->v4: * New in v4. arch/x86/kernel/cpu/mce/amd.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 9ca4079ff342..fbdb0cec5737 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -471,6 +471,24 @@ static void threshold_restart_block(void *_tr) wrmsr(tr->b->address, lo, hi); } =20 +static void threshold_restart_bank(unsigned int bank, bool intr_en) +{ + struct threshold_bank **thr_banks =3D this_cpu_read(threshold_banks); + struct threshold_block *block, *tmp; + struct thresh_restart tr; + + if (!thr_banks || !thr_banks[bank]) + return; + + memset(&tr, 0, sizeof(tr)); + + list_for_each_entry_safe(block, tmp, &thr_banks[bank]->miscj, miscj) { + tr.b =3D block; + tr.b->interrupt_enable =3D intr_en; + threshold_restart_block(&tr); + } +} + static void mce_threshold_block_init(struct threshold_block *b, int offset) { struct thresh_restart tr =3D { @@ -814,24 +832,7 @@ static void amd_deferred_error_interrupt(void) =20 static void amd_reset_thr_limit(unsigned int bank) { - struct threshold_bank **bp =3D this_cpu_read(threshold_banks); - struct threshold_block *block, *tmp; - struct thresh_restart tr; - - /* - * Validate that the threshold bank has been initialized already. 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Rely on the similar approach as of Intel's CMCI to mitigate storms per CPU and per bank. But, unlike CMCI, do not set thresholds and reduce interrupt rate on a storm. Rather, disable the interrupt on the corresponding CPU and bank. Re-enable back the interrupts if enough consecutive polls of the bank show no corrected errors (30, as programmed by Intel). Turning off the threshold interrupts would be a better solution on AMD systems as other error severities will still be handled even if the threshold interrupts are disabled. [Tony: Small tweak because mce_handle_storm() isn't a pointer now] [Yazen: Rebase and simplify] Reviewed-by: Qiuxu Zhuo Signed-off-by: Smita Koralahalli Signed-off-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-19-865768a2eef8@a= md.com =20 v5->v6: * No change. =20 v4->v5: * No change. =20 v3->v4: * Simplify based on new patches in this set. =20 v2->v3: * Add tag from Qiuxu. =20 v1->v2: * New in v2, but based on older patch. * Rebased on current set and simplified. * Kept old tags. arch/x86/kernel/cpu/mce/amd.c | 5 +++++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ arch/x86/kernel/cpu/mce/threshold.c | 3 +++ 3 files changed, 10 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index fbdb0cec5737..b895559e80ad 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -830,6 +830,11 @@ static void amd_deferred_error_interrupt(void) machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->dfr_intr_= banks); } =20 +void mce_amd_handle_storm(unsigned int bank, bool on) +{ + threshold_restart_bank(bank, on); +} + static void amd_reset_thr_limit(unsigned int bank) { threshold_restart_bank(bank, true); diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/i= nternal.h index b0e00ec5cc8c..9920ee5fb34c 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -267,6 +267,7 @@ void mce_prep_record_per_cpu(unsigned int cpu, struct m= ce *m); #ifdef CONFIG_X86_MCE_AMD void mce_threshold_create_device(unsigned int cpu); void mce_threshold_remove_device(unsigned int cpu); +void mce_amd_handle_storm(unsigned int bank, bool on); extern bool amd_filter_mce(struct mce *m); bool amd_mce_usable_address(struct mce *m); void amd_clear_bank(struct mce *m); @@ -299,6 +300,7 @@ void smca_bsp_init(void); #else static inline void mce_threshold_create_device(unsigned int cpu) { } static inline void mce_threshold_remove_device(unsigned int cpu) { } +static inline void mce_amd_handle_storm(unsigned int bank, bool on) { } static inline bool amd_filter_mce(struct mce *m) { return false; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250908-wip-mca-updates-v6-15-eef5d6c74b9c@amd.com> References: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> In-Reply-To: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com> To: , Tony Luck , "Rafael J. Wysocki" CC: , , , Qiuxu Zhuo , Nikolay Borisov , , "Yazen Ghannam" X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000B:EE_|DM4PR12MB6184:EE_ X-MS-Office365-Filtering-Correlation-Id: 9edf5d05-8152-45ce-1a30-08ddeeee2618 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?utf-8?B?MEloZFN3ckRjZlZBaVI3eXo4MFQ4QzF6R1Jhb0VqM2hyb2cxb0x0c0t6L0hO?= =?utf-8?B?cHNLSnRzY1ZYREwrNXp3WEtyYzMvZWR5NEJNNUNQMVNEc3IxRDBMZTMrczNi?= =?utf-8?B?VE82eXM1QmNkT2dtamtFSEZoU29xcVVUUDJMaks5WHpOdkV3SGo4dThmb2dZ?= =?utf-8?B?TXdOMVBUQVhicS8xdVYzb3JFUWpKQzdUNU9xa1pNd2JlVmFXOGpwUjZWRkdJ?= =?utf-8?B?ajR1OXdjVmdUSm1KRUdpQkhuM3ZLRVVIcGMxQ2pVMVJwRzhSdkdhZ1BXYlNo?= =?utf-8?B?dVMrdXpsYjY3N3haNytiR3hSWm1jZ1QreDhES0QrU2Y4Q25OVWhqdVZ5NW11?= =?utf-8?B?MDdZT2lKbnhxb3d6RHFpMXR4SktUcmNLQk1WWjNxMkNGSm1EN2hjd2lPNEE2?= =?utf-8?B?NUFTY0lHMlRMMUE3MVpFRlVzbEpLMDhhY01OODN4K3VZRmlDY2dRUTUrOEI1?= =?utf-8?B?Vk1XUnk5akhMQnhmUlVPUFdBdC9mUWF1b25lTk4xSzZlNnhoZGNaVHN1ZnhR?= =?utf-8?B?QVVKL0EwekZrNFQvM2pLaVFmNm9Nd3UvV1htOHRjMnc4SEZwUWtnRXgxUjA2?= =?utf-8?B?MmhkbHVaT0FlRGR3Y1RYZkdTZlpkT1FmZlB6NVpmR1lmK2dGV0YyWHdmd3JD?= =?utf-8?B?UFptakNadlBSckRuTzdycmpnbVF3MENSb0lmdnh5c1NPdVo4MXZCb2FqWThu?= =?utf-8?B?WS9zT2VtTmVOZU9sc3NsV29BNG9ENzh4a2pTbURWdGNHWUpOQXZUa3ZML3J4?= =?utf-8?B?ZTVmdXpnNEFTc1AvTmJhbnJZdkhOcEg2ditKL3dQYUd5Q0JoMEpmUWEvNi8v?= =?utf-8?B?WlVBMW5hZ0dlYnJCZk5KR0Y0WGZRam5FenE3MFI0aFNMMlF4MzdQbXBPMklL?= =?utf-8?B?L0FQOFBld1Y3Nk43T2hBKzB6eE5pRXRSR2cxVm5CUlZFZDJDS0VoSnhjNHBu?= =?utf-8?B?WEdLeUtiSTF6NjNlSnZISy8xQngwT0c0RjhRSnNXVnZ4M3lxdWtTSEpNZlJh?= =?utf-8?B?Y1AwSk40VVpQWElZU2ZVaE1sOFZramorakJhYStsSmVidU5Ka29yZklGV29v?= =?utf-8?B?enRWdDVXM2k2TXJHL0d2SVdkc3AvbXlWS0M1aWtmYjFXREQzUFlEUFdDeUdr?= =?utf-8?B?SEZFVmlyWG5nQllJVG1XMjcxYnpKWlFObFBldUwzUXMvR3VTQVdzMXBiMUpk?= =?utf-8?B?VEtPMS9zTjhpMmpJbk9KOXlDNEZNdUtGa0hPWG10VjVyNDZCbXM1NVBvKyts?= =?utf-8?B?cE55UDhnNUg4RFZtMUE3d0dkRURta1BmdnE2b0QzU2FKUUlwMGNnUk1TN2xE?= =?utf-8?B?eldWTEJlUDMwYzNqMDFvSndCeERvZEFZYUdYcmtSNlJqaktyOTBDTm9UVU90?= =?utf-8?B?R04yQnpnTURsV0VXd08veTFyQU43MEhYYytqajJBSkU2cmJjVktnQ3JlSGJY?= =?utf-8?B?akxaeTdkM09uQStCZWlEWTMxOUIrWGhFRW9TRmRMRzA2akFHSmd5TmNIV2tV?= =?utf-8?B?b0pSN2E2SWhRMlppMlVoZGxBWmJiejZLK3VZOGlEaExFaU9VMDVEWjVaSFdQ?= =?utf-8?B?dnpJUm4xWG1XNWpRZS8wa2JTa3lyTXpCOW56L3dIVU0zSHNPSFFrVm9YS2Jo?= =?utf-8?B?WHFQN0IyM1huc2o4WkxLbXVER1B5UUZySzZMVVVvbVlpd1VSVkU5UGVQRkNs?= =?utf-8?B?NDFRSmdiSWN3Vng5OGhlbG5KUnBIQ25aNW1sbloyZ3JraEI1azBGWWtoRmZT?= =?utf-8?B?MjhRRjlvcVYzZzkwUy9WTHZjbUphQ3FVQ3hNeXZaODFIQUE4RkZ2Tzl4NXBN?= =?utf-8?B?ZVdyTjJrMUdyTE1tdm9rTGloZHNZZzhQVVdTZzBsSnhZVHQ4Qk4yaHFvRmJF?= =?utf-8?B?aWR4OG5EMmFScVVxU1NaMTM1akxHQVh5cHB3d2dvenIvZGRKamNTVHdBMlpX?= =?utf-8?B?V0NDZEFQdHJpTHJTQSsyVTFkMlBBUHlZVHdIaTVOeXNVY0VBLzY0QjNhRTk3?= =?utf-8?B?bHMyaDl6TG9NRG9xMVRZR0lkcmw3Q3BRdkFGNVBNcGNFUkxiU3dNVWd1TFdE?= =?utf-8?B?ZGZweUY4SEVtdGNranVYbEZOajd4d1A5RDFJdz09?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 15:41:16.4681 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9edf5d05-8152-45ce-1a30-08ddeeee2618 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6184 The MCA threshold limit generally is not something that needs to change during runtime. It is common for a system administrator to decide on a policy for their managed systems. If MCA thresholding is OS-managed, then the threshold limit must be set at every boot. However, many systems allow the user to set a value in their BIOS. And this is reported through an APEI HEST entry even if thresholding is not in FW-First mode. Use this value, if available, to set the OS-managed threshold limit. Users can still override it through sysfs if desired for testing or debug. APEI is parsed after MCE is initialized. So reset the thresholding blocks later to pick up the threshold limit. Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250825-wip-mca-updates-v5-20-865768a2eef8@a= md.com =20 v5->v6: * No change. =20 v4->v5: * No change. =20 v3->v4: * New in v4. arch/x86/include/asm/mce.h | 6 ++++++ arch/x86/kernel/acpi/apei.c | 2 ++ arch/x86/kernel/cpu/mce/amd.c | 18 ++++++++++++++++-- arch/x86/kernel/cpu/mce/internal.h | 2 ++ arch/x86/kernel/cpu/mce/threshold.c | 13 +++++++++++++ 5 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 7d6588195d56..1cfbfff0be3f 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -308,6 +308,12 @@ DECLARE_PER_CPU(struct mce, injectm); /* Disable CMCI/polling for MCA bank claimed by firmware */ extern void mce_disable_bank(int bank); =20 +#ifdef CONFIG_X86_MCE_THRESHOLD +void mce_save_apei_thr_limit(u32 thr_limit); +#else +static inline void mce_save_apei_thr_limit(u32 thr_limit) { } +#endif /* CONFIG_X86_MCE_THRESHOLD */ + /* * Exception handler */ diff --git a/arch/x86/kernel/acpi/apei.c b/arch/x86/kernel/acpi/apei.c index 0916f00a992e..e21419e686eb 100644 --- a/arch/x86/kernel/acpi/apei.c +++ b/arch/x86/kernel/acpi/apei.c @@ -19,6 +19,8 @@ int arch_apei_enable_cmcff(struct acpi_hest_header *hest_= hdr, void *data) if (!cmc->enabled) return 0; =20 + mce_save_apei_thr_limit(cmc->notify.error_threshold_value); + /* * We expect HEST to provide a list of MC banks that report errors * in firmware first mode. Otherwise, return non-zero value to diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index b895559e80ad..9b746080351f 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -489,6 +489,18 @@ static void threshold_restart_bank(unsigned int bank, = bool intr_en) } } =20 +/* Try to use the threshold limit reported through APEI. */ +static u16 get_thr_limit(void) +{ + u32 thr_limit =3D mce_get_apei_thr_limit(); + + /* Fallback to old default if APEI limit is not available. */ + if (!thr_limit) + return THRESHOLD_MAX; + + return min(thr_limit, THRESHOLD_MAX); +} + static void mce_threshold_block_init(struct threshold_block *b, int offset) { struct thresh_restart tr =3D { @@ -497,7 +509,7 @@ static void mce_threshold_block_init(struct threshold_b= lock *b, int offset) .lvt_off =3D offset, }; =20 - b->threshold_limit =3D THRESHOLD_MAX; + b->threshold_limit =3D get_thr_limit(); threshold_restart_block(&tr); }; =20 @@ -1071,7 +1083,7 @@ static int allocate_threshold_blocks(unsigned int cpu= , struct threshold_bank *tb b->address =3D address; b->interrupt_enable =3D 0; b->interrupt_capable =3D lvt_interrupt_supported(bank, high); - b->threshold_limit =3D THRESHOLD_MAX; + b->threshold_limit =3D get_thr_limit(); =20 if (b->interrupt_capable) { default_attrs[2] =3D &interrupt_enable.attr; @@ -1082,6 +1094,8 @@ static int allocate_threshold_blocks(unsigned int cpu= , struct threshold_bank *tb =20 list_add(&b->miscj, &tb->miscj); =20 + mce_threshold_block_init(b, (high & MASK_LVTOFF_HI) >> 20); + err =3D kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_na= me(cpu, bank, b)); if (err) goto out_free; diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/i= nternal.h index 9920ee5fb34c..a31cf984619c 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -67,6 +67,7 @@ void mce_track_storm(struct mce *mce); void mce_inherit_storm(unsigned int bank); bool mce_get_storm_mode(void); void mce_set_storm_mode(bool storm); +u32 mce_get_apei_thr_limit(void); #else static inline void cmci_storm_begin(unsigned int bank) {} static inline void cmci_storm_end(unsigned int bank) {} @@ -74,6 +75,7 @@ static inline void mce_track_storm(struct mce *mce) {} static inline void mce_inherit_storm(unsigned int bank) {} static inline bool mce_get_storm_mode(void) { return false; } static inline void mce_set_storm_mode(bool storm) {} +static inline u32 mce_get_apei_thr_limit(void) { return 0; } #endif =20 /* diff --git a/arch/x86/kernel/cpu/mce/threshold.c b/arch/x86/kernel/cpu/mce/= threshold.c index 45144598ec74..d00d5bf9959d 100644 --- a/arch/x86/kernel/cpu/mce/threshold.c +++ b/arch/x86/kernel/cpu/mce/threshold.c @@ -13,6 +13,19 @@ =20 #include "internal.h" =20 +static u32 mce_apei_thr_limit; + +void mce_save_apei_thr_limit(u32 thr_limit) +{ + mce_apei_thr_limit =3D thr_limit; + pr_info("HEST: Corrected error threshold limit =3D %u\n", thr_limit); +} + +u32 mce_get_apei_thr_limit(void) +{ + return mce_apei_thr_limit; +} + static void default_threshold_interrupt(void) { pr_err("Unexpected threshold interrupt at vector %x\n", --=20 2.51.0