From nobody Fri Oct 3 03:18:40 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F59A21B19D; Mon, 8 Sep 2025 04:15:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757304929; cv=none; b=Z7tKcLYkbuaXtD2WQcslB6RBKph7uHSFLJLSSSoTzSOGHE7kB/BVsN4gKyvi9wbKN88xDFcMV6QJ3j0E7ja/TFefuVcj5osNZddmUE7q4b3eivH/gyAF5orXrLyy+1iV7d6ldjBt76KoHFNwBbbfOAiz8LMDJu+QxNH2yGwJ14w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757304929; c=relaxed/simple; bh=vx2kNy0+HhAu9oJXF7h1H6iRH7NO2rPLGfr4zC9bQyA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=uTgFYXU2/pctYXaPiXzABkJsOccppY33jUIDAG9KN6nJ0zTXqLMSjx1xVgYfUHW8CJfDN4vqGcFWm1OKMKkw/qWOysB65hgOaW2uFHjJl+lDsswrCe3A4VH6GkyKDEmSSxDd0gLrcnygwCH0p6SXAl1ShP3423OcfgcypLJh6xA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=sDinFn7a; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="sDinFn7a" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1757304927; x=1788840927; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=vx2kNy0+HhAu9oJXF7h1H6iRH7NO2rPLGfr4zC9bQyA=; b=sDinFn7aWVSSXiFbA2iG+fne536vUhAZtTy2w/JnOnS7Ul2wiScF+uHL PQ3b2Y/fcWeowFys/HVv0VRmMrd/8SFgUrduWhx7aIVTGq+5rr4ZHjfkw 8lywOpxj8Codi/qvbJXf/6BPaH1IJtUaAZ1kHD4y66vtIIW+bY+7oHvii lL61g/eQ9qAIxgrppsvMjfzG5bgGp4pq+4Jr73h8R6EVl+gDkbtX/yRFw hlXmT9s1ebrt8hBPAZBpYUvEMRZkk7mDVcE9Iuo46Tus079UJColoCYJT 6JT/s1ynhUW98TkmVcyxlwfhmdxprdtM0GOr/IAKErGiAR/iJGH+dN6oQ w==; X-CSE-ConnectionGUID: q/SJvp4uQvCY0cG18DoX1w== X-CSE-MsgGUID: ZJVDMuJtRJitEtb3JxJQeA== X-IronPort-AV: E=Sophos;i="6.18,247,1751266800"; d="scan'208";a="46742463" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 07 Sep 2025 21:15:26 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Sun, 7 Sep 2025 21:14:58 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Sun, 7 Sep 2025 21:14:52 -0700 From: Dharma Balasubiramani Date: Mon, 8 Sep 2025 09:44:20 +0530 Subject: [PATCH v2 5/5] spi: atmel-quadspi: Add support for sama7d65 QSPI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250908-microchip-qspi-v2-5-8f3d69fdd5c9@microchip.com> References: <20250908-microchip-qspi-v2-0-8f3d69fdd5c9@microchip.com> In-Reply-To: <20250908-microchip-qspi-v2-0-8f3d69fdd5c9@microchip.com> To: Mark Brown , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Nicolas Ferre" , Alexandre Belloni , Claudiu Beznea , Tudor Ambarus CC: , , , , Dharma Balasubiramani , Varshini Rajendran X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757304860; l=1545; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=f0BEjRg0ecgW3mbWEOamZAvt1r/7v97MsNFu6rAL6n8=; b=00YL9K3Oot2eHMDWKTvLcLPGPfmcIclFGVvDwqZ2I+XnJFnXS2UbKtOsqxFGJmo9H+6F6i3TO rGVpcQg7n+0C48LlkIsVwYrLigv/DAIZ+NKDIiZnA4Itk2gfbvheFqX X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= From: Varshini Rajendran Add support for sama7d65 QSPI controller and define its caps. Signed-off-by: Varshini Rajendran --- drivers/spi/atmel-quadspi.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 342cdd6e8d64..d7a3d85d00c2 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -1638,6 +1638,24 @@ static const struct atmel_qspi_caps atmel_sam9x7_osp= i_caps =3D { .has_dllon =3D false, }; =20 +static const struct atmel_qspi_caps atmel_sama7d65_ospi_caps =3D { + .max_speed_hz =3D SAMA7G5_QSPI0_MAX_SPEED_HZ, + .has_gclk =3D true, + .octal =3D true, + .has_dma =3D true, + .has_2xgclk =3D true, + .has_padcalib =3D true, + .has_dllon =3D false, +}; + +static const struct atmel_qspi_caps atmel_sama7d65_qspi_caps =3D { + .max_speed_hz =3D SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ, + .has_gclk =3D true, + .has_dma =3D true, + .has_2xgclk =3D true, + .has_dllon =3D false, +}; + static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps =3D { .max_speed_hz =3D SAMA7G5_QSPI0_MAX_SPEED_HZ, .has_gclk =3D true, @@ -1675,6 +1693,15 @@ static const struct of_device_id atmel_qspi_dt_ids[]= =3D { .compatible =3D "microchip,sam9x7-ospi", .data =3D &atmel_sam9x7_ospi_caps, }, + { + .compatible =3D "microchip,sama7d65-ospi", + .data =3D &atmel_sama7d65_ospi_caps, + }, + { + .compatible =3D "microchip,sama7d65-qspi", + .data =3D &atmel_sama7d65_qspi_caps, + }, + =20 { /* sentinel */ } }; --=20 2.43.0