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This controller supports either eMMC or SD-card, but only one can be active at a time. SD-card is the preferred configuration on Lemans targets, so describe this controller. Define the SDC interface pins including clk, cmd, and data lines to enable proper communication with the SDHC controller. Signed-off-by: Monish Chunara Reviewed-by: Konrad Dybcio Co-developed-by: Wasim Nazir Signed-off-by: Wasim Nazir --- arch/arm64/boot/dts/qcom/lemans.dtsi | 92 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index f5ec60086d60..05d5da382bca 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -3834,6 +3834,58 @@ apss_tpdm2_out: endpoint { }; }; =20 + sdhc: mmc@87c4000 { + compatible =3D "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x087c4000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>; + clock-names =3D "iface", + "core"; + + interconnects =3D <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "sdhc-ddr", + "cpu-sdhc"; + + iommus =3D <&apps_smmu 0x0 0x0>; + dma-coherent; + + operating-points-v2 =3D <&sdhc_opp_table>; + power-domains =3D <&rpmhpd SA8775P_CX>; + resets =3D <&gcc GCC_SDCC1_BCR>; + + qcom,dll-config =3D <0x0007642c>; + qcom,ddr-config =3D <0x80040868>; + + status =3D "disabled"; + + sdhc_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1800000 400000>; + opp-avg-kBps =3D <100000 0>; + }; + + opp-384000000 { + opp-hz =3D /bits/ 64 <384000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <5400000 1600000>; + opp-avg-kBps =3D <390000 0>; + }; + }; + }; + usb_0_hsphy: phy@88e4000 { compatible =3D "qcom,sa8775p-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; @@ -5643,6 +5695,46 @@ qup_uart21_rx: qup-uart21-rx-pins { function =3D "qup3_se0"; }; }; + + sdc_default: sdc-default-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + }; + + sdc_sleep: sdc-sleep-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <2>; + bias-bus-hold; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <2>; + bias-bus-hold; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <2>; + bias-bus-hold; + }; + }; }; =20 sram: sram@146d8000 { --=20 2.51.0