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Mon, 08 Sep 2025 05:10:40 -0700 (PDT) From: James Clark Date: Mon, 08 Sep 2025 13:10:18 +0100 Subject: [PATCH 1/4] perf arm-spe: Show instruction sample types by default Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-james-perf-spe-period-v1-1-7ccd805af461@linaro.org> References: <20250908-james-perf-spe-period-v1-0-7ccd805af461@linaro.org> In-Reply-To: <20250908-james-perf-spe-period-v1-0-7ccd805af461@linaro.org> To: John Garry , Will Deacon , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , George Wort , Graham Woodward , Ben Gainey , Michael Williams Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 Instruction sample types are enabled in the default itrace options in Perf, but this never applied to SPE because the default nanoseconds period isn't supported. This meant that instructions ended up being opt-in by the user only when they requested an instruction based period. Change the default period type to instructions so that instruction samples are generated by default. This can overridden by specifying any --itrace option. This solves a common complaint from users that the unfiltered SPE samples appear to be missing, and only the samples that have memory flags set appear in the various memory groups. Signed-off-by: James Clark Tested-by: Leo Yan --- tools/perf/util/arm-spe.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 8942fa598a84..b33a0a170ef8 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -1871,10 +1871,14 @@ int arm_spe_process_auxtrace_info(union perf_event = *event, if (dump_trace) return 0; =20 - if (session->itrace_synth_opts && session->itrace_synth_opts->set) + if (session->itrace_synth_opts && session->itrace_synth_opts->set) { spe->synth_opts =3D *session->itrace_synth_opts; - else + } else { itrace_synth_opts__set_default(&spe->synth_opts, false); + /* Default nanoseconds period not supported */ + spe->synth_opts.period_type =3D PERF_ITRACE_PERIOD_INSTRUCTIONS; + spe->synth_opts.period =3D 1; + } =20 err =3D arm_spe_synth_events(spe, session); if (err) --=20 2.34.1 From nobody Wed Sep 10 01:43:00 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B21512FC025 for ; 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Mon, 08 Sep 2025 05:10:41 -0700 (PDT) Received: from ho-tower-lan.lan ([185.48.76.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cf33fba9fbsm41397825f8f.50.2025.09.08.05.10.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 05:10:41 -0700 (PDT) From: James Clark Date: Mon, 08 Sep 2025 13:10:19 +0100 Subject: [PATCH 2/4] perf arm-spe: Downsample all sample types equally Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-james-perf-spe-period-v1-2-7ccd805af461@linaro.org> References: <20250908-james-perf-spe-period-v1-0-7ccd805af461@linaro.org> In-Reply-To: <20250908-james-perf-spe-period-v1-0-7ccd805af461@linaro.org> To: John Garry , Will Deacon , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , George Wort , Graham Woodward , Ben Gainey , Michael Williams Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 The various sample types that are generated are based on the same SPE sample, just placed into different sample type bins. The same sample can be in multiple bins if it has flags set that cause it to be. Currently we're only applying the --itrace interval downsampling to the instruction bin, which means that the sample would appear in one bin but not another if it was skipped due to downsampling. I don't thing anyone would want or expect this, so make this behave consistently by applying the downsampling before generating any sample. You might argue that the "instructions" interval type doesn't make sense to apply to "memory" sample types because it would be skipping every n memory samples, rather than every n instructions. But the downsampling was already not an instruction interval even for the instruction samples. SPE has a hardware based sampling interval, and the instruction interval was just a convenient way to specify further downsampling. This is hinted at in the warning message shown for intervals greater than 1. This makes SPE diverge from trace technologies like Intel PT and Arm Coresight. In those cases instruction samples can be reduced but all branches are still emitted. This makes sense there, because branches form a complete execution history, and asking to skip branches every n instructions doesn't really make sense. But for SPE, as mentioned above, downsampling the instruction samples already wasn't consistent with trace technologies so we ended up with some middle ground that had no benefit. Now it's possible to reduce the volume of samples in all groups and samples won't be missing from one group but present in another. Signed-off-by: James Clark Reviewed-by: Leo Yan Tested-by: Leo Yan --- tools/perf/util/arm-spe.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index b33a0a170ef8..4c81518a033a 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -62,7 +62,6 @@ struct arm_spe { u8 sample_remote_access; u8 sample_memory; u8 sample_instructions; - u64 instructions_sample_period; =20 u64 l1d_miss_id; u64 l1d_access_id; @@ -101,7 +100,7 @@ struct arm_spe_queue { u64 time; u64 timestamp; struct thread *thread; - u64 period_instructions; + u64 sample_count; u32 flags; struct branch_stack *last_branch; }; @@ -228,7 +227,6 @@ static struct arm_spe_queue *arm_spe__alloc_queue(struc= t arm_spe *spe, speq->pid =3D -1; speq->tid =3D -1; speq->cpu =3D -1; - speq->period_instructions =3D 0; =20 /* params set */ params.get_trace =3D arm_spe_get_trace; @@ -352,7 +350,7 @@ static void arm_spe_prep_sample(struct arm_spe *spe, sample->cpumode =3D arm_spe_cpumode(spe, sample->ip); sample->pid =3D speq->pid; sample->tid =3D speq->tid; - sample->period =3D 1; + sample->period =3D spe->synth_opts.period; sample->cpu =3D speq->cpu; sample->simd_flags =3D arm_spe__synth_simd_flags(record); =20 @@ -527,14 +525,6 @@ static int arm_spe__synth_instruction_sample(struct ar= m_spe_queue *speq, struct perf_sample sample; int ret; =20 - /* - * Handles perf instruction sampling period. - */ - speq->period_instructions++; - if (speq->period_instructions < spe->instructions_sample_period) - return 0; - speq->period_instructions =3D 0; - perf_sample__init(&sample, /*all=3D*/true); arm_spe_prep_sample(spe, speq, event, &sample); =20 @@ -543,7 +533,6 @@ static int arm_spe__synth_instruction_sample(struct arm= _spe_queue *speq, sample.addr =3D record->to_ip; sample.phys_addr =3D record->phys_addr; sample.data_src =3D data_src; - sample.period =3D spe->instructions_sample_period; sample.weight =3D record->latency; sample.flags =3D speq->flags; sample.branch_stack =3D speq->last_branch; @@ -929,6 +918,14 @@ static int arm_spe_sample(struct arm_spe_queue *speq) u64 data_src; int err; =20 + /* + * Discard all samples until period is reached + */ + speq->sample_count++; + if (speq->sample_count < spe->synth_opts.period) + return 0; + speq->sample_count =3D 0; + arm_spe__sample_flags(speq); data_src =3D arm_spe__synth_data_source(speq, record); =20 @@ -1628,6 +1625,7 @@ arm_spe_synth_events(struct arm_spe *spe, struct perf= _session *session) attr.exclude_guest =3D evsel->core.attr.exclude_guest; attr.sample_id_all =3D evsel->core.attr.sample_id_all; attr.read_format =3D evsel->core.attr.read_format; + attr.sample_period =3D spe->synth_opts.period; =20 /* create new id val to be a fixed offset from evsel id */ id =3D evsel->core.id[0] + 1000000000; @@ -1754,8 +1752,7 @@ arm_spe_synth_events(struct arm_spe *spe, struct perf= _session *session) =20 spe->sample_instructions =3D true; attr.config =3D PERF_COUNT_HW_INSTRUCTIONS; - attr.sample_period =3D spe->synth_opts.period; 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Mon, 08 Sep 2025 05:10:42 -0700 (PDT) From: James Clark Date: Mon, 08 Sep 2025 13:10:20 +0100 Subject: [PATCH 3/4] perf arm-spe: Display --itrace period warnings for all sample types Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-james-perf-spe-period-v1-3-7ccd805af461@linaro.org> References: <20250908-james-perf-spe-period-v1-0-7ccd805af461@linaro.org> In-Reply-To: <20250908-james-perf-spe-period-v1-0-7ccd805af461@linaro.org> To: John Garry , Will Deacon , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , George Wort , Graham Woodward , Ben Gainey , Michael Williams Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 Currently we only display the warning when the instructions group is requested. Instructions are on by default, and the period applies to all sample types anyway so always check the options and show the warning. Reword the messages to be more explicit about which flags the warnings apply to. Signed-off-by: James Clark Tested-by: Leo Yan --- tools/perf/util/arm-spe.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 4c81518a033a..228ed52e653d 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -1742,14 +1742,6 @@ arm_spe_synth_events(struct arm_spe *spe, struct per= f_session *session) } =20 if (spe->synth_opts.instructions) { - if (spe->synth_opts.period_type !=3D PERF_ITRACE_PERIOD_INSTRUCTIONS) { - pr_warning("Only instruction-based sampling period is currently support= ed by Arm SPE.\n"); - goto synth_instructions_out; - } - if (spe->synth_opts.period > 1) - pr_warning("Arm SPE has a hardware-based sample period.\n" - "Additional instruction events will be discarded by --itrace\n"); - spe->sample_instructions =3D true; attr.config =3D PERF_COUNT_HW_INSTRUCTIONS; =20 @@ -1759,7 +1751,6 @@ arm_spe_synth_events(struct arm_spe *spe, struct perf= _session *session) spe->instructions_id =3D id; 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Mon, 08 Sep 2025 05:10:44 -0700 (PDT) Received: from ho-tower-lan.lan ([185.48.76.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3cf33fba9fbsm41397825f8f.50.2025.09.08.05.10.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 05:10:43 -0700 (PDT) From: James Clark Date: Mon, 08 Sep 2025 13:10:21 +0100 Subject: [PATCH 4/4] perf docs: Update SPE doc to include default instructions group Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-james-perf-spe-period-v1-4-7ccd805af461@linaro.org> References: <20250908-james-perf-spe-period-v1-0-7ccd805af461@linaro.org> In-Reply-To: <20250908-james-perf-spe-period-v1-0-7ccd805af461@linaro.org> To: John Garry , Will Deacon , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , George Wort , Graham Woodward , Ben Gainey , Michael Williams Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 The instructions group is now generated by default so update the doc to reflect this. Also explain the period/downsampling mechanism in more detail. Signed-off-by: James Clark Tested-by: Leo Yan --- tools/perf/Documentation/perf-arm-spe.txt | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tools/perf/Documentation/perf-arm-spe.txt b/tools/perf/Documen= tation/perf-arm-spe.txt index 37afade4f1b2..cda8dd47fc4d 100644 --- a/tools/perf/Documentation/perf-arm-spe.txt +++ b/tools/perf/Documentation/perf-arm-spe.txt @@ -191,14 +191,20 @@ groups: 36 branch 0 remote-access 900 memory + 1800 instructions =20 The arm_spe// and dummy:u events are implementation details and are expect= ed to be empty. =20 -To get a full list of unique samples that are not sorted into groups, set = the itrace option to -generate 'instruction' samples. The period option is also taken into accou= nt, so set it to 1 -instruction unless you want to further downsample the already sampled SPE = data: +The instructions group contains the full list of unique samples that are n= ot +sorted into other groups. To generate only this group use --itrace=3Di1i. =20 - perf report --itrace=3Di1i +1i (1 instruction interval) signifies no further downsampling. Rather than= an +instruction interval, this generates a sample every n SPE samples. For exa= mple +to generate the default set of events for every 100 SPE samples: + + perf report --itrace=3D=3DbxofmtMai100i + +Other period types, for example nanoseconds (ns) are not currently support= ed. =20 Memory access details are also stored on the samples and this can be viewe= d with: =20 --=20 2.34.1