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Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 68 +++++++++++++++++++++++++++= +++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + 3 files changed, 79 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..547c046730a9b50a82cc9b27f08= a5b1eeb08dced 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1343,6 +1343,69 @@ static const uint32_t a7xx_pwrup_reglist_regs[] =3D { =20 DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist); =20 +/* Applicable for X185, A750 */ +static const u32 a750_ifpc_reglist_regs[] =3D { + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A6XX_CP_DBG_ECO_CNTL, + REG_A6XX_CP_PROTECT_CNTL, + REG_A6XX_CP_PROTECT(0), + REG_A6XX_CP_PROTECT(1), + REG_A6XX_CP_PROTECT(2), + REG_A6XX_CP_PROTECT(3), + REG_A6XX_CP_PROTECT(4), + REG_A6XX_CP_PROTECT(5), + REG_A6XX_CP_PROTECT(6), + REG_A6XX_CP_PROTECT(7), + REG_A6XX_CP_PROTECT(8), + REG_A6XX_CP_PROTECT(9), + REG_A6XX_CP_PROTECT(10), + REG_A6XX_CP_PROTECT(11), + REG_A6XX_CP_PROTECT(12), + REG_A6XX_CP_PROTECT(13), + REG_A6XX_CP_PROTECT(14), + REG_A6XX_CP_PROTECT(15), + REG_A6XX_CP_PROTECT(16), + REG_A6XX_CP_PROTECT(17), + REG_A6XX_CP_PROTECT(18), + REG_A6XX_CP_PROTECT(19), + REG_A6XX_CP_PROTECT(20), + REG_A6XX_CP_PROTECT(21), + REG_A6XX_CP_PROTECT(22), + REG_A6XX_CP_PROTECT(23), + REG_A6XX_CP_PROTECT(24), + REG_A6XX_CP_PROTECT(25), + REG_A6XX_CP_PROTECT(26), + REG_A6XX_CP_PROTECT(27), + REG_A6XX_CP_PROTECT(28), + REG_A6XX_CP_PROTECT(29), + REG_A6XX_CP_PROTECT(30), + REG_A6XX_CP_PROTECT(31), + REG_A6XX_CP_PROTECT(32), + REG_A6XX_CP_PROTECT(33), + REG_A6XX_CP_PROTECT(34), + REG_A6XX_CP_PROTECT(35), + REG_A6XX_CP_PROTECT(36), + REG_A6XX_CP_PROTECT(37), + REG_A6XX_CP_PROTECT(38), + REG_A6XX_CP_PROTECT(39), + REG_A6XX_CP_PROTECT(40), + REG_A6XX_CP_PROTECT(41), + REG_A6XX_CP_PROTECT(42), + REG_A6XX_CP_PROTECT(43), + REG_A6XX_CP_PROTECT(44), + REG_A6XX_CP_PROTECT(45), + REG_A6XX_CP_PROTECT(46), + REG_A6XX_CP_PROTECT(47), +}; + +DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist); + static const struct adreno_info a7xx_gpus[] =3D { { .chip_ids =3D ADRENO_CHIP_IDS(0x07000200), @@ -1432,12 +1495,14 @@ static const struct adreno_info a7xx_gpus[] =3D { .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_IFPC, .init =3D a6xx_gpu_init, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .ifpc_reglist =3D &a750_ifpc_reglist, .gmu_chipid =3D 0x7050001, .gmu_cgc_mode =3D 0x00020202, }, @@ -1466,6 +1531,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .protect =3D &a730_protect, .pwrup_reglist =3D &a7xx_pwrup_reglist, + .ifpc_reglist =3D &a750_ifpc_reglist, .gmu_chipid =3D 0x7090100, .gmu_cgc_mode =3D 0x00020202, .bcms =3D (const struct a6xx_bcm[]) { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 76dd78f5c48ea818a2aa209e0c0c88bc5e8f4e06..91a2a82c4f388ca6b052172efdd= 7255165f3c04a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -828,11 +828,10 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *= gpu) u32 *dest =3D (u32 *)&lock->regs[0]; int i; =20 - reglist =3D adreno_gpu->info->a6xx->pwrup_reglist; - lock->gpu_req =3D lock->cpu_req =3D lock->turn =3D 0; - lock->ifpc_list_len =3D 0; - lock->preemption_list_len =3D reglist->count; + + reglist =3D adreno_gpu->info->a6xx->ifpc_reglist; + lock->ifpc_list_len =3D reglist->count; =20 /* * For each entry in each of the lists, write the offset and the current @@ -843,6 +842,14 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *g= pu) *dest++ =3D gpu_read(gpu, reglist->regs[i]); } =20 + reglist =3D adreno_gpu->info->a6xx->pwrup_reglist; + lock->preemption_list_len =3D reglist->count; + + for (i =3D 0; i < reglist->count; i++) { + *dest++ =3D reglist->regs[i]; + *dest++ =3D gpu_read(gpu, reglist->regs[i]); + } + /* * The overall register list is composed of * 1. Static IFPC-only registers diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 124c63c4615930b00c64e488a498163ae35afccd..0b17d36c36a9567e6afa4269ae7= 783ed3578e40e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -45,6 +45,7 @@ struct a6xx_info { const struct adreno_reglist *hwcg; const struct adreno_protect *protect; const struct adreno_reglist_list *pwrup_reglist; + const struct adreno_reglist_list *ifpc_reglist; u32 gmu_chipid; u32 gmu_cgc_mode; u32 prim_fifo_threshold; --=20 2.50.1