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Based on this flag send the feature ctrl hfi message to GMU to enable IFPC support. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 5 +++-- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 34 +++++++++++++++++++++++++++--= ---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 3 files changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 18f5fc2c28e33d81ccc248216cc018300c81eb77..d6297cc7fe664a74224c441e877= 050612714a3e4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1961,8 +1961,9 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct d= evice_node *node) if (ret) return ret; =20 - /* Fow now, don't do anything fancy until we get our feet under us */ - gmu->idle_level =3D GMU_IDLE_STATE_ACTIVE; + /* Set GMU idle level */ + gmu->idle_level =3D (adreno_gpu->info->quirks & ADRENO_QUIRK_IFPC) ? + GMU_IDLE_STATE_IFPC : GMU_IDLE_STATE_ACTIVE; =20 pm_runtime_enable(gmu->dev); =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/ad= reno/a6xx_hfi.c index 8e69b1e8465711837151725c8f70e7b4b16a368e..550de6ad68effacaea09751891c= 2528464bdfcc5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -21,6 +21,7 @@ static const char * const a6xx_hfi_msg_id[] =3D { HFI_MSG_ID(HFI_H2F_MSG_PERF_TABLE), HFI_MSG_ID(HFI_H2F_MSG_TEST), HFI_MSG_ID(HFI_H2F_MSG_START), + HFI_MSG_ID(HFI_H2F_FEATURE_CTRL), HFI_MSG_ID(HFI_H2F_MSG_CORE_FW_START), HFI_MSG_ID(HFI_H2F_MSG_GX_BW_PERF_VOTE), HFI_MSG_ID(HFI_H2F_MSG_PREPARE_SLUMBER), @@ -765,23 +766,40 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gm= u) NULL, 0); } =20 +static int a6xx_hfi_feature_ctrl_msg(struct a6xx_gmu *gmu, u32 feature, u3= 2 enable, u32 data) +{ + struct a6xx_hfi_msg_feature_ctrl msg =3D { + .feature =3D feature, + .enable =3D enable, + .data =3D data, + }; + + return a6xx_hfi_send_msg(gmu, HFI_H2F_FEATURE_CTRL, &msg, sizeof(msg), NU= LL, 0); +} + +#define HFI_FEATURE_IFPC 9 +#define IFPC_LONG_HYST 0x1680 + +static int a6xx_hfi_enable_ifpc(struct a6xx_gmu *gmu) +{ + if (gmu->idle_level !=3D GMU_IDLE_STATE_IFPC) + return 0; + + return a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_IFPC, 1, IFPC_LONG_HYST= ); +} + #define HFI_FEATURE_ACD 12 =20 static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu) { struct a6xx_hfi_acd_table *acd_table =3D &gmu->acd_table; - struct a6xx_hfi_msg_feature_ctrl msg =3D { - .feature =3D HFI_FEATURE_ACD, - .enable =3D 1, - .data =3D 0, - }; int ret; =20 if (!acd_table->enable_by_level) return 0; =20 /* Enable ACD feature at GMU */ - ret =3D a6xx_hfi_send_msg(gmu, HFI_H2F_FEATURE_CTRL, &msg, sizeof(msg), N= ULL, 0); + ret =3D a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_ACD, 1, 0); if (ret) { DRM_DEV_ERROR(gmu->dev, "Unable to enable ACD (%d)\n", ret); return ret; @@ -898,6 +916,10 @@ int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_stat= e) if (ret) return ret; =20 + ret =3D a6xx_hfi_enable_ifpc(gmu); + if (ret) + return ret; + ret =3D a6xx_hfi_send_core_fw_start(gmu); if (ret) return ret; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 9dc93c247196d5b8b3659157f7aeea81809d4056..390fa6720d9b096f4fa7d163964= 5d453d43b153a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -59,6 +59,7 @@ enum adreno_family { #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) #define ADRENO_QUIRK_PREEMPTION BIT(5) #define ADRENO_QUIRK_4GB_VA BIT(6) +#define ADRENO_QUIRK_IFPC BIT(7) =20 /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. --=20 2.50.1