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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7723f4858e6sm24285076b3a.4.2025.09.07.19.03.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Sep 2025 19:03:09 -0700 (PDT) From: Jie Gan Date: Mon, 08 Sep 2025 10:02:01 +0800 Subject: [PATCH v6 9/9] arm64: dts: qcom: lemans: Add interrupts to CTCU device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-enable-byte-cntr-for-tmc-v6-9-1db9e621441a@oss.qualcomm.com> References: <20250908-enable-byte-cntr-for-tmc-v6-0-1db9e621441a@oss.qualcomm.com> In-Reply-To: <20250908-enable-byte-cntr-for-tmc-v6-0-1db9e621441a@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Jinlong Mao , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan , Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757296941; l=820; i=jie.gan@oss.qualcomm.com; s=20240927; h=from:subject:message-id; bh=9cRSlY2NurvnURIS4RORNBk1ASEWuw2jDevqbo6Yazw=; b=tbAut7V9y1GHLMtaEckyjFizzcfbfFKrXsRyaR051mOcnrkay17afbh0raaPOgNxvrZC7TC5b 9r6YmIT3PiPC0Q2P2HRKUC5MJekXUJa6Xeq74ntPUsDPgLOyqJilyBz X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=OZh7JyRifqJh4xmrcGgmwa8/LCS8O11Q+mtx4aZGmi4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAzOCBTYWx0ZWRfX5qZXup72xTM1 M+adnQ6MWxP2FgQNjgbChairecGYzBAlm5Z44eEqn4YXB5nalXmwRxJl0FaZr4MRiAdaoZ64uCH oUA8tdwj+u8VRjTVh6Z5he38Sq7LxeKpOWUsItUPOFE/HNRLeSQAHq3BBGiODbkiuY1OyQxd6tT vcbPQWJLPaqUMO86r7rgftzV5CN26GpbXW+fIRe4WL5q555GeF+u9TmZPiDJtQNSKF411Dzjr5R sW0Ui0xRkubhg2ZA5pOen4vSi8vAVE5aigxjxfqGDpwQxj6qFP3wu0THMNC2Zi2dEkXUj1PWxCE Euznr+5nUh8E02Y5g9JRu9n5oCxDVaII2RQeVSZDMKxXqRpUiYszwvNQ2YZJQpOGLY8SY7u3bBd 1h/A3rP0 X-Authority-Analysis: v=2.4 cv=J66q7BnS c=1 sm=1 tr=0 ts=68be395f cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=gBkj9RZkAcI1HbXH1KoA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: jZtdjVWjt9qZLd9plqXLmJQ3yrIqMTaL X-Proofpoint-ORIG-GUID: jZtdjVWjt9qZLd9plqXLmJQ3yrIqMTaL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-07_10,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 spamscore=0 phishscore=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060038 Add interrupts to enable byte-cntr function for TMC ETR devices. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/lemans.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index f5ec60086d60..0a17a26f85a5 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2774,6 +2774,11 @@ ctcu@4001000 { clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; + interrupt-names =3D "etr0", + "etr1"; + in-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1