From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pg1-f172.google.com (mail-pg1-f172.google.com [209.85.215.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F9722F616D; Mon, 8 Sep 2025 10:00:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325649; cv=none; b=UAhE0M6FLu1T2VYmJrchm5hm6PWMJ/029adVYa9vthasNow0m0u6M1LWfsLHTzMxjSw0GcrGpLgMrrrg7j3L0twtXWrtikN5CCoA4Rf0TfDQFRKfctX2ez1htejOAC3Y+MIdRWFYJ28oGqOsDWIAnrZxUApUBbMlBuL5PyXibPI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325649; c=relaxed/simple; bh=octx4ZTnNO/R4DCoPqgavGVNNjwOBSkdB0RJJeuCRxU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qCRflu56dgJ85AQMB7B9aG24BAp6Sg14EUlTBP4IBAe2xXIvzqChibJFecKsT0bclLjhuy7U8gCSho1TIwX77If/G5HsMeIHn6ZkkSK60YnVtieDcSMjv/YdZCQgCVN8suBi0pfQkDLtBflJRDAt1qyQ7wedkkq733jOz8M3Zgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=h6dVBZX8; arc=none smtp.client-ip=209.85.215.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="h6dVBZX8" Received: by mail-pg1-f172.google.com with SMTP id 41be03b00d2f7-b4c53892a56so3760109a12.2; Mon, 08 Sep 2025 03:00:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325648; x=1757930448; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=v7IroGFfuMHil+70rPWoixnASrFWM1LVOm0U4Tub+go=; b=h6dVBZX8kTXRgvExG5H6nOX0I10x1YS/RkpPmGK95anZKTAtm8H54flu4moDngqodN L274Ic7XluKgMTzHkdVqMog/IlzDdeovWSYXEM0pRANueH4nYDQKJtfIh777RxSK/xR8 27wtCmir8flzYNjk1vUmP6CR+kJAVIWuJpo0SFowo+KnfOfiwTf9kdCiKoWOtv8GlzbL 3rPoW/yjV7WkWjNJHt79lrP9Mkp56qIs+qjQwTf1Ygww+xejGnFDd983aTOZW2+RD7Cr MHjiWfKd0hSCizGiqyFndQtQGKn/3up2yFQ3ZQovI8PXOR5HwEx/g95cjlMxttFlXHzF PsHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325648; x=1757930448; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v7IroGFfuMHil+70rPWoixnASrFWM1LVOm0U4Tub+go=; b=VcAET01loC4shhrQemH98BkQkGh7tEBYaHk4CZGwVCXddaq4MiDXrsI0OKYCHntS6n FfllhkuGf0oOoAJerMHBLru27gxhrn5EjGZ3ed+grxY+EtGGWmDUMXC8t9ZxLNti4TtH NGtv6Fh/XwFM6BmGCSshIF++qIK3N218WXxLlKOD4HnLI9izGs4AQ01tl9meIX3HZAsu S3C4JrYTztoZNQLEvwl4ceo0Wh4HDSWjvAHFVYl3Wc6C+QRJ7w9vrlg3IKExxeK8cRTh JiVaLgIfNa1czSMOBnGo2jThWbZDEGfHWHOSICdxzQYoxanWxotCcMVcsXI+W5f7n7Wa 1E8w== X-Forwarded-Encrypted: i=1; AJvYcCVTCBGWYbtClPmrMZOmVeStUkKR0vIOwEaIT102gxpByU3yZ+r/zr6bpMfBxxeHKEfMy1Z5cpAAiHWybCl3@vger.kernel.org, AJvYcCWYgQ7f2RuxPuq6s3pjoJ5BBVQtxLot7xQbMioji+Qn5s5e0aPQ/3khOCWYl5KIqiu3i+TQZKOOK8gn@vger.kernel.org, AJvYcCXvbjMpdY+/ynwA6SpQdxpaOTP+eSpWsqqZ7lX1/rThMPbh2O9FF8tcd/r230YvDyDLErWbP2gWgGCQz5tHnfglYQ==@vger.kernel.org X-Gm-Message-State: AOJu0YxtlHS/TUzzFo8kJrXkr5SLxyuZ9E+Opo8Xo4NdZ/4EKzNMKlO1 M09rJek05dTlST1LR7uOAp8rBR1YZcf0cmSD9wrRDIT/ZtMg2Ced3L7h X-Gm-Gg: ASbGncsrRt7dkc3OvUWEqoKtSeiLm8D8/C2jMYoLA6uYhJ4RnWZVNxFPnmJgOVD3yXY 5DqEuFCj194gUwVBh8tntWgBtuguHRJ3y9xszUYpkyWgpxAeW86BrjaKHf/2Jbi9X6BLl97uPKF qO3LhLtPhSWYJe0suRRHXXWGJGR4hq30ChuIhP5ralCL5cXIK9CBeKXYV2VRw1nu2Lfri4NCKRs zF6Y7LzkW4YRv4pJ17YrZ5omUsuYNz33KMHD07elQi0WYvZlFXgBrHZUUiqTWIGadGWFNDRio24 OMnkoorAm6CyuIvbVgRUXoBQTRov8CBDLs73/XwuMSE/UGVkoJ27USw2doY1lXftQlycehlaJx6 0TlClWJDo6fisfqZa8K1Lk6GTXU/YcfpSlt58UQ== X-Google-Smtp-Source: AGHT+IFsPZJGbWQibtI69hZHXu8fKVk5G6jBIPDZggi8j75kOe9U45Z2azxmFroNNw3gmJ/V7Ni/Eg== X-Received: by 2002:a17:902:ec90:b0:24c:7bc6:7ac7 with SMTP id d9443c01a7336-2516fdc7190mr101918085ad.18.1757325647510; Mon, 08 Sep 2025 03:00:47 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.00.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:00:47 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:25 +0800 Subject: [PATCH RESEND v8 01/21] dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-1-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1102; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=octx4ZTnNO/R4DCoPqgavGVNNjwOBSkdB0RJJeuCRxU=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlChNFI3mthcIeTlCYyHJhPM7C5e6BjzCC1N tL6LoHRUq2JAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pQgAKCRABygi3psUI JNUTD/0YnBxui5mvov2K8mWd9O1tHzRdmwtmrjY7djVyJI5LorUssKVMdKsrPFSkBwwilP42wqq KKLZwunYeSkkC+QRtBrgWnK0Dnk0V4GgAx0Zxz/5R2K8Tb8HWN/Tl/Wp8OYPmBZig9UosPdVLT0 tRZQo+1EhuMsr6WGqsGVDG16LP7rlqmBK2+yipL7LBZgGNM9DP6VUR3NZ1ji794Bo/zvxWPK6S2 2INBnCWOCPmbj3Y7ucHBjqQ5Wqo6s+ZUWDmPAt5qty6Pi9rS4IdDUHQd8RNiDCRse+HWqaMWuPH VdlCbRmMSZWzkRtNamANXo/d4ByNcC9mmGlpx3GQa2scfPhATeFipJwNm9WqwRdxswkqGUUiyqm Eu62wk88oVRSdAJxJUtHZ3iiTlbnkWpc7w3sXb5U941oBDcAhCbbdqVVXGBeDMJY7l27HOK/INi Pkm8Ji+xmY3aKOh4ccjw4oYiIZ7A3OZrzCK/Gsfj/eecxPlR84cu2i8OqqRtvficgTiIih+ULMU VvDtFCWNaGNn7OoObj93WI5B9VWzWi6s7SmA/cSe9sQ1gsoRO6Idfb/fIkQGZjSNorSbmiTeYRY SfbZuf+0pflYNFivXnZu0AlkZdhHQQIMJPDgL5Z2QkDvIvMjALrX28eDsTFmA2b0PDHgiyZvNyp /OYG76R7YW+Sz8A== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Document the compatibles for Apple A7-A11 SoC CPU PMU. Acked-by: Krzysztof Kozlowski Signed-off-by: Nick Chan --- Documentation/devicetree/bindings/arm/pmu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation= /devicetree/bindings/arm/pmu.yaml index 295963a3cae799a54560557137dd6b3cf4bd00f9..3726e1b78c42f150cf1dc68a6b3= aa3541517c311 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -22,8 +22,14 @@ properties: - apm,potenza-pmu - apple,avalanche-pmu - apple,blizzard-pmu + - apple,cyclone-pmu - apple,firestorm-pmu + - apple,fusion-pmu - apple,icestorm-pmu + - apple,monsoon-pmu + - apple,mistral-pmu + - apple,twister-pmu + - apple,typhoon-pmu - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu - arm,arm1176-pmu --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pg1-f178.google.com (mail-pg1-f178.google.com [209.85.215.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02FA81E572F; Mon, 8 Sep 2025 10:00:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325654; cv=none; b=nJ0syj04t0W6CklASn/D3bY+rUZuOSk5ycWbPSXYlRWHeg12qIQEL4vS78leKYRIW8L34wxsrz2szwNkf4xuhKRDKYQ1/IZYAHTCURHPN49cPXBMOjbLdxOw9I4W3gH8XHilql/mvurXoALXeP8k+noDNzmmpzsuk2sHQFy/D9o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325654; c=relaxed/simple; bh=LWdyJWF3F8SjS8P7dCHoXr3nix46HR/GnW+584oj+64=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hSLGOpmzZIxcPbC5UdtXwPh2IPitQfrSrfwjfoGrzHARG65t3ODNhZAq7wKlIy3Thp0Zyimf/KEV3tFKVToGHTZL9SsQgvuTuFYJpyIsf/KtfV8lpGHOOW5xJQSh9xAyklMyVySenFapXw4jYdHCPqAYtXOj/8/HzMfep3y6eDA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bxhinYkl; arc=none smtp.client-ip=209.85.215.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bxhinYkl" Received: by mail-pg1-f178.google.com with SMTP id 41be03b00d2f7-b49c1c130c9so2847093a12.0; Mon, 08 Sep 2025 03:00:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325652; x=1757930452; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=DQMq4XFtoATrbQB4MivFxur0yQnArRqt8i7j0LTryyU=; b=bxhinYkl/5Af2JPmMWnu5sDFb9DK2t92h5gP2rgDIaQtXdkxdR0H8v8B7uIhPPbNI3 uP5R01CEyyVmIrAzokryV1MyJEMaXd6ujJ0O9M8I4id7nysBOnPojbZmjpoA87faqk6D ndujE4IkRhffYvzmo2VkXk3fEZKKN8y3TCg70f2uEbByKnDETK74vdzbe/Ct6xYpoC28 onU11tBFj+QCxnsd+e8tvYoVj9rUD6LQlxBfOyec979WdSLuvW47MN4xEZg4IHVkl9pr 0fxO8LLRhMyL0xEj0mt4tRxqW8fA22dXlZ41ZsGXHq8rdFtCzahx3nqBDdvCbgNYXArh kV/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325652; x=1757930452; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DQMq4XFtoATrbQB4MivFxur0yQnArRqt8i7j0LTryyU=; b=FS/bs3ZtuuuAmFS1gQ1OUTDI6o9j5sdHTrHQFG87UIghDu2ikCrcnV7LZUwer/erJ0 n+WBLstH+W2vowKPAFhmfzC40NtBqTFxOzES8tHR94KhD2xiwE7ep1Q44iy3Bk77snw6 2mFzxUI3zpUPUqOiThYojvFTA9YaLpd9kNLOcukBZiOF5Ggg+dCxQCNrf0lkQH3dLtxr mZCKjJ8AgU2Pl2FENXcp9IeiG8hQLuhZOdnPT0MQa4RP8lkmFf3Rok3gAieI4iYigFfJ t7Qf722OWKmySd4akYMwhoI1G8aPCiFIRQ7l4eqWfobA6DUjKS6F6CX6KwK1SsBV9M4d /xsQ== X-Forwarded-Encrypted: i=1; AJvYcCWICpQFRIAyD1WuUKuGJl3TV8xsX9Y+hDVUcfhaz79Yer58PHRaEcAtE9xmuaC9HvBRdLSQ9Elz358b1PpiAwDjag==@vger.kernel.org, AJvYcCXLwqp+Wk8TPT3Z5Fm5Zhgs7BuhSjWZSTcndq2KfB+WiwKushtczNB0MWKp4NLbhTj6UZVQabsICpyCuN2c@vger.kernel.org, AJvYcCXeTKlvi+HidNqYKBD4tL/zuUbZrrL7FRyBZh43w1AMAydK11iDzLXNKsgtvQeANLW8+L7O1RRWD8Jy@vger.kernel.org X-Gm-Message-State: AOJu0YyC6leRLyYyvHvx9KayZEjCQc/jVoc+RLkmaEITUdbelX9oPJrj AjbmEeW2ltvGDxUkRcx0OlEbA/wMeP2mqEeh1RIyWwII7rI3bMk+HGY1 X-Gm-Gg: ASbGncuUwqRjHalOqCgkIY8HM5QY9QMzW2PlCM6wcC4a1xrTs1mI2WnU6JVIszj/O/a ZVx+uBOTbYL8ktUVymYkgnhZTAaODb/cGXEqjJSxanovnomPMPjqSc6/dZTt1Od4tu8c3/MS61X s/uU56UuXjOkJYDdkboXKfa6hzK4JsQAVFjB8lXhAxJEjxuV16sbv7X1PM9H1nMxV6+ZxHIscYf FwAFdsEOvkPNLCoyJJKzjm/eCd3HPCtCdRRtKB+pqLH4YxI1HYweaoQjPv+LEGAPyS4O1tkCeMY ZRF6FZQElY+Q1716dLW4r4/FVT+VyMLv6GbBYFMbIb1Khah8lfgOKGqnqECwKftoy3G7eYR/I10 /4gRkSO0zLCHWugtLunOech/CrI0Hucihtyujjw== X-Google-Smtp-Source: AGHT+IGl1vTxo4904OtH4SWs6LUChVqEb8VgEVVJCvo1a6Vhe/4uyjIXKuDfOVxqGh5ob3vqwyQS7g== X-Received: by 2002:a17:903:2447:b0:24c:8984:5f87 with SMTP id d9443c01a7336-25170c4177bmr88762415ad.28.1757325652051; Mon, 08 Sep 2025 03:00:52 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:00:51 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:26 +0800 Subject: [PATCH RESEND v8 02/21] drivers/perf: apple_m1: Only init PMUv3 remap when EL2 is available Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-2-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1251; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=LWdyJWF3F8SjS8P7dCHoXr3nix46HR/GnW+584oj+64=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlCU22oAvgbtrscdWyafurkYoZy3NYlLu7IW hWt7fHK+GOJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pQgAKCRABygi3psUI JOdlD/sFhoqfCpqj7FgtxcF7snNtZue8D3D79Nk0lMIuUtqH/nory8bTsgP5FO/zDHh+FzhBEy7 GJUG5aMxsMgWbZ4oOhu4BcJsEnQ/HSTwuGElbI6pqsP4KbDS1zIvx2hOJNuJRGbx6jaB2f3ey0t 2p6/ABbDkq4/k+u26kcWYqUpn2dIdm60CPY9K+w8ymRjXil5oDJtvofwwxxccAQamA/PDtC9b0q V1iGE5JMO009hyP5Qe0XzUMxt9p/Xyep7q3SJy6/njas3ngxGwhm3J3l4W01bLaA8Ah/ClLiWYz S6se+MQzcAzrjnvg0UEmxRuIprQ76wagNthUVbO6yJ3MAWWGl8SboRYantMnCentWT5VNddrkcd A/aivnWTHEZ2j4v7EiqlW2rHR0j9cCO1DUMGQ9dh8HbZKkTs+Tz2qFw8Wk4tyLZs4+2ld3h7QnP NjOm71HU+AcueUvdudSQXiQwFFwb6WSBvdnod6JRmUo5ux5T2oFav2FobmJ9iMAewbs/ST6M/Zd VxA2irnqTESdTNa9WiNDiXkriDS3z05nttR2zhuQTXcQmlplp30PUVF6IwTMeL+LWvX5xEl/EP0 JjX0qtoT61ruclg+NO98M0UvrM2ll6YLMr6gls5yLrceca8/2rMdUo5cbp3nmCSMNd8Zk7tCfB1 PchvliyKYEioyKQ== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 The events in the Apple A7 PMU is very different from the ones in M1, and EL2 is not available on Apple A7. Instead of assigning the wrong PMUv3 remap on A7 or declaring a new PMUv3 remap that would never be used in practice, skip initializing PMUv3 remap altogther when EL2 is unavailable. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 81b6f1a623499566ef04d04075752f34e2cb6a92..f3948528e28e0189efd0f17fde0= d808930d936af 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -645,8 +645,10 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 fl= ags) cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 - cpu_pmu->map_pmuv3_event =3D m1_pmu_map_pmuv3_event; - m1_pmu_init_pmceid(cpu_pmu); + if (is_hyp_mode_available()) { + cpu_pmu->map_pmuv3_event =3D m1_pmu_map_pmuv3_event; + m1_pmu_init_pmceid(cpu_pmu); + } =20 bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 995DE2F60A7; Mon, 8 Sep 2025 10:00:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325659; cv=none; b=l9gOLAH+6iL0XKEVU+6PsEbGf/iX9IoeKD/91GSDfx8VMqWH8WwtFLt21YbYkcdukBqo5p0auITt1vRdnavPyzLuwcf9tWdTwNeIvJltpXOcrHdFUYExjitEh2Se4CIpt1BP6Kmx+Bo3AJx0D1Yth1gEifN9xfZVwto636zsPzo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325659; c=relaxed/simple; bh=QXdFCVGEPqTyu8Bm7SIf1fxdHsV0PUqAo42n6ezyRRw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UGWgxlV2Sl929Y+he+OAO7LtPt4wG2Svamd73H+QqE6jY1URCUSm1xRwJEjrO3sGN6iXVMqXWsy3RJ9ts9b0m/e87Kgu7WuVzmETQrIT7Ytv4LHh1tJf4Fv9nBA2Q5svym/A1Cy2s6fAZnh2iq+krnkGg+BWxGvJaPu4iNfxe5A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=P74FKUwf; arc=none smtp.client-ip=209.85.210.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="P74FKUwf" Received: by mail-pf1-f179.google.com with SMTP id d2e1a72fcca58-7728a8862ccso3641695b3a.0; Mon, 08 Sep 2025 03:00:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325657; x=1757930457; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ZKGU1abQVfuJ6I1lGgEqdrdZCTshmOZZLCi+h9rWnIw=; b=P74FKUwfmldYcVZx3l6Pgq4JvxAScwq2vUb7NJajdN8mPLBdWmUMD2ARJrCFSPClEp 75JWCMSjZiheN7xdQ0aToR+Znb0FwNhZ0UMb+YURAHQtAsagO24tb0oJoqRI6hi8k+Xa a5zjEyGycZJYqC9KMt+TaXP3WFIWW7EvZuSeioOH0rmY29/4SgaQRskTOf2NP/HIkWy1 Nla76shSj8cKX3ccbVO0ffpvkzkBL/8fOcdfA2Vr+VJURU4iLjNdhE82ER6jjqw5AWFX 7aoZ8tuUk+ff7Bu6exrLMOyn84jxjFJOxdo2CZiR4jBST+QKJXO4KdgC3PxIdk5XXSWo s9EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325657; x=1757930457; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZKGU1abQVfuJ6I1lGgEqdrdZCTshmOZZLCi+h9rWnIw=; b=Q+L3wMdgNKu4dotweI9V9auOD3MiSVST4vavFDivoojPGSoCBbDT4MpWCLEqVEyJWz 1hwWAalC8gzEg/huXy4Uz+SdGmuW+1Ezf7yzgugURby/28FfV4hhQ10v5GnZBkIWiR2l g/NY8ifoYN01iLIBUcOCeyqsLIKK9GQb35gxANiGbeZDWrqUkECPR4r7NnAjEEbE9an+ AP3kBe/QYG+5++5Y9eLnInVl6fJQ9w35DAm73OD3tnlHqRnDW45Iu8JySQ+f3V4eWknx vBJYgI1M0Pdv9yvv+h78Ew9vydOOKudcvO+igj1Ij6BNF971MR/Tt1avIRSjY92Ou1eu 9oRA== X-Forwarded-Encrypted: i=1; AJvYcCUeB2pbg+RB5sjTF59TPTRzM+AQspjN6/btpfNPp3A2Iq83VgDNDsqd/jRlCCNzpRqQ3Br1uyzZtLCObNYTODY+EQ==@vger.kernel.org, AJvYcCUgemhrMmi+zNuk9N0l3AsNnaZ1z10yemaTRpKkG/lDOgdblJ7w1wu/PqNHBvRcYpRxRoo/D7SnZqXQErxN@vger.kernel.org, AJvYcCVL7CJFjv+sJ2HrOOzH0ZkUv1qoMKKQGOYUWAo98oGeKmrqmAue7MFnedOELBCnL3kkV6l1Na/OIAlV@vger.kernel.org X-Gm-Message-State: AOJu0YykR5A4Ze/lvdGjdsHfxhm16uhTeVZKWaGVlBlpjkruXNfbvbuY /pYdyvn0nkcfhYlTNecZw8dewkoOeq9J0XFwal02/xH02IlNOZsUZdpf X-Gm-Gg: ASbGncs8ngM4mEKfpPJLHaLcnYxELU2RA62NAHAfeZcJqw3VfOg4eXHrl9us38FAwii rbRG71udw5kqVZg7saSlPTAWegZHJsngGC0qbilHYm/1Wl7DfMzORwKsSxnaSIBSWqIqmBx86If nTx/H+2Ix6kwm1JOAMNgQCR/CUUCqllDqxuP7ev/ssHimS9x8aFbqg8pJAsguNdtrmO3VA0Tj8u 870D7PY16yKsRdMjq0UMMhAqnjqJ6C6XIeTmM7dIbVhuJM368DssXgivngVg0T/vW/3DmDp3Res PjWas6rOaAFWjA7lIaSgZzT2VymHBCh4QbJOQnSweMODEllOEReKm6mQB4VWCq8W+9O/L/ghBmv 2i4okrT6i8V90DQZDZucpaPWrNjA= X-Google-Smtp-Source: AGHT+IG8f7QWlYnkY3npMDxRjSVlZs6moYuSIY71etdNfcW+FyDv3+n517pdY5xG+zHBFK5Cwi4wKA== X-Received: by 2002:a17:902:c402:b0:24c:ba8e:c5bc with SMTP id d9443c01a7336-24cedc83ab6mr163142315ad.8.1757325656753; Mon, 08 Sep 2025 03:00:56 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.00.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:00:56 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:27 +0800 Subject: [PATCH RESEND v8 03/21] drivers/perf: apple_m1: Support per-implementation event tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-3-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5769; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=QXdFCVGEPqTyu8Bm7SIf1fxdHsV0PUqAo42n6ezyRRw=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlC0et+/+z/qtxr5xUy6bUrh15N0o6KHo8wQ 30tLI0+/N2JAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pQgAKCRABygi3psUI JPpzEACVxTd3EvWUAjSmnAg5qkeRXyzv2oSB43nFGnYBrSn3nbiIr/XzPOVAUPZtXQiYYNh73iC 6bCtU17u5gIGtcU6pfvVoB4YWzwrDRG759MI5aU6+1P4kvsQO4zPQTpmvyRLdmHXFXgdNsqcpvv m0cHQF+Ts+RICEnKb1273DabKgNmGq7tfBatr48DfQnYXJJWGBph27/qZhJXpZ9i+Muzgaz+AtI SjZvxVXQIdvMF+wxsFm7MTJ6w74w0Ebuf/RsoxpmkVVAFqRrn01G4c8uu5aDHTVY+L2xuLp6JAm CMZT63tlvPWVy8DuxTPHpu+GuJuilhYO1+e77NEAT9Jl17hBcsNpIJtg7T6eHEe4JH1DIgQsxFH b7LMtJzxPYyl1T2tkrsZqjHOcE7NXx+VthTZ8wST5GT+cw7kfJaXRYbzeuSaGLscoGcRQc2sHQv KP3JM7beuodYfVPmjAX5Y5wKMH7IbcEnFo7AcPhUZrk3h+7s8b7/CU8V9ETFrKB4WldYugbVMke RXKFpUM0wrohJBO9Gcsuou8JqCZPkFt9OraZDrJqm/w8XfIaToSHRurHq8bhSfpcWfDjPMbOZJ3 Se4oSUhlVT7S0z6x1hVyJ8XN8R7ozMtsSZ1UXXGxPyoiEL8V7/aqqXDj5PIuNseLFf8MfhJPTkP dBH32S9OHOPIZ1g== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Use per-implementation event tables to allow supporting implementations with a different list of events and event affinities. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 65 +++++++++++++++++++++++++------------= ---- 1 file changed, 40 insertions(+), 25 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index f3948528e28e0189efd0f17fde0d808930d936af..b4ab6a3e5df965b7ef450d7e533= 995f3cc8633fd 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -43,9 +43,6 @@ * moment, we don't really need to distinguish between the two because we * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. - * - * If we eventually find out that the events are different across - * implementations, we'll have to introduce per cpu-type tables. */ enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, @@ -493,11 +490,12 @@ static void m1_pmu_write_counter(struct perf_event *e= vent, u64 value) isb(); } =20 -static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) +static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event, + const u16 event_affinities[]) { unsigned long evtype =3D event->hw.config_base & M1_PMU_CFG_EVENT; - unsigned long affinity =3D m1_pmu_event_affinity[evtype]; + unsigned long affinity =3D event_affinities[evtype]; int idx; =20 /* @@ -516,6 +514,12 @@ static int m1_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return -EAGAIN; } =20 +static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, m1_pmu_event_affinity); +} + static void m1_pmu_clear_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -543,7 +547,8 @@ static void m1_pmu_stop(struct arm_pmu *cpu_pmu) __m1_pmu_set_mode(PMCR0_IMODE_OFF); } =20 -static int m1_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_47(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* * Although the counters are 48bit wide, bit 47 is what @@ -551,18 +556,29 @@ static int m1_pmu_map_event(struct perf_event *event) * being 47bit wide to mimick the behaviour of the ARM PMU. */ event->hw.flags |=3D ARMPMU_EVT_47BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } =20 -static int m2_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_63(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* - * Same deal as the above, except that M2 has 64bit counters. + * Same deal as the above, except with 64bit counters. * Which, as far as we're concerned, actually means 63 bits. * Yes, this is getting awkward. */ event->hw.flags |=3D ARMPMU_EVT_63BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); +} + +static int m1_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &m1_pmu_perf_map); +} + +static int m2_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_63(event, &m1_pmu_perf_map); } =20 static int m1_pmu_map_pmuv3_event(unsigned int eventsel) @@ -623,25 +639,16 @@ static int m1_pmu_set_event_filter(struct hw_perf_eve= nt *event, return 0; } =20 -static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags) +static int apple_pmu_init(struct arm_pmu *cpu_pmu) { cpu_pmu->handle_irq =3D m1_pmu_handle_irq; cpu_pmu->enable =3D m1_pmu_enable_event; cpu_pmu->disable =3D m1_pmu_disable_event; cpu_pmu->read_counter =3D m1_pmu_read_counter; cpu_pmu->write_counter =3D m1_pmu_write_counter; - cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; - - if (flags & ARMPMU_EVT_47BIT) - cpu_pmu->map_event =3D m1_pmu_map_event; - else if (flags & ARMPMU_EVT_63BIT) - cpu_pmu->map_event =3D m2_pmu_map_event; - else - return WARN_ON(-EINVAL); - cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 @@ -660,25 +667,33 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 f= lags) static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_firestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_avalanche_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_blizzard_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static const struct of_device_id m1_pmu_of_device_ids[] =3D { --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09BAC2F8BF5; Mon, 8 Sep 2025 10:01:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325663; cv=none; b=WWVn+fLhVDVBcumm/VXVxxzpn7dqwOoEWrbYeirgzBI+5r+b1zK+twylSyJvk2Y/Ml4BgvTYTx5pX4jiK6z6B8uBfAuoSiIMErUT89TFUEFzjNWleNhL/Ub/1IsYn1VNcTSsauTO0TO3KYpezCgrAtOZMXs4yNgCjFTWaqn/c3w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325663; c=relaxed/simple; bh=e978bWoFjBQgsdNlqdWrRQsmNCkoajFMktc9t6zXMkE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZQX0C3Q9esSOjdGEliXYDpOt4YGCfmwr2Z89yUAZ2JVQpLAsKopxmiPA7YnTddaZ41aEruWCLyl01JcRMoQDsgQvlF3dq9zZEY2lOJ6GU6jwm2jfDk43iPb3qBRyBvuYATGMMRmanhgCh9pRTUB92KLlHMpO2Xeg0eRJT+EyQ40= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Tc0U66Uy; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Tc0U66Uy" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-25669596955so8200175ad.0; Mon, 08 Sep 2025 03:01:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325661; x=1757930461; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kSUQIaWycRWPeDhTmGOQryGYmMnqnnTORM1hSoq/o6g=; b=Tc0U66Uye0LBB3bWb2zbnT98+1T+IeLO965rGslkIho42MdCSHLSash+FCjIjZBsa9 kUk6VLmf2pd6rLX1eg8kp1MdDbtH9JMkp8MBdHMKfQlgbVwb4y2l+xX7vAASUuTUQibs aAjxyvwPhp9k8d61eGUzPSOFPnrv7iixKJ5XcMWvIDnJB/M1OlaZrYz1qUnS1/FrTuVs M67gyqmNXRZeVqFMnFT7v2wbY8S1rlMZSG/oplTMGbpO959D8cBA3+kTUyniIBhvDaQs 1Fxy6MqPvgxRl7bB/JeYka5E7LCnu2Zu7QuT26rjXAySGeEaSKeM2iZOm/3fPkPVJ1By X59g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325661; x=1757930461; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kSUQIaWycRWPeDhTmGOQryGYmMnqnnTORM1hSoq/o6g=; b=oeJPat+GUPstQkplphSverlT2ILo9W7CHtvFLOM0p8eKB8s32dy6hgBGPg/coxQWP2 V3G1ohgAbsMwh9LxL9gvTQ4VsPaCEfyLGKRDXhJRNjnbGegd+SVVVt2wjcgb9+cPLluV sSto+WSKZy+r/abA5O7lxLizDCE468XAeruo51SOlC58qGhSArMr9lZbPirgDxri1aT4 D8aU2+jrTZH0nx/KeR9IDeCqwzjUUQgKuM9ZTK1CrNbnF98oRrIn0Uw2pyZu7qOLxK3q eY+Vqi4O8A1YH1FrGjRGvFOB9UT7CeQEQGhRg5i3Dc4WxsoKX/cf7+14cFq2iVpimjLr NUaA== X-Forwarded-Encrypted: i=1; AJvYcCUC0PFWPRCDerX54fTWk9uHw3qMJEPvUCFwV7qLw8HQZff7+fnADcFmjIKpdN90QQr6DGsrlkY5m3UY@vger.kernel.org, AJvYcCVov8VT81kZA64la2IYjidBTJZ09AyVjISRlXeYS+9Ofe5+O+Wfx0Z4d2PNnPIVNR6Zh9tuEN7IjpzsBe+k@vger.kernel.org, AJvYcCXgDYGYE0tgKkAg/NhxWLuk/GTgQcjBCWw5OhKozhNP3Idd775l8m1Dpuw6bQUyIUj73iV3hakQIuymJJE8uExn2g==@vger.kernel.org X-Gm-Message-State: AOJu0YxshwRyxAZxMrlwm84/L/5+SV2cGdrW5MxMs16v99zK6Vts6U+u KxfR7Gxu/MPUv4zC1l8euPfOmrd/zEa7phx5Lwzm3LgIhAHBlEU4JR0m X-Gm-Gg: ASbGncuI5EQojzjax4kN2D7GKLcnlZQl8XdbvPx+hkRfSF2aJ78z5moYTrooBcGBnY/ cKx6YRe1OuXM5faKmMw18wr8WHsZPT6dY6hy9jiYLsYf3W1IYtRKCIwUAAF8vmaJuRfquR2Tv3V 8pyaxMoxdN2obqvez8ggevJ46c5EKWg0HhAEkRa/M0g+IWH54vatrKdC8MgS3Ut60zKkxbUdt0N ifxJ3EepSgqgq4+A5fiDraTWROySUdXLSlvPGBpzMglPDYhKDgMUcUHo4yWJolsx5R8RlmNkU5f vKcubPXGNcq0PqkEUYvARCeuKsQgi2mO41vaDGNrTbmalLN9+VMzEI3xJ50X8cFdszAYd9XqwWD kD8DlWf1siP6CkLS8nSvW22ffW84zsS/bIZLmpg== X-Google-Smtp-Source: AGHT+IG11e5yGQ6mc6A+u6URsOan+E/sP/pcqh8w5VNsDhDKar9RrdRNruPHJgRVAnjqfyCyjH1Reg== X-Received: by 2002:a17:902:e5c6:b0:250:bd52:4cdb with SMTP id d9443c01a7336-251736df0e2mr88144745ad.32.1757325661328; Mon, 08 Sep 2025 03:01:01 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.00.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:00 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:28 +0800 Subject: [PATCH RESEND v8 04/21] drivers/perf: apple_m1: Support a per-implementation number of counters Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-4-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4845; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=e978bWoFjBQgsdNlqdWrRQsmNCkoajFMktc9t6zXMkE=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlDf+O1g150hHA5Hs0I/aUaLmgR27sqVHJQs 3djsJTRQ5eJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pQwAKCRABygi3psUI JGxAD/9Q9nmhaDwo8/y7zqJCPr0t6UcR8TjZGcnNwQiqAW4DjwMh5R8o6Pra744BBIYH8GfubUD YDF7aXmWtHvBnVXTS4Hl9YpSV+4QpTuVPt141vLZ24paPzXJyVWg0tc/lzg7xn0T1ny+VKmrbDB Xy/EF/rZMNSSIzMEJ+bzdfbNlC1wlj/AnHv6Gj0vgqdJ4qPCOhym4ASBaptHHKfDfQ3Ogo56HVu na9AHhu6/ltmS1AtmFz1LKPAJUn+F3E6QRdnaWsyZdlD7FbCVzXogQ85wfdNs6bifQ3ha2P2TWa 4d9RAc7Q4s8B3EQw8YbOU4JdFAwGCDhEKXXAee4zrjYDVrbt5hSqm1ShFeBQ5b4qwGxH0sZNjzz b+BZ8ww0RZGTakwCYBoM6lW7BgT/ZqBcfE8sA6DYjkDJM/U8012SmwUoX8T8MxBfRtA1OK5dCzT Mlvq/mlVGUYejU0ageOkLD+Oibs8W2qma+seYazE5dX6G3MOhZY4Dvk34PeR+2C4jTGvR8lYaW3 Fi9O6ZcTXtd+zezlkAy46nu9sLthHQibo3ZuUZokE8k/BxZ712AiNkglf0BxfyBPoGhSfKFXcqi N6iG1guaDHzZt3K9I3UNzrfNLbdttqJARxjy+JHvG213JQx+KrL9K/gHKa1GlzmOsGgu6HZNsCB pmmMxHOH3bj2/mQ== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Support a per-implementation number of counters to allow adding support for implementations with less counters. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index b4ab6a3e5df965b7ef450d7e533995f3cc8633fd..b5fe04ef186f04b4af32524fe43= 3afb79979b791 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -20,6 +20,7 @@ #include =20 #define M1_PMU_NR_COUNTERS 10 +#define APPLE_PMU_MAX_NR_COUNTERS 10 =20 #define M1_PMU_CFG_EVENT GENMASK(7, 0) =20 @@ -459,7 +460,7 @@ static irqreturn_t m1_pmu_handle_irq(struct arm_pmu *cp= u_pmu) =20 regs =3D get_irq_regs(); =20 - for_each_set_bit(idx, cpu_pmu->cntr_mask, M1_PMU_NR_COUNTERS) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, APPLE_PMU_MAX_NR_COUNTERS) { struct perf_event *event =3D cpuc->events[idx]; struct perf_sample_data data; =20 @@ -506,7 +507,7 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events= *cpuc, * counting on the PMU at any given time, and by placing the * most constraining events first. */ - for_each_set_bit(idx, &affinity, M1_PMU_NR_COUNTERS) { + for_each_set_bit(idx, &affinity, APPLE_PMU_MAX_NR_COUNTERS) { if (!test_and_set_bit(idx, cpuc->used_mask)) return idx; } @@ -601,13 +602,13 @@ static void m1_pmu_init_pmceid(struct arm_pmu *pmu) } } =20 -static void m1_pmu_reset(void *info) +static void apple_pmu_reset(void *info, u32 counters) { int i; =20 __m1_pmu_set_mode(PMCR0_IMODE_OFF); =20 - for (i =3D 0; i < M1_PMU_NR_COUNTERS; i++) { + for (i =3D 0; i < counters; i++) { m1_pmu_disable_counter(i); m1_pmu_disable_counter_interrupt(i); m1_pmu_write_hw_counter(0, i); @@ -616,6 +617,11 @@ static void m1_pmu_reset(void *info) isb(); } =20 +static void m1_pmu_reset(void *info) +{ + apple_pmu_reset(info, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_set_event_filter(struct hw_perf_event *event, struct perf_event_attr *attr) { @@ -639,7 +645,7 @@ static int m1_pmu_set_event_filter(struct hw_perf_event= *event, return 0; } =20 -static int apple_pmu_init(struct arm_pmu *cpu_pmu) +static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters) { cpu_pmu->handle_irq =3D m1_pmu_handle_irq; cpu_pmu->enable =3D m1_pmu_enable_event; @@ -649,7 +655,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; - cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 if (is_hyp_mode_available()) { @@ -657,7 +662,7 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu) m1_pmu_init_pmceid(cpu_pmu); } =20 - bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); + bitmap_set(cpu_pmu->cntr_mask, 0, counters); cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =3D &m1_pmu_format_attr_g= roup; return 0; @@ -669,7 +674,8 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_icestorm_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) @@ -677,7 +683,8 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_firestorm_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) @@ -685,7 +692,8 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->name =3D "apple_avalanche_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) @@ -693,7 +701,8 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_blizzard_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static const struct of_device_id m1_pmu_of_device_ids[] =3D { --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BFFA2F7449; Mon, 8 Sep 2025 10:01:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325668; cv=none; b=S2oqfpC82OZpsrpblebC/QWnu7A9wmHi+ItJENLHQ/eJqx+9rsc2cfeoLlbf/M5Hv/v0z3j9KnunvHDm3NF3TVcbuxCxGgxYUJKRCaqoaRsZmMOuvstKziMO7LBLSkHSuhflJFc0+sR1RPZfX3+trGGt+TmsWoteLahUvwp75EI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325668; c=relaxed/simple; bh=C6Dad8JPpdCuqjz4s5GhSEa3XOS5lpXoC8lCTSueqRM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OFX6Qc+FriRTHHCo87GC6OPMmYEOjvatJpfDq7BcS+dBNY6jtb7YiTjYzHs2yUNqZ3ngJc1fp0ifaJm9JOOxFpDjRtqpuEwNeaACYNW/xEJL/Mm1nGhzindHOZbN/4NhLiX9vhwRne/38AEA2ULzG50hPnjCoT7uTgK8oxfYnlA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DkRODvFp; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DkRODvFp" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-25669596921so6164025ad.1; Mon, 08 Sep 2025 03:01:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325666; x=1757930466; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NLtZQAdEAm9Qpl1KbOMuUjIonMp2MqyrH/XDjYnJ7DA=; b=DkRODvFpJCw0RXQ8fPlzbm0QQ0DIpWtTOIUw6a3gCAmfyAWs/OWO6WLDT5oVR6NuLZ hb8ea5GtZoZ6v96XM5QkjpuSmicrp42agOd3ynYmbRlJNjF/GYZmYWfiQoP9r94z5IFC 3KVt47K630UCldy9K+ovDw/Dv3UDMG6yGoDghKuo+PZuyRVic6JOpxGD4iZpUBgBrynz rYPktRwkLkm8EavxCHzNw/ofYe3zs8SJiRg5GdLh0QvUMpaeaAMRCOK+YiRehFdVugvM 7Q/fA62QgZVirlWxknfGK3MWcHNpTJnoM14mn0GJTyPZYdMsbCsLEf6jFVrNogbxRrt5 Czgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325666; x=1757930466; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NLtZQAdEAm9Qpl1KbOMuUjIonMp2MqyrH/XDjYnJ7DA=; b=bcqLejVIjLjOoi1V+R+Pmk2CkHVkr2wo/dffCuhEGuxgD48Caq5H1WarxzlN45h0ak W1e1VAYs+e+boe/AkGPCLGSjs4lOVwuAmXKlmOk2JxZvyYOhMtgnr+6+1hJvH5sx/4Vk uHFZxlB6e//TE0pqNXM1q8gD9UE1No+1CtFsm86JPk3Yfw0Y04DuoyPlWtzsQyhBzils OpEvGTDqLaIoX0PclpLiT13KlGfYzxFD62XQsegUebBAHZLoeILcKWyMtSb3WcfhYtgo 8v1dcaPgcTScBkVkRmrTyLPlpeh02uSZS45m8hS3hlpiR5H+H+2JuC4GTm6boJqF/xyz DgkA== X-Forwarded-Encrypted: i=1; AJvYcCUfZsbkKr0IERmeX0/KF1yoZA+oNgGzYv+aBC0eGKlc9n5PmiO/JdTbM5YrSzHXzyjXofD8tYglTz+tGHi1@vger.kernel.org, AJvYcCWCq2uW54UGf+TlCZ0xA6SUJbms4FZFnwispC8HY3BGEoZrKzJ0WeMQHO87ziq/SZ3yxnIuIHsI9ar2dMxHmRuzQw==@vger.kernel.org, AJvYcCXe3xk9ZDf30qSGjAIUqpzQvZ1JjHsWr4rciGlB/g1W18Mo+LJp3XooCq5Ef937JqpFgTuyxX8jU5Gg@vger.kernel.org X-Gm-Message-State: AOJu0YwYg46jSYtsK+hGv0dyuG/uKxWR50neywAWbYbI5U1gsXVQMobM 3GIa9nBKPnBwt5vvG+2Iya8vqZDWvHkYvs02MkFc7jws4/zo7EIyj5YG X-Gm-Gg: ASbGncu7KTqxv6EYKFfpF8BA7jBCam9q6rrixT/AG04EygfhurfjXavkO81XxzNcv9C fCMX8OKhtsOViVh6LI0K58mfqbQbBFtoaaYXnZUbKTUFEip/Ft6u1iwUz1xBS2mcjAsFR0w+t5E D85CTXkbpstiGsHvEIujuql8PhXivZCMGeWkZY9iMYrXBud6jNFpqm1dvCqearCv/dD7GxjiOqe 3/JAb0MIvc3LJ63Mrb7lQm9Gyexch76yQuvCSAMIodrk8Za0rYzzc3FqeAU6gdr1cxhxGtJU0WB Y51o4PVIEjJMriGI3FZpXofHLoG7cPPBZr+wV9ywWZWbAFQ164F/vAbu99L+5kcG4CvMScZUedU MsERp5m+fSFtM5CFLxejH0yHbevoNyaqN3JRiBQ== X-Google-Smtp-Source: AGHT+IGWWHiKtpsu2QdAXRL82r5j04D9+oNux4leyEfdfdI4Mn5W+IrDB1mcVdqQVYqmtjY+ExOHSQ== X-Received: by 2002:a17:903:234a:b0:24b:e55:34b with SMTP id d9443c01a7336-251722922c1mr123807425ad.31.1757325665919; Mon, 08 Sep 2025 03:01:05 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:05 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:29 +0800 Subject: [PATCH RESEND v8 05/21] drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-5-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1977; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=C6Dad8JPpdCuqjz4s5GhSEa3XOS5lpXoC8lCTSueqRM=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlD3N+SiZMRkNdtDE0OP5I9wS4J2cex7dpSE Foy/InTsRKJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pQwAKCRABygi3psUI JCWjD/wKCDBrxnc0BnXSw+ySFzk06gEQT9Hag4HuvuMWKisRlL5pPvn9ri0BwkHcfdJ5TlgE2GU MFmEaXtrAXUNG8jL3DDiyBpeZWjLiQZo7G5ckwlKp7S6WDdPhzwFlb5TOsHjg8VUWIcf9wJUm6S 7wwzd23QfpnMP7k7xvALkJ4klG4koXG7ANuGbnSav7Y3cYEF/MgPaTUm4QyZt9pk0S4JZnZkN3d x+8UrV/pvBaSa7osMjj1RTU9ZCiQeGrlmfBo94vzdLy0i4oKzEb8RbkqXObHRaU8jc/9wR9a+YD y0SIRETKPpwYOxgkDBvhouVh2PSdEdO8DOEMsj7CNCdrdHmKVrzCDPNiAh8rsuZr9Oy/FcYBHDW 3KQ70JA0oB9I4xFyNBLviFDzWpHAgYqoo5DWGICYAXBRTsx+uGIP+GwKt/PfTrz7qPAhhkRREvr lYvPajB2umqznZFQZY8R1bGCnJEyO1qf0JAmj3zOhY/536/hZFcKZfuUvIlQvtBt42g5pExCIB/ nEMdo5Jbd3O6KU03jndXs5JNcJMKVRaZz2embvJlhy7ksrmAbb3R7MNKnLwAchDndToqG39uxjv zQbZ7WCDnPuMTJFCmmoIZ35OhcLCLNBtRcw/T9YbsCXG5QfVcyn8KAhmau/+NxwegBZPke0tG+n Ko3+GvN1XAO8cZg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for configuring counters for 32-bit EL0 to allow adding support for implementations with 32-bit EL0. Signed-off-by: Nick Chan --- arch/arm64/include/asm/apple_m1_pmu.h | 2 ++ drivers/perf/apple_m1_cpu_pmu.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm= /apple_m1_pmu.h index 02e05d05851f739b985bf416f1aa3baeafd691dc..8a667e7f07a517419c22a4f9309= 47347be8546f7 100644 --- a/arch/arm64/include/asm/apple_m1_pmu.h +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -38,8 +38,10 @@ =20 #define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0) #define SYS_IMP_APL_PMCR1_EL12 sys_reg(3, 1, 15, 7, 2) +#define PMCR1_COUNT_A32_EL0_0_7 GENMASK(7, 0) #define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8) #define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16) +#define PMCR1_COUNT_A32_EL0_8_9 GENMASK(33, 32) #define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40) #define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48) =20 diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index b5fe04ef186f04b4af32524fe433afb79979b791..fb2759069fe9e47146f0342fa46= e40f3ab836926 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -348,10 +348,16 @@ static void __m1_pmu_configure_event_filter(unsigned = int index, bool user, case 0 ... 7: user_bit =3D BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL0_0_7)); kernel_bit =3D BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL1_0_7)); + + if (system_supports_32bit_el0()) + user_bit |=3D BIT(get_bit_offset(index, PMCR1_COUNT_A32_EL0_0_7)); break; case 8 ... 9: user_bit =3D BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL0_8_9)); kernel_bit =3D BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL1_8_9)); + + if (system_supports_32bit_el0()) + user_bit |=3D BIT(get_bit_offset(index - 8, PMCR1_COUNT_A32_EL0_8_9)); break; default: BUG(); --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pg1-f176.google.com (mail-pg1-f176.google.com [209.85.215.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE3022F7449; Mon, 8 Sep 2025 10:01:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325673; cv=none; b=BKhm+DUHm6nK/YEDeqqYPajSr7GDYx6Eg7ZAC0k+xbHw/ShCKiy+7Nn/YbaEzgnKUezTWd6VpIAo7HR2iNDLkyyp5RYEPhuk4wmqodhcf6reLG6B6LgCc1TLjoJrgabq0jB5OMjP1mrj0ceFFG4d7jsaNw/rz3Qb2Ulw6H7JGmI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325673; c=relaxed/simple; bh=HTqUsRXqv0uayXlXxBww3HqeknMt/byBk1GhhunGYGY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=S9xBJV9dy8pYhvyKzyethVznnIk4qQl9maKg/frLZVKgYPoJnXIo2ScsD7oIcfiA4FEYwXiTpu/rYzqSEDecA3zsMAz5ge6tJ3If3HDw/0e0i4Lfp1AP12OAYFRQE8rW2mCYnh2GMDLWi4h04dekfPJlu1psgCeRHxUEcQQDg/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=cGyc8cCe; arc=none smtp.client-ip=209.85.215.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cGyc8cCe" Received: by mail-pg1-f176.google.com with SMTP id 41be03b00d2f7-b4c8bee055cso3731299a12.2; Mon, 08 Sep 2025 03:01:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325671; x=1757930471; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=16lNfyPp2lVpupbRAD1MY+eMmDibLLbMsLULc43CNdM=; b=cGyc8cCedUJDYIFMqjO5YC6lVW64cfigPBKdP3AnyDt86qf2yi+/zS8zcILOyTPKeg tRnr6vqZfE9Q6+T6S/+/GeoP2/hgNr9n5I+02bUNQBG7j7/9/YfLsMrtIsAIERoT77WR ejTmgGsiZX1gJ1I7JLxkiHxN/1u9jBzaBHpuQdVbG41C7nYevYtWIA0a+bQTxDhpAcOg b2sXZsV5QGeSRHMu5ShXWYw6Qqc9h0ZyswmRwp1RV/4gHXlo3XOJQQK+Ny2fRFcL4VUQ CNIin+qccTnmtSR8Tw0TvO98eTB33L6z/SFzQw+K2tJHTlWvfpTB2FDa1JDGK79zdNiv nhgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325671; x=1757930471; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=16lNfyPp2lVpupbRAD1MY+eMmDibLLbMsLULc43CNdM=; b=Tb/s+ThtqrWWpXQxBjZ7fkTeNKp4c6J42u6bJX1RoPqMjFnbtzDJbnU9YpZ2x6QN4s di699gpLSDRkklwaulywzkTDRfy6I9OxBTG4bXsfXdwcrzvPmHaB3pZrEgtmAcuQ8Hwa JmyNTuhE6doU7r96WfFuAbAMHO8aQB7SpkYHAm2I7iA883tqZD7sQB5gKAchwCliNZDo 639JUAHYOU3uCE/FhrPY/b3f3+y9sNywcIJSAv3tYWG5+CSFKMQDOHSplgHRQDUx9+sL gwmEe3wizu5SoCvjtwVU8OCiOjGvZvw05QEWSucU7v6RItDsRG3Xi6afu/630py8jNmZ YYRg== X-Forwarded-Encrypted: i=1; AJvYcCUKgQJHsd/rSMcYHOb3OKreYQVFpqUpKI1MRxuIl6T1d1EGQx0S9grqIvzPsV+ovNBdZJBlmWoweP+u@vger.kernel.org, AJvYcCUu9sFCtRTMhlm1GiGSlLAmA4cp2v7miHAWIIxhEpW+alNRAnq0kZ69j6OQxw6U7GJDRUg4HWyqGY67d7Z4@vger.kernel.org, AJvYcCWkf6u+2UxMcpD21fwDMiGhTHe/CQlWN4Nrzr06lOiAQEgd8kRpuO5alj7ZvQWD3Pg592z1u1J3MXjEXSnEFPdQOQ==@vger.kernel.org X-Gm-Message-State: AOJu0YzisfOsblL9OSXm4WWhTFMQ5gS/Xtrkvbt+aJ5jAsMZ3bAzWWQq rt0V7SvL8n4baP9gcIDF0rOdxSkfzvwnw1hndr5tJdtloGigrJ5PxhNk X-Gm-Gg: ASbGnctG6+fLaUTYJ4LLsEU8PXiiNGLyYmDPYJCvSb6JY3EyD2JeP2BDbSZz/VIzvBX qVPvA32VK5suFatQrfpsUdqMeP8YcbyNVn2ubnJcNpJii7Hm0vv7uco7W2a4N0J5Bv9cZRr1PQC 6v1QWASFL6t4u/9IsaunIJXV2Ok+EHoD+mFAc1lD1aCfJR0Yri4fbu5Roz/fgesPb+VDFMcF7Ux Zet93bIQmy8VisTvW2dGnrT6fL1fSPLDwg3GVm30Rlt1NuPyQcTp1pobCCdilwenHOo1ZIuW+B8 mLi4dT8g+gRMcH+3b8zp1TslF/zcfZBVHphusP1JWJZit5UpilIY5h2H0SnrysGW2VFA4nTFxME 2xuYO4DtufnIwoXqd5la2J3/Hmmo2oTI8xAxlHg== X-Google-Smtp-Source: AGHT+IFG8nlBga9cu765ON1HNtnAJSKtln2AiuFotPMwkoUfxyXOesYWBBY5/ceXgicQjppuNNDlcg== X-Received: by 2002:a17:902:d2c4:b0:24c:e6a6:9e59 with SMTP id d9443c01a7336-2516d81a0b3mr106521115ad.6.1757325670620; Mon, 08 Sep 2025 03:01:10 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:10 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:30 +0800 Subject: [PATCH RESEND v8 06/21] drivers/perf: apple_m1: Support per-implementation PMU startup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-6-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2178; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=HTqUsRXqv0uayXlXxBww3HqeknMt/byBk1GhhunGYGY=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlDETZgMV+/MDSD5BsxF9IFaobbIfNhofPoV +IcAuRUXBKJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pQwAKCRABygi3psUI JCbzD/47Ps4GiPxo5vmMsl9FdVJxhCkkddSC8f6nDjwiU6Uoo4+9iniHA/la6Wsqo5kMop7B8m1 jnWyUbA74cLg6IShxozfTVhrHgqLTi4m0lH+wvGX9yywsSyIvM0vqZ+q2D6ZzfkHszNlhqVFS1Y jwTEbBVTJ3Jnp7JbeZCSXxuReIUYn3nF4gRIJ2xUQaMIVtbjjN2boRFbYOsebNR2PClLUlxilXz b5JNoBopmGVTD2W4xUin6DpNPAqMFiFeIuV85zgLDvs34jtlrxjTZPMBxuCWmHrdEQ8mIvuIder iHez3j6nHY2ZMwCh3fHWTDv2Puvwks2onUPRAmfqSs2+Sg5miSj9mko3chyvdvzXRK9X5/r5aXo 5pQ39e8R319HRDja2LibYoiS8OD45CS2GpMMYyqQD/s5sVOg9AKKWNpaMMLk4Cb3qL7eEo/extD TWzyhVZx1+fK8dwQuoGLjor8k2BeMR1fDObLUHw6jroeevMxjKZ5zN/SPCFVQl9XffiHf5jsUBm C13RnAnhSRrJ2siY7CZL16widt7oDmzHquniHTD9jeLFeyrW7B8HhWjMVsnvAAjycR3ORBftw2x oTJoJU4LaYLqYGzhTmeXBFkgpFb1eNyi582FQb/bPNTRGXBxdT9I74q5J1gvBnHbL0xFfzeuycf ErbyjMhO0s5pRzA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Support for implementations that deliver its interrupts in ways other than FIQ will be added, which requires a per-implementation startup function. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index fb2759069fe9e47146f0342fa46e40f3ab836926..303c0e62432281e899a33fc1973= 65c70078d6ac1 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -659,7 +659,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 = counters) cpu_pmu->read_counter =3D m1_pmu_read_counter; cpu_pmu->write_counter =3D m1_pmu_write_counter; cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; - cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 @@ -681,6 +680,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -690,6 +690,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -699,6 +700,7 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -708,6 +710,7 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AFF72FB98D; Mon, 8 Sep 2025 10:01:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325677; cv=none; b=LQW0kMVUVfP0hnrgxJk4uCgPAsz8qHrnKbXmknE/OedYTvFk2uB682r/dJ1v2ljjlHGx8L7a81wdPTaQE6a58i02Pn977h1aRcaG4rd6oA7vduSPZD0T3qqR1pEvTrsEmDje1VmOjIQAMCSvWK+2/G3v990FYncb7P2LtvrBBio= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325677; c=relaxed/simple; bh=HNTQqQJemqX0WI0eYRGH+l+1PjBhJi/4JkQ/C04BuCI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p4IPude9sxwtm2tlW2aQI02JXGtWfz9Gm9ELaCbhVbtJ5kkDPRhaHn4IXKni8BvsJPBCrzWK0nPkJDFHHS3E2YqiqwvfFoatvoodFloFdM3dfJX3ngAZybXsTVE6+pRZKclTjWgJ74DAI2aN1wphF6TT4KEOfd5veo/doQEk3/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=R9mPCh3C; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="R9mPCh3C" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-24456ce0b96so44002785ad.0; Mon, 08 Sep 2025 03:01:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325675; x=1757930475; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gfwDPpCiVyJ0buY5NGtfte2dcu4mrKn89k8yErLBKTw=; b=R9mPCh3CIOMCx80sgY750KZ1VZ/hrsXXZLrXA4eyY16h0UMzPVE7dkmqQvKWYnMWPo 56oxIljtfUdFVOfYIkzJF4liKVbVTk2FdljbBLr404tbbLidrqk2Hvvou5RBJeUTOxOA fwqxjPy0f1c6jlyfj6JBcg33aM0F5XyA9Y2B3J7XBCz7Y4hFbf0obuBdvWf1MlvBN9E9 DYvOE/VrtLE7DW/jxevA9hxAZXQOzdd6oHWjQUvw8MkIgIr+9mvAASDoPGbhtUOPYJy2 FUQRIXXniXrMzdtFNyz9cr5ItuJTnDyGTDTeExofoyToQV4HsmbdjifqWqP2hiCEbYD6 mx/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325675; x=1757930475; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gfwDPpCiVyJ0buY5NGtfte2dcu4mrKn89k8yErLBKTw=; b=PkpueHsYzgGqr6JEGzHa69pr3mVQKsz9ao7XsjTzt/+D6dTPo5M1Tr9llWyNc+d+L2 ywoHBBiqYsDDpzeVFSN3bzaH24HR/vOJ1/567fkWwfbokDzhDjlAUiVxDjF46lWqkGF8 5bB99c4Fxu30imLhP+/FAMcMfCRtEiccCYhgB4ylhclTQDwqnNjcAztvLTUEfXo8TECH tj0oagtB+F5QJnFPYZ5U5f0iL3XnQCtUWCNfEiO+6NIed/clZ33f+rg2e2q/h6i8ecu1 3vV1pk8+59zWeiT+jjXEzDBYj1xq9mvy5DUEDwxcJjf7w7PfevNTdgYJpnBxazNkbMK8 JozQ== X-Forwarded-Encrypted: i=1; AJvYcCUcpGLcj29UQf0kfFWAx4spefxfL0eRn/0tEJCRdmKrmLfyL3wQagFB4rDY6FVvNL3hg2xhmXGVPx2d@vger.kernel.org, AJvYcCVzu4MukOfdtc3D91ztQ30zdNxOs5FiZPB0B1SxZD8fpo7L+FBfKqqlhsZ7PTtZslPfJCm1lI9x2bVrSVFE@vger.kernel.org, AJvYcCXXUCJS7MR5pKM8HzGGGpBL+GDRSpv07fSRJct3uNdLTtbIf4CslNa70wAntfJeT5NwJHBgM6+ScNg1FB9lo278dw==@vger.kernel.org X-Gm-Message-State: AOJu0YzDvRSbf4eV6j/q9sFagPnCa3tsKhECX280j19UQKbz/VZmLOrq H3kZVkK8+rtekEnNDiXGamkuWd4s/K6m+rweUlyeBhmZ6zz/H22QZNdA X-Gm-Gg: ASbGncu8VzwdFJocyzPoYGi2kB85SG8wxd5x1r59kVPun+l+wwjeIYccNryfMasYg5u KCoi1AAH93v8Uz4dirXgce3TNl5cHPhD7SkkDZukXcO3L6a/H5UUXDS0+uNcbfdAu73s4zLxOsq wKEw6e4pzy0Mf7bUR3Z1a80ASZRcNY31DlXfVavQAd3n0lLxYviA3+xW1AuazK9kTKkL4cGQZ1v Weog+2Dcn1mUEi4+mifrzamOszmiwPU8m1xBes5H2496SD9xV9eRtL1xkhQgVGt0fc2RV80wxxZ UuA6EP2SDC/OnIKsh2cHDLUoZPC4hTo6ljdA7XDdX7+y6mojw3A9KhtGUOfabXzMYWkoKQqoJGi GUN1yO1NfvJw7UIgsEpdro0lL+kGoWBzwPTl1Uw== X-Google-Smtp-Source: AGHT+IGLk7qlbfVScOMCIeIb42XcLnwpLlMwiHFaoZOJPZ+XNLGGX7CNUjJexYFNYFgrdXDdh8bXbA== X-Received: by 2002:a17:902:c653:b0:24e:7af7:111b with SMTP id d9443c01a7336-2517427bc46mr80800895ad.6.1757325675347; Mon, 08 Sep 2025 03:01:15 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:14 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:31 +0800 Subject: [PATCH RESEND v8 07/21] drivers/perf: apple_m1: Support per-implementation event attr group Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-7-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2222; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=HNTQqQJemqX0WI0eYRGH+l+1PjBhJi/4JkQ/C04BuCI=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlD34FCamS7+BvFxzQI9pN7EpC0Hbp6D6ALC y9ge2t7aEmJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pQwAKCRABygi3psUI JCtPD/9Ufjt9jmDhmxNUAxoA2V2hfzWrlQmETddcge9lzhC2G+4lt9vtNcKyoJqjbR9EcVuuH+N 0SF1IYHPgbVm6HiVcUf9sAvi7pQpj3D0tXtvx1y3IIUONGg2MrYDjqbvQyRehoWYfc5c0DzNfRX 9T3FDbDuaHmQWVLEz4H++z6nnstjCLImgqVDK4WC+QqD3R9vs4QHpkeYvyYKWG5cGm202IL66+Q 3zfH37A0bK0eRn8dMahrHxWmRImZ8Us1Nm+Q2mVwXDbjHJ8h3PPyuCvggNGXgSk9sz+EuMYRuT+ EAucmWITr9kYf6lKOZLN4aKXS8Gv66Us+OMTMBEkHjP0cm4s25JZtX7k85vC/SQ0+dNP5mJCITY IlA4Dvg1scmk5byxkrCRR1T5BiEdangbWzRvbr/JQpb0bb8fHGxqR+AkeEvf6IELA5cnelHEG9b pFXm5yUYNcvOWCJkls3XGyLILQGnP5s/suOebq6BSXb4G4f1qiU56y8kggJ+zRafdDKIzicZ4pa bYcNDSgadB939lrENMqO0DQ3yJrLCSTFPX/aEtqdqQ7YQ8WNr83VZJlbcxswJiQfIKTLfEJS7Sf T4Kr+YsEgfgZ1sN4PjE+SkVKbuUVPFy1lcD4Rd2t/p85VynzhTwijW/Pir/6Z/qyFdOZVcVPBg2 UJkGyS4ezYQjliw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 To support implementations with different event numbers for cycles or instruction events, event attr groups needs to be per-implementation. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 303c0e62432281e899a33fc197365c70078d6ac1..d0362a1813788776f4210523efe= 33a3018cfef2a 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -668,7 +668,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 = counters) } =20 bitmap_set(cpu_pmu->cntr_mask, 0, counters); - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =3D &m1_pmu_format_attr_g= roup; return 0; } @@ -681,6 +680,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -691,6 +691,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -701,6 +702,7 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -711,6 +713,7 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 502C72FCC19; Mon, 8 Sep 2025 10:01:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325683; cv=none; b=uqItgExj0AFEQum6+ls1BVDYikOpptoRKeNaIjNIEo0sCIB5zjnHFw+ziyz7C0Vn+WrghK+rfdAVQvlOh1YzZMJH9fVE6mYCB2atupcefZauDAYFOujz4FamubQRGR6Nh4+N7QroHwqUdSjkFeIi0/IHz52vkY0rCg3+iapNuFA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325683; c=relaxed/simple; bh=qBtg7GvHWTTjyZPMcecSa1H/np7c9hEJRJGdlfAVn88=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Bdn5cFw+ZuxH2DqpXLMiMsJK9ycWv7ZwZL0Wk8NgrsGal6gILE0f7z5Iae9O9IvikOw8/c3jRbCrwTI2CJaQimALcr49i23wst1+jZdRZygZh1fhgXF5SKdrS9xgUznwH6bN27relAhpuOh8M8dC6Zey5Ps9bk2aHHwGwSFJdYM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=h5UmRRmb; arc=none smtp.client-ip=209.85.215.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="h5UmRRmb" Received: by mail-pg1-f182.google.com with SMTP id 41be03b00d2f7-b4d4881897cso2865671a12.0; Mon, 08 Sep 2025 03:01:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325680; x=1757930480; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=M7yamUBkHwJEe6SZQP6ugity7ctW5TH+GzI9VTk5Vx4=; b=h5UmRRmbQ7GYQh77NavD78VQX7k+aUwwW3Lb5KzHsgXvY5a52CeGAppxjH0jcuwWXf Nzd/I4Hy5vNUw1p/Ztw9ZIXyrkTCRhAE9BNwzcfUARtuKHl7koF6GB3c39h9Y3JeMCVD I5TcsE0NevFCQJSKi6kEyTY+cYTyatZCQFT39xJ/uXxqkE2fIazPN24lkiNMYaSrLfkK pQBvHVTJpJWcG0n3p1pBTdmu/pWK5o+RJ1+jIpW0rm3JlN4H/AcJsro5Ru8GU0B1RTLT x1CgKDm4G8sVXE/dlN/B9UJz+Ja8+y7c71LouuYZnl3iMiTFf/A6RnuObUp0SLI4QXhK 9RiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325680; x=1757930480; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M7yamUBkHwJEe6SZQP6ugity7ctW5TH+GzI9VTk5Vx4=; b=N/o6Fh75dLOxyBj3VoqcuFAkElFb2tPE5Fd+JPecfP6sfeY5nlfJsGWmsxLWKh75Kn huemkPLDXbLUvv1l7FxgbrlKJPt8GhyQ8bySEt/qtC8OArhK3GWJxatePh/JnLKmSE9B OAjCZDr/6vIL3efSRSjKHUprAJPH+PgyUjfHtA8rZd8VZj7pANpsFU5ygxcUvdhAAWcv /YPdKXCCqODBN7TgxUGC6+MU3lSsQpdyKfBxT9u0/1qgbvX/infzCPeQQ0WlsH8ljOh1 9/KaMvTt5eWnHjdDxUS+53KuP8ZfLKlBPa2ALrxPmqzQUBLbowu86YGQ36s8S4G+BPhM oQYw== X-Forwarded-Encrypted: i=1; AJvYcCWikmg4p3LYOJ87KMEDQjvk+qcSJYx+yA5OhsQd06Ja1ImryLxdX3sPZYW99zz9wNDgduEonI2nhqQeyH1YDsZgGA==@vger.kernel.org, AJvYcCXWQhyJFEIW1M10kYQ2qvRPYmq7/pzyCHBg0FowgHyLCxwWGAN225BFDFniA5ijxhs6Ogx1KN4yNDPBsxZ0@vger.kernel.org, AJvYcCXyALb4bJVo76zWepSiaKs1a7cyB019NSeKb7rbbQnDNDzuW8iPOGv9qXy2wReGMCJrGezXHkRQ3iWf@vger.kernel.org X-Gm-Message-State: AOJu0YwqSWo9O+rHrihYGvBpgLuKeI4gxvrY+bv/+ky60bqWBySGFgxD QO2Iva7ZXmIX/HV3xW8rWPktlml/0KaIdJvWb9TEd4xtkIZexQg66SV8 X-Gm-Gg: ASbGncv9U+bngwfwmVFqUhZNdUOQb0dAmBLfKXTAWKdD7Dt0oES1VlaPpV8bl6J/3p7 AWNCFDJajmDg6HFMAUfbn4qNZ6XqrkLM3vYgk7zOPJ2CIw9hmx6O9TmD01iad5XzhabiXb6+x1Q eLlzd5VrCXRN1z672+iHVCZg2K2VUmXPTY8/QHpM3Ed6c/KNmnul1xHc9sVtiBBkyxTlux1BahW tzk5ufNDvNO7et1lFDug0bCuToSVGYC5+697uawZbvwZc6u77T5qB9pOkzyJ53U3UW3UdZZaUVt CvrudNl6xj0XBqJMqFHRIP2xlw6yyXT34UYexfbgw478b+13HvjIr8m0oEv40PS7w/vz7Y3W0Vl mqYr2Q2EG+YZ2seLkESUjTvEmYxKHEYBCEyvr0w== X-Google-Smtp-Source: AGHT+IGPXLuiMA+sbG/cWtPEyT2K8NORxzTjZDrtK9tYtfAcGxwLdVqXGZAvayK62PE5HXIaBEEnCw== X-Received: by 2002:a17:903:3d10:b0:258:2476:77c4 with SMTP id d9443c01a7336-2582476792emr9080065ad.49.1757325680464; Mon, 08 Sep 2025 03:01:20 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:19 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:32 +0800 Subject: [PATCH RESEND v8 08/21] drivers/perf: apple_m1: Add Apple A7 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-8-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11055; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=qBtg7GvHWTTjyZPMcecSa1H/np7c9hEJRJGdlfAVn88=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlD36g3iQqgbPFoUIQ3QGnzNPOStixQafL8k 8FaIMKEnb6JAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pQwAKCRABygi3psUI JEczEACHumVIHSMeJZjjzaYMjrrnWHx4aPj8N6/rIrhTH9YHcCNtrySkt61gVzeuITcmJCrIt7n +77MIqnlsgQmJVkUadQVdy4+MGq4jRjzeXm6Bj+G5Y38rGyQ0xZS7TOKKfSPYbJ/tMhYT+u6h0C esVyw1dQgP0ONEfO2bjHaSr7Qp3nIxhRix+Pj0eraPsQOdC7ophrQxTuDn8FK1EAgZi+9hDme5y ONzdhLEWcdKak7Ej+ayrxIjFP0djA+ilVTZ7UTm2tlDW8IiHSLedl2SS82/z9SpxU3qjUY/uzNx JmW2wG5CSFx8+9I2C2In1z/lryPCTRhJUhlmfYXDKLKWb11o+MLpD68qjGqsYrhb52RVeaVrL1Y g6cxB9M6o4cmMdG0yWpREq5t2uPTLX5Aqt0APBfi3tgDZuYY1ovh1ksF9Cg4u9ZmOuWgetmSVN9 K1JBcfDujsdX1fJu4yOAey0dYeyYExPHb/Q9/TUjMmC4DMNGWYawaiqsfxe5p2g1TLihrZYCR46 iPKCWfcGoGnpu1YAxCnyyO/db3onVRezlQwSnAu0FA2caaqNhHcaFbbyBf30UhZmXDptuGr3KoG dzD/9kO4m4LJ6eo6ByRkx/A/GNZ1yYgzbCt1bZnbnUanKwgZHFSrflHGoRWuVVD86GF02yJiwIJ DXDKGTZmMuN060A== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found in the Apple A7 SoC. The PMU has 8 counters and a very different event layout compared to the M1 PMU. Interrupts are delivered as IRQs instead of FIQs like on the M1. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 190 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 190 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index d0362a1813788776f4210523efe33a3018cfef2a..afcf7c951379698ceff21c1a99c= ca31b3a6177b1 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -19,6 +19,7 @@ #include #include =20 +#define A7_PMU_NR_COUNTERS 8 #define M1_PMU_NR_COUNTERS 10 #define APPLE_PMU_MAX_NR_COUNTERS 10 =20 @@ -45,6 +46,143 @@ * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. */ + +enum a7_pmu_events { + A7_PMU_PERFCTR_INST_ALL =3D 0x0, + A7_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A7_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0x10, + A7_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0x11, + A7_PMU_PERFCTR_BIU_UPSTREAM_CYCLE =3D 0x19, + A7_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE =3D 0x20, + A7_PMU_PERFCTR_L2C_AGENT_LD =3D 0x22, + A7_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x23, + A7_PMU_PERFCTR_L2C_AGENT_ST =3D 0x24, + A7_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x25, + A7_PMU_PERFCTR_SCHEDULE_UOP =3D 0x58, + A7_PMU_PERFCTR_MAP_REWIND =3D 0x61, + A7_PMU_PERFCTR_MAP_STALL =3D 0x62, + A7_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x6e, + A7_PMU_PERFCTR_INST_A32 =3D 0x78, + A7_PMU_PERFCTR_INST_T32 =3D 0x79, + A7_PMU_PERFCTR_INST_A64 =3D 0x7a, + A7_PMU_PERFCTR_INST_BRANCH =3D 0x7b, + A7_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x7c, + A7_PMU_PERFCTR_INST_BRANCH_RET =3D 0x7d, + A7_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x7e, + A7_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x81, + A7_PMU_PERFCTR_INST_BRANCH_COND =3D 0x82, + A7_PMU_PERFCTR_INST_INT_LD =3D 0x83, + A7_PMU_PERFCTR_INST_INT_ST =3D 0x84, + A7_PMU_PERFCTR_INST_INT_ALU =3D 0x85, + A7_PMU_PERFCTR_INST_SIMD_LD =3D 0x86, + A7_PMU_PERFCTR_INST_SIMD_ST =3D 0x87, + A7_PMU_PERFCTR_INST_SIMD_ALU =3D 0x88, + A7_PMU_PERFCTR_INST_LDST =3D 0x89, + A7_PMU_PERFCTR_UNKNOWN_8d =3D 0x8d, + A7_PMU_PERFCTR_UNKNOWN_8e =3D 0x8e, + A7_PMU_PERFCTR_UNKNOWN_8f =3D 0x8f, + A7_PMU_PERFCTR_UNKNOWN_90 =3D 0x90, + A7_PMU_PERFCTR_UNKNOWN_93 =3D 0x93, + A7_PMU_PERFCTR_UNKNOWN_94 =3D 0x94, + A7_PMU_PERFCTR_UNKNOWN_95 =3D 0x95, + A7_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0x96, + A7_PMU_PERFCTR_L1D_TLB_MISS =3D 0x97, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0x98, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0x99, + A7_PMU_PERFCTR_UNKNOWN_9b =3D 0x9b, + A7_PMU_PERFCTR_LD_UNIT_UOP =3D 0x9c, + A7_PMU_PERFCTR_ST_UNIT_UOP =3D 0x9d, + A7_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0x9e, + A7_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A7_PMU_PERFCTR_LDST_X64_UOP =3D 0xa7, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xb4, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xb5, + A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xb6, + A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xb9, + A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xba, + A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xbb, + A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xbd, + A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xbf, + A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xc0, + A7_PMU_PERFCTR_UNKNOWN_c1 =3D 0xc1, + A7_PMU_PERFCTR_UNKNOWN_c4 =3D 0xc4, + A7_PMU_PERFCTR_UNKNOWN_c5 =3D 0xc5, + A7_PMU_PERFCTR_UNKNOWN_c6 =3D 0xc6, + A7_PMU_PERFCTR_UNKNOWN_c8 =3D 0xc8, + A7_PMU_PERFCTR_UNKNOWN_ca =3D 0xca, + A7_PMU_PERFCTR_UNKNOWN_cb =3D 0xcb, + A7_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xce, + A7_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xcf, + A7_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A7_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A7_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A7_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A7_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A7_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A7_PMU_CFG_COUNT_USER =3D BIT(8), + A7_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A7_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A7_PMU_PERFCTR_INST_ALL] =3D ANY_BUT_0_1 | BIT(1), + [A7_PMU_PERFCTR_UNKNOWN_1] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A7_PMU_PERFCTR_INST_A32] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_T32] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_A64] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ALU] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ALU] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8d] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8e] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8f] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_90] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_93] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_94] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_95] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9b] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_LD_UNIT_UOP] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9f] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c1] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c4] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c5] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c6] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c8] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_ca] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_cb] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -165,6 +303,14 @@ static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_= LAST + 1] =3D { [M1_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +static const unsigned int a7_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] =3D A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE, + [PERF_COUNT_HW_INSTRUCTIONS] =3D A7_PMU_PERFCTR_INST_ALL, + [PERF_COUNT_HW_BRANCH_MISSES] =3D A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =3D A7_PMU_PERFCTR_INST_BRANCH +}; + static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { PERF_MAP_ALL_UNSUPPORTED, [PERF_COUNT_HW_CPU_CYCLES] =3D M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE, @@ -199,6 +345,17 @@ static ssize_t m1_pmu_events_sysfs_show(struct device = *dev, #define M1_PMU_EVENT_ATTR(name, config) \ PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config) =20 +static struct attribute *a7_pmu_event_attrs[] =3D { + M1_PMU_EVENT_ATTR(cycles, A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE), + M1_PMU_EVENT_ATTR(instructions, A7_PMU_PERFCTR_INST_ALL), + NULL, +}; + +static const struct attribute_group a7_pmu_events_attr_group =3D { + .name =3D "events", + .attrs =3D a7_pmu_event_attrs, +}; + static struct attribute *m1_pmu_event_attrs[] =3D { M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE), M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INST_ALL), @@ -521,6 +678,12 @@ static int apple_pmu_get_event_idx(struct pmu_hw_event= s *cpuc, return -EAGAIN; } =20 +static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -544,6 +707,11 @@ static void __m1_pmu_set_mode(u8 mode) isb(); } =20 +static void a7_pmu_start(struct arm_pmu *cpu_pmu) +{ + __m1_pmu_set_mode(PMCR0_IMODE_AIC); +} + static void m1_pmu_start(struct arm_pmu *cpu_pmu) { __m1_pmu_set_mode(PMCR0_IMODE_FIQ); @@ -578,6 +746,11 @@ static int apple_pmu_map_event_63(struct perf_event *e= vent, return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } =20 +static int a7_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &a7_pmu_perf_map); +} + static int m1_pmu_map_event(struct perf_event *event) { return apple_pmu_map_event_47(event, &m1_pmu_perf_map); @@ -623,6 +796,11 @@ static void apple_pmu_reset(void *info, u32 counters) isb(); } =20 +static void a7_pmu_reset(void *info) +{ + apple_pmu_reset(info, A7_PMU_NR_COUNTERS); +} + static void m1_pmu_reset(void *info) { apple_pmu_reset(info, M1_PMU_NR_COUNTERS); @@ -673,6 +851,17 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32= counters) } =20 /* Device driver gunk */ +static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_cyclone_pmu"; + cpu_pmu->get_event_idx =3D a7_pmu_get_event_idx; + cpu_pmu->map_event =3D a7_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &a7_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -722,6 +911,7 @@ static const struct of_device_id m1_pmu_of_device_ids[]= =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, { }, }; MODULE_DEVICE_TABLE(of, m1_pmu_of_device_ids); --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D50C2F83AE; Mon, 8 Sep 2025 10:01:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325688; cv=none; b=UnRBxgRf8NPkHDjdhBdgylsc4OtASq5QDuqoBo71RPbPXSX1drHIYdqMDp4avwPU3H9G67EY2Hm+XOc7ztRdB8impexUiZAcnXWnD8e+uepEGZ17KdpRN7G678n3YSAkfZG4ZAPML91DoJl9mlF9M5v3X/VnFrc/g2LjeE4/OVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325688; c=relaxed/simple; bh=0Gjw2DLDf2HcgWJCa0UKXhEAmzcC7ohJTyexzyC2M4w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ilrsbo5aFbznlEVRNb6dwAlO4hIc071CBRIurMHC7I/D62e2jRme6/odE9XvEg9OxmFYHSNTzuPtveXcjiLLDcJbxoPK1vKnvTtKZWSSQnOasqpPLuJPk37iUaxSseQedWzPHq0z1uOkOH52cSLttBLVuv/l4SxzLB00+yXrmu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=iP6kzmUq; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iP6kzmUq" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-24af8cd99ddso53164775ad.0; Mon, 08 Sep 2025 03:01:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325686; x=1757930486; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8gRaoB9vYf5O7cEPCC+wUggQERU2xhO24hdBoAxLCGI=; b=iP6kzmUqD3ecn2QV9JuAxPR1JExE6tuCpmdXMU5OJvZVGCZ1MKUGzWSIbsu6zcBNU7 4EmAM9s8emEnMsZ0qG9zwob1HX6DVaiuJCWkrfOgUyDRb+n4YqYtyHCElb1yP/A0VA1Q h86d5wrHgToLScch1TqgHY1Ruo7N1EKm7u8Q7XRZxiK0BWHMpCVvPdxokOE8Tw6x8Hed EMlkqJ93xagPVLIC2KTvQY/OgPCAMYq2TmFfA+n2hMjgfy/nMOsTqYq+d1d4NB8aYFyn P/Od5P8LgclEbYXvzFGSsuGcHVUZAdB9IC21I2v6fcxKSf5SU1mNLLFt364sFKOTaKoE fh/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325686; x=1757930486; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8gRaoB9vYf5O7cEPCC+wUggQERU2xhO24hdBoAxLCGI=; b=MjLSEM8GtY/dIw3Q+Htj/NkmsKYBIC9aetuJlufDYHh4tgFp4NnJeNdAUpbElrry8P V1b+l2bHA9btoshVmq5TY+jHNGezgMJ+NASjwmH6ezhWoRnTAAoUwwoVA3G/E0QuEhKL ybLWuHTHOahxd6jHBdE+dge32sh9gx6oKrl+YmEWKEXl256Vp1B1AJzb2QwAXGawMYFE X0FcucVv4Fh5u+1FQgP3oEfCfVChTQGJNNqGJm/9qobMmpKbX6TVjYv4cW8Ox7wmLT6f OEbmvGQ1rQgjGCgX7++KcBOF090QwfzjeNlv0jRKMfm4E41rlHcqtWVF3rpFxv26XfNe c+og== X-Forwarded-Encrypted: i=1; AJvYcCWYYWf5emark0ljyv1GaWLkgI9Egj1lKTvLmspv4Aw4Mt1zb49blvNuMcwaCTNfKawpkyTwcHd5pVNWtMo9@vger.kernel.org, AJvYcCWeZ4QiG9iUSsJrvU4snpTGgBPhtAYIhed2MfcvBbjuSaR202wNgJOsw+81XHJE1G2iMtmNkG8J/j0LPF5GlqZ3gg==@vger.kernel.org, AJvYcCWksTk29uZqYoU5aslMdlUuJZDq0h086ssOv3ZXGCO+wR785QRdQQstUn1htfuH0svEV79XmUQx4IuN@vger.kernel.org X-Gm-Message-State: AOJu0YwMpPrBw4XU8+8mXjCnfzA91HkW/YT2F3TlgwfiztFiI66IdbML LvZk/kx4llK2nZ/c8Qe+qY3qkhUbUFb5wJaagYpKDLZm463eTwa2xqpz X-Gm-Gg: ASbGncsfrT7Te+KQMM2909bxn8tvtmg+IzpOeI76yd2FfLY1w1xNV/c4nvZa983rGqD zgNg61o9fgRlrtYAxAqxn4NjpZGCCusoJPv/AWq6ZrYp6+cAD7CB0AG9ZieakJL3W3QUnNaYLjs Zk+yPltL8tLSsRv+7GGdOSxmjWNnJdbq1W4j5IfeX8Fkz3kKtPNYoyzee52dbMiHuOvCwlDwOWj IwZcWKK1mnpEGb9lgEDKFj0H+q+lWgvcK2EdMwjBXVI8mQo8F7TVsPO2YuymEJZJRtEV4r2lKdA IcTw0w6jxYDMPfAcrdPkNGV0IgzhRS786kIu1DlpcpNNaJQDitijsAdWBUrgtXurg66tD2LOOQ/ 4Tb3SAUfAp8QJoBDUkOrM4LemVcTSaSUcZxvlMw== X-Google-Smtp-Source: AGHT+IGwTu7AeEp37OBrOVDCqpWlcPIAs+R/Bgj3SZDrqLRjAuTttf9OcwdxpaatJ5YCvORcuCJoJw== X-Received: by 2002:a17:903:f83:b0:246:4077:455b with SMTP id d9443c01a7336-25171cbfb5cmr108591465ad.36.1757325685527; Mon, 08 Sep 2025 03:01:25 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:24 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:33 +0800 Subject: [PATCH RESEND v8 09/21] drivers/perf: apple_m1: Add Apple A8/A8X support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-9-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Ivaylo Ivanov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7370; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=0Gjw2DLDf2HcgWJCa0UKXhEAmzcC7ohJTyexzyC2M4w=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlDy566EqPmVFurDG8GuQSptLajwhF9Asocb svJht31dRSJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pQwAKCRABygi3psUI JAdPD/oCjTIsqsMPOd1egGiYKlOn+/mW/4vM0ECWJ+PM3nQmYbObB9Aids1NIOyFLlvl4FhIvkd Fm4i8y5HBO8gYPddtH4afs1rA51X9A9XnJJB8D627+LMkPRLEx0dDPDevKGnmYVvu4Y+K/zuPYH YwLi5+5J09xQjvk/7WWwx/lQ3L9xXfZG6bVZVz3lu54PNqL8A+o6qKZKri0eiEdY3PPm0oJ7Uqq Ew9PYRwyB51ssHRi1WWUw8x3wicxXo/lZcXZTjd2KIk3zyZI6IicnJfcXBBu3qoZ6eP4VAZqKe8 S2QGow0t7ooECMDPVEztmjCoWbox7DTX1XaTGI/QlTz7OgudsACg3YeLMQEEVQD0qiycbJh81DZ fKwD/3RRfvdv2cBr640nU80Z2aqZMQQeqoi47O0HcVbz4n98OqtD1DA57tPQO5lsNJ/p36CUzYs jY9YmLU5a1WFuCtjGvF/EjXDvHD4f7SKNcVANEgTFUWyiFT3pEQ4efo6+HDfJU13/EJNbOsDEaP ao1Tg2XFxHpPnvaAhhpr3NyXrmpj4ilhIHvJdEWBvK8McUNKY05jkgg8Vv5jSvVoF6rR7InFVRu eYZJJxW8keLJTlfvB0kWx+b27qSt/Y0neRq/0T0IbJkX3J57aF6BrU0QlzPNhpK7sEJXbZBUhYA H7ZXX/dOh3QpUiA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found on the Apple A8, A8X SoCs. Tested-by: Ivaylo Ivanov Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 124 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 124 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index afcf7c951379698ceff21c1a99cca31b3a6177b1..a95f4b717857b30284470487827= 954dd4b139010 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -28,6 +28,7 @@ #define ANY_BUT_0_1 GENMASK(9, 2) #define ONLY_2_TO_7 GENMASK(7, 2) #define ONLY_2_4_6 (BIT(2) | BIT(4) | BIT(6)) +#define ONLY_3_5_7 (BIT(3) | BIT(5) | BIT(7)) #define ONLY_5_6_7 (BIT(5) | BIT(6) | BIT(7)) =20 /* @@ -183,6 +184,111 @@ static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR= _LAST + 1] =3D { [A7_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +enum a8_pmu_events { + A8_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A8_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A8_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A8_PMU_PERFCTR_BIU_UPSTREAM_CYCLE =3D 0x13, + A8_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE =3D 0x14, + A8_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A8_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A8_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A8_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A8_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A8_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A8_PMU_PERFCTR_MAP_STALL =3D 0x76, + A8_PMU_PERFCTR_MAP_INT_UOP =3D 0x7b, + A8_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7c, + A8_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7d, + A8_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A8_PMU_PERFCTR_INST_A32 =3D 0x8a, + A8_PMU_PERFCTR_INST_T32 =3D 0x8b, + A8_PMU_PERFCTR_INST_ALL =3D 0x8c, + A8_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A8_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A8_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A8_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A8_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A8_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A8_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A8_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A8_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A8_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A8_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A8_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A8_PMU_PERFCTR_INST_LDST =3D 0x9b, + A8_PMU_PERFCTR_UNKNOWN_9c =3D 0x9c, + A8_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A8_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A8_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A8_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A8_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A8_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A8_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A8_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A8_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A8_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A8_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A8_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A8_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A8_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A8_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A8_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A8_PMU_CFG_COUNT_USER =3D BIT(8), + A8_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A8_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A8_PMU_PERFCTR_UNKNOWN_1] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A8_PMU_PERFCTR_INST_A32] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_T32] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A8_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_ALU] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_ALU] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_9c] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_9f] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_f5] =3D ANY_BUT_0_1, + [A8_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_3_5_7, + [A8_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -684,6 +790,12 @@ static int a7_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); } =20 +static int a8_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -862,6 +974,17 @@ static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_typhoon_pmu"; + cpu_pmu->get_event_idx =3D a8_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -911,6 +1034,7 @@ static const struct of_device_id m1_pmu_of_device_ids[= ] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, { }, }; --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 073FD2FDC57; Mon, 8 Sep 2025 10:01:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325692; cv=none; b=T7p4+/b6pKzsnno/9AAcmETmlf5SPvY6Da8OOnGYAgCXZDB6mDtfmerNFeb3CfGgoY0USLX61hmPCIVRi5L5AOuOmB3nQViS8UhoMwqhz8n2VGbkuGKzLp+4NPtfwMdhiyI+BkbyZPAjF9wP86BTn5bGsxdntvbFs4FghP7AaZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325692; c=relaxed/simple; bh=LUTF42ROOv9lWR+4KsOLqtJZDON2mQ0ehFAdOL90kEI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=n9sbpdhqgYdrCMWSOlUnvprvcQurfHdzaqR4KxqI3qH9I7YjgPkDKevn02GDw0V9vAzxbuR2A3Z8zaX7d/RUc10XIWibgmf/iJXSj+6vtw9582eRZnf+jVf409C2fkwQMewIEYhKk+tuYnx0PRRfWdo6KJDfDZhlnRKLSjMG4Ds= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bf+Zovhc; arc=none smtp.client-ip=209.85.215.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bf+Zovhc" Received: by mail-pg1-f177.google.com with SMTP id 41be03b00d2f7-b522fbe3088so569187a12.1; Mon, 08 Sep 2025 03:01:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325690; x=1757930490; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kW/u6QKovqkYoXjfaaQ4q+qjIiyLs7/vzeRi0yEodtg=; b=bf+Zovhcyrqflf9YsZJ/SKZ/A1iQEQHDTatCPtvu7ckcVuOUTvXHDdUCV7Cd0sRihr rj4pJGlHz0xrYbKx887CgURoex27VlcRSnN7vvqLSnbNgVvgBTvBIF2qYQxjwr0Qa3t+ PUaR/V9GGab1/EGwqCc/VdCiDl1lmpI4xOUsWi4ryARdttKFHosMy7xF3limmd2gjDrZ Hxon4Y8y69jz8VaPNiGs7AR17OATCS690YNs4Ke0qQhSPP5rZdijN9m1cWaHEJcxoGJu GZCcnT610jDPnMbRZ15meF2dmPMG/GJIhH2y9H5YOIeToBOXbMU/EEuVlqd5yWayuKEA gUyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325690; x=1757930490; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kW/u6QKovqkYoXjfaaQ4q+qjIiyLs7/vzeRi0yEodtg=; b=aBPZuJNYJI9n/xR9ZISOo171dXQx6cSwIQs58ukpPBMdjEg7RCtSzcm7uEjtsl+iA3 C2vK41LP0/W6hwnLfB1pExSydVvFuggeBYoECfqWeggNYzMy+5J5l421c5Mu8Vn0KNok ZpE/sZR2X8npNj3yWOEjNbs/c7+nsO0lIOaO+4IVoZBLihIRttmaiSSh4VkWchlj8ow9 9DALdS7OtvaG9K5vkoNQganVftE+NOKDFzGFNbTZTY5VXiMIExvTI2ERm0cXxcnWGRKb xXPIQcCcbFS3JHHr6How5fuaGi2wwSzySWmMcffx4VvMbg2kKqscAdTh33jahRK0hidu gBmg== X-Forwarded-Encrypted: i=1; AJvYcCVAesYERnDcs/BlbOrlQduRmpepZQ8qQfkVhySwrZcTdtuxfrN4XTiTWSBNeOWstcZQ2IoAweyfZTrk0Zv4@vger.kernel.org, AJvYcCWqTfTattvTPG9ihzMfvzC5N+vvxlhLdPtZOmxwbRjNWkcKidBgL66V008Jr9i88K2DA0cftYUjqwr0@vger.kernel.org, AJvYcCXFKn4mkvbqwt/UnuBiDGuYPy89mK0ujNSPmS0pZNFtFVrePjPtNTWzwiGVM7PYao97HMnS4a2vpgK2UTzso8+c4w==@vger.kernel.org X-Gm-Message-State: AOJu0YwarC4FmyA0AQygJTNVA0eIZo7PPfHKrZeiyXeAg1w+dBfyq68H o5OqQ/7w1+7vYmClPyjoanHJGTz1z2ZXBe7xjgbS2xxpKjwYIvNul571 X-Gm-Gg: ASbGncta/OJ/Kd1hQElF4DHjVUAjl0EN4h9zI56u2sOGbEMLPmiPsRaUj5dN4iHRx8z 1J7EjIIz1NpyhHubOJbvqIdI6p1ikgsrXiDPfokDSkb0i5XwNeN30A+H8+atGsMdrom+TIYt+E0 iGLp7YQ/3Im+QnUt0fgP66r+N8GIz1BO3Ps5XYOMkK0PkpuUuLUyHt6pfhJC5wLnMMPMP2U1gfn 3t6eZhlBYAMGtYkzho+xLdRxx37/5UamAuENu9cVvBEsopDLrGBe8B/yarwHlF2R8bPCOTTatot /GmhdJVPaFmc8Gf2nAcP5V2b0BS0SBps1jsy7fTh79GvZu2zK/Mha99NpTQ829ZizCOIMFlUgJv MTuCmCb9U/jqrKMqIb6pqGkqfRucwvECv0rVARw== X-Google-Smtp-Source: AGHT+IGqFyg8M779JN7vZpNoonq5SLITan8X42VEYbjbAKkGB18BSM3pzr4jwL1baVOwYl2lLRo8IQ== X-Received: by 2002:a17:902:c653:b0:24e:7af7:111b with SMTP id d9443c01a7336-2517427bc46mr80811805ad.6.1757325690097; Mon, 08 Sep 2025 03:01:30 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:29 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:34 +0800 Subject: [PATCH RESEND v8 10/21] drivers/perf: apple_m1: Add A9/A9X support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-10-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6996; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=LUTF42ROOv9lWR+4KsOLqtJZDON2mQ0ehFAdOL90kEI=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlD6gV4uasUu9A7D576CKcpDSoH8vJIWnHJl DgMA/Ff+xCJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pQwAKCRABygi3psUI JPagD/9uOdIfUGCw1TD6HbWDjCa/xmGgSz9LSI8K7Gm2yptbO58E9nN4jlUkHxC41mEc+ZiXtY6 B7L2fBgVIgHHAaNJfgwOEdVr9XMRrqsYpgXWiPluK6+M6pEEljJ8rDU0P5DsWurK7KdDkFwjX2s n3Za9lvSY9vZ/Ejo5UQTsxQ7uIs9TjUR2MGNjgCC7s6PnlYIL3AQqUGv+nYNCSuNs6RTNFdULl9 BI94caGefvzxQZgz4EWXEh3Nms3raJmGLgQlV9Ny0PWavDrlV/+gOE1aNid/2lIMbJXBWUTQOdD sVJfmfAk42YWlRgjPHNEaJFMKicDbI5UPD8jHml+PWNqyL4ifj2w74DGZ3hRWMnXs26M7+p0I1v W786BptuYiEKUaP4be+CcJAYoebSQDhNELbsnPJ+PVTkrm13QCy2+IY0D+M4aqZx5MM5aDDJwkg xc2q1zrF230LCet1XD0NRH8Oexop0JNz7BOBOl6xhqeIXL31QpOzVpQt40m0HHlFUwagEw3Qngr kenBt6D/7FYU5UN/7zyNUc8BcJyxXbA5DSaz0sx8zer97rmb6t8IXPsM3Gb+THDsszGhlbc069S JDm+VYXBcTOExHw/DBMApRYuLyswCEnRgQJ7CvRfa4OAVkwmjfxhA5u4Zn9RkcSNnKHvSIJPcMm EsPGOppqoHsGOEQ== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for CPU PMU found in the Apple A9 and A9X SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 121 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 121 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index a95f4b717857b30284470487827954dd4b139010..bfaf926fd47b02a7d77ac31cbb9= 7779b5ebedec4 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -289,6 +289,109 @@ static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR= _LAST + 1] =3D { [A8_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, }; =20 + +enum a9_pmu_events { + A9_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A9_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A9_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A9_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A9_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A9_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A9_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A9_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A9_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A9_PMU_PERFCTR_MAP_STALL =3D 0x76, + A9_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A9_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A9_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A9_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A9_PMU_PERFCTR_INST_ALL =3D 0x8c, + A9_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A9_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A9_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A9_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A9_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A9_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A9_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A9_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A9_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A9_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A9_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A9_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A9_PMU_PERFCTR_INST_LDST =3D 0x9b, + A9_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A9_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A9_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A9_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A9_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A9_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A9_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A9_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A9_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A9_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A9_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A9_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A9_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A9_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A9_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A9_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A9_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A9_PMU_CFG_COUNT_USER =3D BIT(8), + A9_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A9_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A9_PMU_PERFCTR_UNKNOWN_1] =3D BIT(7), + [A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A9_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A9_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A9_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A9_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_3_5_7, + [A9_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -796,6 +899,12 @@ static int a8_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity); } =20 +static int a9_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -985,6 +1094,17 @@ static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pm= u) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a9_pmu_twister_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_twister_pmu"; + cpu_pmu->get_event_idx =3D a9_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1034,6 +1154,7 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, { }, --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED21D2FE588; Mon, 8 Sep 2025 10:01:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325697; cv=none; b=s7r2g7TQFk2NsVu+yLwgEio4BAPovxv+O+7SMR71sdslvVsLkrzR8xMMlkBWK42st9AOvP5zeLr5VIcHmnK5lGRCBrBOPKTwhhB9SqEXgDVb/Pk1U21IRhArrUe2JFxO9kDC2zFycfOPrrXyH5pWgacNy8aIj7j2zk61AUkwjLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325697; c=relaxed/simple; bh=wFKk1NRP+ZMWRbYofs8l7oAm27DHSag/Moujm6quV7I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UCWbDyym/I21AgcXZYHrcUxY24xidbpnJabnc/fl54WYyj4E+ncXm+5pc5pfU2csuFnWdNY/so4XA/YP0SxzEImjbSefcmXuwH9kO1SwFBCCxxWOBF15YPVTaqa4PaBM8n/QFL8kUf9V23baumXuSIDYVXggojCSuAsNIkYSC5g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UDzZFtlL; arc=none smtp.client-ip=209.85.210.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UDzZFtlL" Received: by mail-pf1-f171.google.com with SMTP id d2e1a72fcca58-772679eb358so3786190b3a.1; Mon, 08 Sep 2025 03:01:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325695; x=1757930495; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RWNYzRq/Vb7U7TDz4etpmaiwu2aIj7aVaqiDoz+nPgw=; b=UDzZFtlLfSq4ozRcgkiQKu4V3h6k8YKUJCIiEELcHHzeEr4Y3w4d6YfPzreFcPmXre aZ+E7mjLeZMmARD5ZndUCbuqDAjH7kI4Gor3f+MtLzDMZhbZuNvUPj5HregrEK6aCcfQ B+peoVX+Dko2WnEv9sLN5tLMWWF+SwV+T3XYdG/opIZww3BNSBvONxv3/pCdqWU1Rkin odgDyX0+c9sATBPyPm3lxQxcT/LCDfOWfSrl7KRyqwslhxTf8/vvR+CO128gKslQ7SNt iIwqDE/oAc4WM8/Wav8lgm+aZyDXuQ+p0zub1UMELuJf5DM/iVnWatGtzztnVIwejmK5 IMHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325695; x=1757930495; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RWNYzRq/Vb7U7TDz4etpmaiwu2aIj7aVaqiDoz+nPgw=; b=GG5mdKUIZXUOAtD4JuNHPDzvfoMAGo4yHLw7tMy0nrxiOuFPank9O5MVjiCLgCnLYm l8p2im+i1slNSVZumbKZKRDbQONuNGS7nGLdJh3BoQWVHwwP4nDX9PscAuMxj26koX/U sL35rvNzAPGpg85GrwHHL7RyPabQkwrZiGm9qiuPezKKA/Nw/rCO5vLM/JYrYDaUCRHr 4r6cSaUXXGUvqstQsb99nY5XwGvOECCP0tWGw84HxvgNB69jZ+hEptvus4I8sZPQOZRr Hcsmn43KY1m2BA/fSt/uJfBIiHysXeih9cvM8KRMFvGiDFER5jxtZ6DVSuXU10DnA0dM ovkw== X-Forwarded-Encrypted: i=1; AJvYcCVMV9J/xoBhSY3MlZH0YnEb+6Q5YW7DCDlR77EtDawbjsAs2/zJgCv2TAJ8esvfuT2uaA7g1dW4855A@vger.kernel.org, AJvYcCVzQicHADDFNU82RYjEpDfGMBNdwzqPbSbkJoGqaO267KZLR+Q3e+IfYloLi7WC9SlaZbV5zkedbQJOlzNQ@vger.kernel.org, AJvYcCXJxPDFroaWOQxRn0oniBkKQmOacptYXMd2pw/7Ep4fa0D6k7rZVBFzrFWNq7gCzj47Wb4CTMa3p++FwXSQknN1RQ==@vger.kernel.org X-Gm-Message-State: AOJu0YxGtL974sI75Gs3UtEyV/Nr97ugTldcid3h/viNoyySYQjHmzEO Fz6liGt6shNhdIEdU1PPa5FmLrxcYdfCjibOj2NwjpV31P+eK9XPH6cG X-Gm-Gg: ASbGncu5xcsNDoImXy8x6YAwHmhT4Oe83IZAEOoN+YqmLTMK/PBYHFXDopJD6cgRt84 ueJtnXzgKYbWOx/JYU0P0y33jtYro8/2XCIiG/X/Xqjjd/rNY/nINQjQf4uw6kDQfZw5NhYENCU 3v5S8IWGF4FQX92vlPElvU2zLjOWSFLwsU8njthG5PqBe37jOmFnwsUIaSpg2bV9AXOWidQprVa gnRcPb1UbjMziLn8HpjHZ/eYveYzO8T6kd/FFAL4pGWY+UeKN6H75m9Pi57ZbjbsFyb0My4ncMy UZCvwzftBrXe0MgPM3Oq3QW4aA0frRB7CReyTeLF0PHeIyMKb/Horq1n1Enc3+LkAUuSZhJthdZ LvOYYnbtr4YvfFupTGyFrzCWurRY= X-Google-Smtp-Source: AGHT+IEXsVw2KwMnRYVKtpu8e1JAnW9qtwH2og9QK2RZ8U+O9CmxeO5e78o1hHozrdEZMVvhwrfG8A== X-Received: by 2002:a17:903:2b05:b0:24c:a617:1185 with SMTP id d9443c01a7336-25170c477e7mr110295785ad.29.1757325694926; Mon, 08 Sep 2025 03:01:34 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:34 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:35 +0800 Subject: [PATCH RESEND v8 11/21] drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-11-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Ivaylo Ivanov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7534; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=wFKk1NRP+ZMWRbYofs8l7oAm27DHSag/Moujm6quV7I=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlEBK67sB8Qe9kwU0EWfhRDDrd53yxKG0AF8 SHdU+1yyTuJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pRAAKCRABygi3psUI JJSrEACj0DYxkhVmKfGvq4xH1M1KjYoqVRhVnQqRLkEW3vCysHguTQ7EFnLMq2QJBolJhKK1sLc wsNstC42jEOo/7D/tKrjBdNnbzrJNG8/+OC1PTVSHS9rG/dxQkeTpuqC6GJEdFlDa/piSAod/XP ZG28OkREfoKpZhP/dRpx23g8YeGpKRjkWvj/NbcBjfyQqGsElrNKfrOpEIYPVZ98aj1Djk78iZY g9bST0ZCqZ6l+0lWAi9o/xGn6R2acPz4udomW0yIn2M99si9zIsu166ch5SO09FiWRS+z3otah7 ecGAukVQcGJdBjV02OxBiB8O26NSIIzwta95VvSXxfBKM0MPDhufzlifxyg9QvqBhTm7+9VBhDU 4kBB1MULKwCW80WRyG9MJJDlbm5x2n7TZ7VNjCktO1fdMnTLpGh4DO2Xq3XR9q9CYtncBvc0QCv g7UKDYr8BqLG5Z3uSaeUf5yYvoUWPqlpDEPuUZf0r0Zrmk+elmYYMbhqywdHXMzLeRVBN3lNTyZ UckITeHx1TDD74dkT77eE+jEt2bsuKJiGj/ehWuRHiXsQ3mMXhud//9lpslOaJhYBhYtQ/Z74CA 6GFTR3X8zdtOKB+RQNCQTJSLSkZ/ieXLDE8JuqrgKbE0otcu0yiwIr5FhmZ4YGvCcIPwHWCIgUr CREhv2hqBhSxd3Q== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found in the Apple A10, A10X, T2 SoCs. Tested-by: Ivaylo Ivanov Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 127 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 127 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index bfaf926fd47b02a7d77ac31cbb97779b5ebedec4..37ca7e99aaad97526c468d3c98e= c7ce4fe115763 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -392,6 +392,115 @@ static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR= _LAST + 1] =3D { [A9_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, }; =20 +enum a10_pmu_events { + A10_PMU_PERFCTR_RETIRE_UOP =3D 0x1, + A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A10_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A10_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A10_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A10_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A10_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A10_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A10_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A10_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A10_PMU_PERFCTR_MAP_STALL =3D 0x76, + A10_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A10_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A10_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A10_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A10_PMU_PERFCTR_INST_ALL =3D 0x8c, + A10_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A10_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A10_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A10_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A10_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A10_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A10_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A10_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A10_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A10_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A10_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A10_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A10_PMU_PERFCTR_INST_LDST =3D 0x9b, + A10_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A10_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A10_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A10_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A10_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A10_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A10_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A10_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A10_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A10_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A10_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A10_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A10_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A10_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND =3D 0xdb, + A10_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A10_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A10_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A10_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A10_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A10_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A10_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A10_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A10_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A10_PMU_CFG_COUNT_USER =3D BIT(8), + A10_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A10_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A10_PMU_PERFCTR_RETIRE_UOP] =3D BIT(7), + [A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A10_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A10_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A10_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A10_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [A10_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -905,6 +1014,12 @@ static int a9_pmu_get_event_idx(struct pmu_hw_events = *cpuc, return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity); } =20 +static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1105,6 +1220,17 @@ static int a9_pmu_twister_init(struct arm_pmu *cpu_p= mu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_fusion_pmu"; + cpu_pmu->get_event_idx =3D a10_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1154,6 +1280,7 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,fusion-pmu", .data =3D a10_pmu_fusion_init, }, { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 448BC2FF652; Mon, 8 Sep 2025 10:01:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325701; cv=none; b=Ei2Ve+G29yS1gLRyKAkuFLukNJ/T68ypxo/1f08X9bE3H68m/Gss3EGL7flM+0vJUh6FrQazy+Gxt3zV0+VWB+kVOz8zJbE27ocWNUJtgnh2kUndJ1Ncl1ECUMuV8NiB/JA9oAE8S+lm1SEuS28+uIutt4NmmNi0oxz8gsa6i8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325701; c=relaxed/simple; bh=eXvZmBK39TeWTus25bvyHnZagmjkYHmZXICDGfTJwOc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dZCPAhMbuWGyGzpJF7W0kkMD8F072DvoW6eXpB0lAwWgvm3QYYEh2mZV8Hvq5V/ndL4+pZ2XyCspuWOL0Y5G2m0iwPE2KTwlaBWQaJ7W6kgPIWyFs29d+HeJH3cj5zqRuhiOYaJGlQYz75/gmyKufFLyCfvle84EhujtQrhmuyg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=I7yrlhdT; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="I7yrlhdT" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-24c863e852aso37862945ad.1; Mon, 08 Sep 2025 03:01:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325700; x=1757930500; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=071bn53SF5Y6btM+NHs+KZ2Murp+EE2d22d8zM6NOIs=; b=I7yrlhdTUlVZ9fQpvIEw9gL5ueKHPp7pWQV9E+TK1QHkcOQ3Aa5rFMLiaVcauQ+XqB Q5Tvn47Eb9QdUbofD68rhos+WZS8eMl49yFcpIP1JxSfZn8S0zp0sk30aB4nBIiqSKmp vQZ2E0kqX15tq1GwybpSSbpGDK8RoDMtjZKo0U+1AHSVIv8e8bVgKoyRZ8xRqltGE7LN 2qcp3wtRGKJ51edg4qYQrrsQC2yOvd69UfDpJ1+Qy5Q/7qbHw0wLmdgWst1AKhP+K96o CCR76EcH9MnQMUnd/USYdj/BNeSxeH5JwbUsP9UoF+Qwug0q/B/Q5rqncmpdZAywwe+N IXfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325700; x=1757930500; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=071bn53SF5Y6btM+NHs+KZ2Murp+EE2d22d8zM6NOIs=; b=VAYCnv8Otpn5KPjJgIPry+BlzNFpemov74FRzS9msdBVob2tTyyJrjlyU/3/KUypQd tjDw90YwR2+OZEIRYscOwNIdG+KkGtkzG1DYdmgtSg7v98RygmLOs8U+yiZ0dnagsTVs jp/hsjbfZ8Z9lEiiyPLNW7B2COlOtFxn13rBvd6YFUN35FigutN2RW2g8tQ7LGNI0Hdz Mmv77MkaPbWZIsJrta3ZZVEe1iffqMt0D9rspEGX1+JQ5gR59Iky303x+T8v5UcddMgC WqpNAY8sxE54O0KpotTcCkXoMn5ULXmOvk2S+6g6XlQwY15FJRxX1ia0G+ELhQ+AzC3Y H0Aw== X-Forwarded-Encrypted: i=1; AJvYcCUR+dTrSXVOdXB9JUW3nVw6Lh6z8vANxOAJcCmaeMpb1G0xLrncyptDTRFAkAeHEGOWKVUtgU5JEH+RQKxYUEAEEg==@vger.kernel.org, AJvYcCV61LZY8lDNe1kcNawI2mXEwWWWPR1nvsszw8GY7tJtqiC21OaO2KfuDtUInKAeNsZlCNUVPiVpXsUVxYFe@vger.kernel.org, AJvYcCWJ960/MoI5+arYa7QlLki+LpVIJ+fh46I0eUU5B0abX+JLvFtD2D2DZfPocsh7Q5gEnax/g/EnSQGQ@vger.kernel.org X-Gm-Message-State: AOJu0Ywj+8crn877KfVXgzR5E2JIHds94eCnivNjLY8WZmM9heEsqbte 1vHfmOBYBqtdquiD0T2avqBnpDYzmu6eKqgMDvzupbQPwt/j2o75x6js X-Gm-Gg: ASbGncsHn3GQ9uqfT6PhhufDduz5xrOPyi2kTTj2+Ph2GMnjw2TPbiRqRfiarWskmE1 EpoQ9cUZBjdZyBQkco8xor1dxXeJ+XkZKV5MD3AqEXsrKPRSLq54FDIyHk6rKrP3gjs/0C/MucU yBa8RI9vColOlYUcQtJaihCyXtAp7jpfrNsFDzeKM9XLVNJi/kclTlHVDK77szju4z4QXSNJTz5 hibS6h75PXsSAmN5acoSV/xqaohHvZGLlUryrpLgm3X8s2cIsnQG/rWSf5mNPbW1IG/g3AyAZ4E KGsedLwh6MNcVIMWp2ylELi32tL3iTwcUJL9WWKA82vMQmX6MDxiNgghTiDCeqs6ExU2Me0wHvf efwF5dr0tkXINHAEOdgCvtnLkEkQFFM2ZFZYkzg== X-Google-Smtp-Source: AGHT+IEGUl7LoA/FHitDuvGBlB8EGhMm3IQNAyh8Mue+gzf027Ms5/fwed9z1hSvn4P3CoOF3PlTMQ== X-Received: by 2002:a17:902:e80e:b0:246:cfc4:9a52 with SMTP id d9443c01a7336-251736def47mr94169785ad.52.1757325699545; Mon, 08 Sep 2025 03:01:39 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:39 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:36 +0800 Subject: [PATCH RESEND v8 12/21] drivers/perf: apple_m1: Add Apple A11 Support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-12-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7991; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=eXvZmBK39TeWTus25bvyHnZagmjkYHmZXICDGfTJwOc=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlEeTgLQQhpA8oGsFfUu7v12sKxAAOX9fPuC Y2ZZ/Pq+96JAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pRAAKCRABygi3psUI JIpGEACKmhVZVpkC/1BZ8oss54MQgUZvMj8AxKLzQ3g2/6tHTC3VdvJduPbOChQYy/E/nnYjAHP lsPAb5+xs16I9BDnoJTxgeAdr6QoJALJWx2PESKF/kcjWvskFGd2XvAI+NQtW/Q/5QLNbXSMof8 zkXVQsdcWo+4kENgKWH6iVSNbf5NmnMlMmXu/ZXAr71e8Vmwt3OrCYBZRzQ28sCUCZmGjnCr5Mg TLzMcnhoYla3P/5i++C6J3qvRgzNYpslXNyfujxRB8W2ylXO6RROoWMAR0gf5Oqg2IUaWWO3ls3 thiaNa/mZ+BmxTT1uPOQHM4j3HgyQ4l939BzGCfH2bufS3XuxgakTfA/yE8LNBfu1068Hq6vTN8 Qb9oGhOnqk4Eud7jKUvXFSPefqntZjvUiOZ+inUows5qAG2cnhzVlbleHoDwV8xgBiYkW97pKPE 3IWqqiKzN5fZW659D802DwbvjAKh0msZnjqidvjy1F5ILK98ChfBreTlSo/RfDj+DFCruoo8H7b gScMfzb0pN+h9BCO88prWkFkR7RudWFDLNpmIfCLt0kJtcpiomt0Wyer0UZwe4XHyIXiSKvzgEs 96iJU4gXjUVFTaCr59Bkr0HKXduW6rRT6nRlc43+mx9CC5qlxWSLL5pKXq0QvmQNSABvTtUF4mX wB4zZQ1xX3apVaw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found attached to the performance and efficiency cores of the Apple A11 SoCs. This PMU can deliver its interrupt via IRQ or FIQ. Use FIQ as that is faster. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 137 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 137 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 37ca7e99aaad97526c468d3c98ec7ce4fe115763..31fe89c928364719ee0d7101128= 6a91adaf6b99f 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -501,6 +501,113 @@ static const u16 a10_pmu_event_affinity[A10_PMU_PERFC= TR_LAST + 1] =3D { [A10_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +enum a11_pmu_events { + A11_PMU_PERFCTR_RETIRE_UOP =3D 0x1, + A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A11_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A11_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A11_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A11_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A11_PMU_PERFCTR_MAP_STALL =3D 0x76, + A11_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A11_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A11_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A11_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A11_PMU_PERFCTR_INST_A32 =3D 0x8a, + A11_PMU_PERFCTR_INST_T32 =3D 0x8b, + A11_PMU_PERFCTR_INST_ALL =3D 0x8c, + A11_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A11_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A11_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A11_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A11_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A11_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A11_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A11_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A11_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A11_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A11_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A11_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A11_PMU_PERFCTR_INST_LDST =3D 0x9b, + A11_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A11_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A11_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A11_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A11_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A11_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A11_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A11_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A11_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A11_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A11_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A11_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND =3D 0xdb, + A11_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A11_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A11_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A11_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A11_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A11_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A11_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A11_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A11_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A11_PMU_CFG_COUNT_USER =3D BIT(8), + A11_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a11_pmu_event_affinity[A11_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A11_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A11_PMU_PERFCTR_RETIRE_UOP] =3D BIT(7), + [A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A11_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A11_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A11_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A11_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [A11_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -1020,6 +1127,12 @@ static int a10_pmu_get_event_idx(struct pmu_hw_event= s *cpuc, return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); } =20 +static int a11_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a11_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1231,6 +1344,28 @@ static int a10_pmu_fusion_init(struct arm_pmu *cpu_p= mu) return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 +static int a11_pmu_monsoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_monsoon_pmu"; + cpu_pmu->get_event_idx =3D a11_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + +static int a11_pmu_mistral_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_mistral_pmu"; + cpu_pmu->get_event_idx =3D a11_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1280,6 +1415,8 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,monsoon-pmu", .data =3D a11_pmu_monsoon_init, }, + { .compatible =3D "apple,mistral-pmu", .data =3D a11_pmu_mistral_init, }, { .compatible =3D "apple,fusion-pmu", .data =3D a10_pmu_fusion_init, }, { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00E671607AC; Mon, 8 Sep 2025 10:01:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325706; cv=none; b=uBUFTCLIKq7oGlMB/AaC0bcRyGYEfFYcyfLdTi2UTHSmKaFbEbEbhTPO8EHkFbJWT2hz39JR9fd/D6KA4R7djsyhUC6tc/SIM1nxXD9K8tyjOXwjdPnX1SvX1/oK1K/E9/hTT9iD2/x5xa28J+ZQw9WGTaswmMzdWuPLTkCb09Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325706; c=relaxed/simple; bh=XiGGX/gYUODKcUIpICueRO0ZWhSBnplWOTrgw4sJMTI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TQGsQvCIBkphznY+XSU1arYf0WB1d3ssaGhmySFQNThIV5Y5mMBORdalLti7tsHmBgN4fcUYSfcDQJxGCNlRvNVRHS2RvjT964KuK88yG982pU1z6iZLmqwuwp/6GXBgVYlJLWb6HJzLjEAA9UGVNiOl/z6cZCSLNALwfGgZO0k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=IKiC0T/Q; arc=none smtp.client-ip=209.85.214.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IKiC0T/Q" Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-2445805aa2eso40703795ad.1; Mon, 08 Sep 2025 03:01:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325704; x=1757930504; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gsMRt6a+0MtEqKde4YWuihoSzMbsHghVTF7OAbgmvz8=; b=IKiC0T/QNgPyxdwl3BI9RQymqTFA9eYULnF2bp/ckVX6s2sE0FlnB0yN7i5bwmFkuz 6sk4TTJ4O250yyRY6Qv8O4AnFDaCwi7tmyza1uYmjjTZZPjUj7LzZQxOdt6oZALHRZcd 09rVA+J72cYYmRHabUq2e45Upb2NljYxzeGm4bWVVP/7LQPMhQV90trgyrmDif9+DCld 2WHhOVxI0goHYsT19ymd1+rktu4alMcCXOoE3NrGMn312KbssILYgy3mEvF+0i3+ltst 71bTF837O8OcoKJTJzAlC4jQsVhEZhg1UaECAN44XNkZ9ZaeiNYppeqafAmm1pXMpts2 nvgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325704; x=1757930504; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gsMRt6a+0MtEqKde4YWuihoSzMbsHghVTF7OAbgmvz8=; b=AjeErbCCPUeFzGHzskntzTF/CQASRAiI0rNcpraA+c3Z/ZJ7UAEbJABKwLMAbLnqRN TNeOz15bEIGTJ4CKtGEK9X1ZPbOUMHkKWaV21pl/LkfFt+IY8c+CJXda74eqPXXgsDwy 2zMJxNBGZ9r5eNksH6eQ7v1uyEWUmrMvI0kt/KJaj5R3hR1Xopa14jHdcHOe8aZf49sc 9JuYzK/PshaP7vKNVtl0D8CsXDBji+fEmDnbAsXo2c5KPyz4Js0/DyQzg8NI6TnPTr1L +4oIlikEcxampDg6CSW3rcTDgREEKWlClRMHsV2WjrxIbcW3oAyacIlST72BsTrsiCG+ iFFw== X-Forwarded-Encrypted: i=1; AJvYcCUPLtmlXOCmxpexX2SR8PNQwnzDwQWP0mChZNJR+kh3Wa2IwXjJyaPSY4ONyncIjG2EoMUQjetO7x5u@vger.kernel.org, AJvYcCUrApqRG7yPrxYZw+0kWGVqWX/tU/oYIjqJ1SOtrDR8OOLH0Tq6/jA6c4L/8AdVGexp7dO6Sz6GNa0Ae8K/golumA==@vger.kernel.org, AJvYcCXPskWncg9SmZk7fv/1L4DUAhskkeQAh5ccylUuS6p8OQzsD8PeYW5gEg7U0HppiUsVItuu92cgKadYCtj9@vger.kernel.org X-Gm-Message-State: AOJu0Ywum/2xOnEBj+k5j4345heigPwSdRMHMy8fy0boop11O7PS2OEJ awcx1XxAs8YCJ7pnbDYg8dkyVrEcLyFISJHqH1jxwbsekNcnD2ARXAvp X-Gm-Gg: ASbGncuP8B/9X6Ie9/pArDIeBE9GvSGSBPX4e4d9a74k6GD9qTcyBzDWgZjScCAKwcS JONIc1RIgRbUm4HD+aUhRuK+6jfoay0hb5VzuLvgwKTUe/xaSemIJKeWSk23Jj41DhucbDZE6kv MPtFjdXkuzWpgcKDDieNc3kFmpleHX5D+OnqNzJo5WvE0MMXv/wM2w2VdOTP8P1UDGoezdwQuoo y2yC/lthkr/lDurjzAFCD8p86xS+TGtD3vhEfBD+ZYC3FB5eIryW5oDUw6egeiI7NPGZWAEi325 iCGCk5vMDr+mQBq072688pEQySMauh5VchdgpVvf2kWykxiiJzE0sHQm1pDl7W5Q+x6SiSII8Pl WCNJDOfkqsikygGXuzokyJR1O8tavClI4yWvc/Q== X-Google-Smtp-Source: AGHT+IGWrFFeN5OuYsc2+jqffuPG2Hr5NStgaizfvWwDUNYrjOwOl9gETEIxQibCu9QxuhZoPFAr1w== X-Received: by 2002:a17:902:ccd2:b0:249:f73:bb9a with SMTP id d9443c01a7336-251759a7cebmr75603215ad.51.1757325704077; Mon, 08 Sep 2025 03:01:44 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:43 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:37 +0800 Subject: [PATCH RESEND v8 13/21] arm64: dts: apple: s5l8960x: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-13-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=914; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=XiGGX/gYUODKcUIpICueRO0ZWhSBnplWOTrgw4sJMTI=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlEOIKfaiGjiWT5qhlwzLyEPVCQY/VJwPgay fLx6J5fMyWJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pRAAKCRABygi3psUI JCK7D/47hGQ7EEbYb3RiVEfPUWL5oGTUJJuyrEfYATok2diZbfaO8vsmGKTDnEmqtKb8gqU+2n7 Lp6zjhh9oEjKyRrzDCkkkklAINjLnHxx7H26yAlasJddrqlaH7kCy8plaLF2XJ6M6QSaN8QTqOn lzyI1mnllthTYxE/9HN9qXHReNQDyfU2DBTuI2W8eGaOZ55tqbCkrqUJ9eDRzcDs/teI6Mog8tF uFUki4yo1nji2ZfM5tYEPEWsq/cwKfp2HLbHO9HGORcl++fa0ulK1l2lFsCHGXMhFpsItUoATlz /yel0bcv+HY7DXJ6S8fG1IHJPp+x6HSki6RiwuyHZDON21iabzcb1AuMF2jeYGPASvBBDSxyFW4 J2KgywRdiPunrkLovWNtePU5yquVzgqW1TaTA+B/mtDJYmbgGfucHP5QF6DsJJVXOgMS+ZqbEPr zaF01qsBjk/QutseSkV90pKuIUOGYFJ0zFwPF1tXd30QXJ/+4ZJhq46HfG4/+1POdsdX1VAMhz5 aiOFVzqmdR3Q2StZuFBqPGJN7fVpDeEZ3UFlyBzKkXEOS1edsss5HO+qklSxis7yDADLnr5A6Bf YQ93e8rBpV7P/nz4rlR9VEV04XXOdzT20JF9LIYVYiMdOlZbu/iTrBqGWOP9TwzY0MCU8j12Sz5 dOTPL8I5jJybKiQ== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A7 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s5l8960x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/= apple/s5l8960x.dtsi index 5b5175d6978c45052ded495fc0d18ee3a8fbfdcb..1a3a90f7b9ded42e371ef0b4105= 7fd3081579615 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi @@ -151,6 +151,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,cyclone-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "s5l8960x-pmgr.dtsi" --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 917023002DA; Mon, 8 Sep 2025 10:01:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325711; cv=none; b=oJO9WCCDx9q0BFCoHS8SiGy3T7wwUtNV3f/V2daXUCrC7m9y7Upf9k3HIlW3NPG9Q2JknfNKevh6u/ZL3DNergwXzcStyB8ahqgOmBbh00NDc+8updsNhGBT1oc67LwHwxv5yblJCnQAmvPrE3jgrg17YxwgqBUTTlzXlSUlY1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325711; c=relaxed/simple; bh=1JKajXUwqRhul1ka4zSxgmuIZmZnF5dN2V8kqpA2Ejs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c7ufg8Mm/jVLbokVF7iUenx+8rze8ftAMX17oo9dbeV5gRNHIVsYjxjLWzAXuxO0fnAFk+EdrHgK2fnShbnYzLLN+ueZHh4kliEueBn+LNmjicDvQ4Eb8STJmnP1qOrGedvfwGmW4rpwR/wmD7ZxtwpDOyrXpeMBlghLUA0ZxLo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HRLs+S3R; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HRLs+S3R" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-24456ce0b96so44011045ad.0; Mon, 08 Sep 2025 03:01:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325709; x=1757930509; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FyHd36Q32D6LVFmjxrrSCjpcR8v8mTvafzGLYpLOI3I=; b=HRLs+S3RRXbBs4H8rK59vR7LVW0CjpodVV76EnN05yfUMxrY921bq5PK6tZGvbqG4H ex6dh6AsuTf0d7YEppuopswFpunOB+2XotSHQDA+oCKpAIRtv+cai2/qvM3qavR3LfS2 Hz6+ADMXdu+uB7iy8MWrz2Ja2lWVAK3njJZUvvfTxP1wmfVpzcSZ+cRRb15ybSGPQ2dE ixTmwNd0jxRgAx9eBUzAR0ETyW328lNweFLH1BaSmlRpk0Zi+RMqA4TIc8modRchwXBL 3RArMpl41+y5ESvq5psKzrWO3Y/QtXcSdDPbzYKDTOQO1BNqFDl8oEIOMfv2aoLGq4Ty MsHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325709; x=1757930509; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FyHd36Q32D6LVFmjxrrSCjpcR8v8mTvafzGLYpLOI3I=; b=HM5glxWoKTBPedSn8ot8yyPPE9oRDxnGOIaDLanePtcUmphoH6a7ybBrYAXkdUWcjP 1Rw4lKEdjTBvAiQ9ts2AclR8ENIrC+wAQzLulCTC+3Y8H1JV/GR+jrQWrLa7sWQVTnFu teYtrjjjpnDEKy4kAu5f1nwFB2lBju9QTX15AXzt4AOvS0+Y+k0nhPt6QZ/cvirD9EMG 4wzyoAYlDn/lwvwCsG359CNLPC8O8HI/cvGgzr5XFp5IfJF94e80ZDdxen2haqlSMtp2 mSckYXP3bNJdWbmeqXFbs6QimrS05rvjawNnKzNGaiBrwdashlMbFjm7ZEhSBUFSoboi pd8A== X-Forwarded-Encrypted: i=1; AJvYcCV+DUfBt5Vs8o1bQ5a1RvNzF72hzTl9ULqnzkIf8XrDh7QuIEsd+kITE5K81mkS0e2hyxXAhqgTs3YFe7vYY6Sr5w==@vger.kernel.org, AJvYcCWSk/Ml6va85p1vBLa8ucsA3mlxt/J2KfvRToJioeyIeZUyDrelaAJRcJUIPZxtLlZUqxAny0ixDiII@vger.kernel.org, AJvYcCXpm0WV8e+Kz+Kl4ntl4WHrQPGkQI1dAoybf1s8H5jfXAwzWhdROntcfH5UjtvnZM8/pfuKCLuLnhPi8F0l@vger.kernel.org X-Gm-Message-State: AOJu0YyhZt34cUzdEtT3lZPpoHdUhoIegMusKRLplYeIcvhfJA4EwOid x8w4SmC7ZBTCoJSkKF4lh6K22icLTjB0ReZn21Be/FhXxSjwbLS99YW4 X-Gm-Gg: ASbGncsNI75RSEQ+hxC70X5ajunq5xB+HXUed3OCbU4ifE02YSIUqNU6uploYSRrTwY iMWO8IX4anyU7mlrS4FNbn1L3lM6Sygi8l8Kj8GbznkfI5aNADhHN1xrzPxd/yEYMVLbR09lYal SRQGZLc8HpPPLfcGdOfhrOHT3wq2KBPTqAlinfjf7KWPxVBPQIaOJnAucbNOT3rF3xmNtijUlEm z3E4fdB0ln03W2ak08VtpYSvmsX4vtn5+lHIGiZ1kcwBxOR1h7YDjNu4B0WX0uro/0VAZK3nozR KFklmKjfvh/Y/tNmm9uk1jF663aKpi1GsGoaulbXgxCOUeU3cJzM2jnz9eAw7QVXBRcrqZG+q6l Fw18z9lfBFmorHnxY6CRl1fX5Mvr4AjJp3Wqqew== X-Google-Smtp-Source: AGHT+IHVU3ALye4sph0Wu+Tnv2WEHOcB5qvS7mM3i56TPwTLcEJRcMe6hHtK6mhihmKypJeKyqYQrw== X-Received: by 2002:a17:902:ce89:b0:24c:af27:b71 with SMTP id d9443c01a7336-24cef93a60bmr134956285ad.20.1757325708812; Mon, 08 Sep 2025 03:01:48 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:48 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:38 +0800 Subject: [PATCH RESEND v8 14/21] arm64: dts: apple: t7000: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-14-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=894; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=1JKajXUwqRhul1ka4zSxgmuIZmZnF5dN2V8kqpA2Ejs=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlEwbV0Ai/6KcBnAAiK7K8h/Hekwrf8ii3JD vUIXaW0sDKJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pRAAKCRABygi3psUI JOnOEAC19Bj2cTcDw/YbvyrR2Y1VbvNwSkj4qxaAx7xK/5DBRHYeRBprDK+1I0jZhVFQEVAcQp3 /ASswENjcVv/tgFKU/1PM6aQQafuVRTDRKa3Rbtips1arm3MA+hlj7pmVMkbN+THB2vxPnJtun5 mQtGm2BEqf+TLJvbm+G/n0jkfTbCsrAu1/N1QXNt1stLCkCPZ0WlUQcLGkPGdhYJQlccxH5CWuo YLQohlunR/Lb0fKzwYVWSRHqPqKJWsSjchP3wUg2uHLnrKuLQMQOkJqOBCWnCVzmJYOpdNIw5sx gLl/Ja54mmF1N3cWrRkqeyWD8tjY145npqfbvHPpeWzcQpTh9dzWMFcsBcyAr1VSd8jGl9nHntV KAbvPrvqeJUOZAp9XU7cih0V5uq17aqZ77tdnFpm/bxgbNCkdIbqa1z5phh/YgJtB4eDhiZgMxE suBo2jWn7tKLb+h7bQxAkcTCQ4gKtDj86TwCNDr6ANv87FtVUdLXFQmaf5VxLWQ0grbwxDNRQkC KIxxWW/Gc/sm3jJc+d4fuZ9gQbBw82htBQhIObSGCPj7jSwQ8k2nwMORywqrLOQ4fW4CeQd+UqL Sw5XyebirPlIIK9P8nr+nPZxMqf8Gqi3zHxbhko6sZ+XiQsIDkpUOSv1QGT/Fa39tjcnsRqJBOL /4nn0Jfb64M6Zng== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A8 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7000.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7000.dtsi b/arch/arm64/boot/dts/app= le/t7000.dtsi index 52edc8d776a936ca5ba58537d4d68e153023f536..98c41473a84098bd70df86c2728= a8080b05b41f4 100644 --- a/arch/arm64/boot/dts/apple/t7000.dtsi +++ b/arch/arm64/boot/dts/apple/t7000.dtsi @@ -206,6 +206,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,typhoon-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "t7000-pmgr.dtsi" --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27BD930102F; Mon, 8 Sep 2025 10:01:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325715; cv=none; b=gXVvbfZ0IymxVQFOVxKo3fUpcVMlfcbHHSqyWghOn+cO3qJAcJB1YxuM1fBCp9bX6IFcNFx1oyoXW+OufmFxhUQoN1277sAZON6XrlQzvTqwWboqHCRHntHpiHTrH1uWZUeR41J3cbnmgFcZNQWdVS3X6uiddbc80gMHpa2TkJM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325715; c=relaxed/simple; bh=lnaE9Aql0p+zaBjSHyK2yyUlKYAm5n38nVhdpv7cd64=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fc71SFcDfvzSPvDWNQujk+x1Gs5XCSHA7/pzLpG65EFRdGLeXg0XIDYE9lcAtajVMY4eaZlRHHC4Q1fKVGIAauAC+cwB/dXPUdvgsGeHYOE/emkEsGNp3Id9YLFfyHEHsRW7Z6TQfP+FY68sqPYLy4PkQGIrWtlRvhc7wr0FKiw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=V9s8yhss; arc=none smtp.client-ip=209.85.210.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="V9s8yhss" Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-77264a94031so2892095b3a.2; Mon, 08 Sep 2025 03:01:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325713; x=1757930513; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=QdXx5WHPadAVmQPefLqhuYKaW1K4eJN9K2RwteEElB0=; b=V9s8yhssDoy38iuJ5mV8g8OW9vr96CjXxNH8DNRacdfwkL7KNoM4kQKH+P5wLd0bCE 1npsDVIcmVxZiWa3TWX7QOdwGIy2b8MVa+Dx4T5/cvyMcD2b/+u43RlpaPQ0aewLYav4 YUsUf11lolpg+YmVl3kNE42pGag29Tgb15Jz3cuzQ61hQZATbmTDl2rT4AlzPakTpWEG XWB+vsJlX4fxYymGkjAOkgBITaMBuf88/FItOwDPpISAsLEUsOf43uja86q3VAxdppwk QTSDJ2wu+kudMwK5RGDA3GmdKLP0d0ej4bZBuZvO+HpyWfKgqbjqnYK0FXEiOk2aAvQJ DaDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325713; x=1757930513; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QdXx5WHPadAVmQPefLqhuYKaW1K4eJN9K2RwteEElB0=; b=oeNvSHHdzVh55utPs3IenCTgWVHJQKN5nT1Ld9JewDZuyAWVFtOChA6Sri88fdUcWX pxHs/jlw9IAM3yi6dGNmFBlaB3J/eIl+AHg5/uugAJJb0oM41JZNZSZPIW1SpXWEt5xF qi+ddK5BJ96myXV923bLsYneW6tsnEq5V4JkSMUP9638Gmk5xwUtQ0xwRkCpwXjFRCQu NDYf7LNsvk7hq2jB0HuwSP3RRk6WZG9h4dSnzuhB7aegmbl3X3fH9MPuCJB1RWrdIt+8 ATaM4t2gZw9/1nShBAIdshhi5GlfTgmTcRzYyTMNwD6FD/+e6YNs/i/nlm2vR6zFMY7U /AVw== X-Forwarded-Encrypted: i=1; AJvYcCVl1ApS/emBjobteyTVEqnxWwXyPXhz0Z+k2/HRYSn3UHqFwSeOpb4afbwq23UTn4Jly1v6Gq05QoSV@vger.kernel.org, AJvYcCVubNxKUUZEnOSWVkYr8WDnJhoMza4slUeXvE8/AeHHs9n1Nx2as0kqcbdTzFtamSFyXRwiY0QdNBCGgmIE@vger.kernel.org, AJvYcCWxi/EyfM0AWbTvHywPiLpa3eYQAqnaiHo1f2ZcnrRxdchxMBQtXHSqRLBqIA9GMC72Qf/ehmEfMH+uXqd59TWiDg==@vger.kernel.org X-Gm-Message-State: AOJu0YzvaqT4UrW1fHBQNq9VJhOW9Obtcw86AjGiLe6e9SLIFCAQQ+JQ scoiFuFcD75A08BXEMTciuRxqvOG/usIg/58MiDt4UrOvAA7dbIpP/db X-Gm-Gg: ASbGnctAuPxdp2kbkm/HCX1C9XqeKyOTc1ORAWiBt+zirePYBOvZ33DHnEw5GN2fpzb oEBscjmkUsC+XODW9JYFesxrqSn9bzy/ib3dMJmJFEzSJigphGdlyh582NFqzmvWHxgThYh+HRt HAYplI+1S4McW6w/ty6MdZBH47J5/ZMRE9Z2g+tbQrutlfZZF2jdS/23qtwxOA0DTA0w6DJrqdJ eSTn5bJYUf221TaD+y9FOsK/NHYKA40XKmvEi2HbYWGVKgOI0ADXAKMUYhf1wbYxHr+JWEIatNc RrpCuJrKp/eavZd1oi+LaGpEtWULEOx8o7mg09AFu1r+5wHWs59sFJv7jwboT8E+Egbff2Nc3g5 q/LEdbLfufR0R8r8ep1UhlRzIJFU= X-Google-Smtp-Source: AGHT+IHVeB2ldGD9lByaVExSPq65coU5HN8zsO2WyV76Pj52Ray2lGVUsmxjkuZZ9lkMLPVGsDPzQw== X-Received: by 2002:a17:902:d501:b0:24e:3cf2:2457 with SMTP id d9443c01a7336-2516e69aee6mr120267185ad.24.1757325713382; Mon, 08 Sep 2025 03:01:53 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:52 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:39 +0800 Subject: [PATCH RESEND v8 15/21] arm64: dts: apple: t7001: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-15-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=946; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=lnaE9Aql0p+zaBjSHyK2yyUlKYAm5n38nVhdpv7cd64=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlEaG4dqRUS59rdWuvyoslW/xZbeU7W5FMYc Dv0BEFms4iJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pRAAKCRABygi3psUI JG0WD/9LyMWx8U1EOfmaE1lMDGBv7OlkEKBgXAeGH0Y7oEuZJ1WCg276LK7MnLHTDx/B2PDzN6H Ui9mfg4uWgxb59NgvOupSiys1A/UpzaMZscIuweCw8NS/WwmX2vWankY56oPTRjUVxwaOW1bpby JBc+sslES3rlwzGOMxgbYWcShTQbGUTzfmo9r7wkvjvs1PK5vOIVgxzUMgw5TWK7on/MlooIkPA iuqEClLbdR7QQZ03wugZkXy0toHbKbwpUptvPTlCNRXk5YCATYtrNILgn5gWiEQ330eesscqEJ4 mfkrYiPDqLn55d/TwShHBIUlwFpABFNHVuV58AS8uCiA0xV4fI3F9ST7nYCiFrrCcJX16I7+R9k qZZMbLlB3QYj/IhOrlnRLqmHPKGOaQAJlMUu9u5Fz72u7rmhZFRQCB5I7vaNzbWePXIB80qDwp4 1dl20lRd+8VaF0oaf36IC5jNAdXVHeV6MJ4hL2He7cfRCMumxvpUzh273994aREZTPpGDHhVm7i VMKu3nCh6X1980fuZws8XwHpiZTCZHN/leOfWCOd6dCGx3xDnbTsTxmYjZlIGVBWxrYZaPgW1Ij fTD1pOsYviZFC65kZQSVzWi8W/Kes9/o0o4vOURRwhxRDdoU5oLYNnFWeEXw026GFqSNbShpPIh D0yR9laSIwEnzjA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A8X SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7001.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/app= le/t7001.dtsi index a2efa81305df47bdfea6bc2a4d6749719a6ee619..0e414018f5acbcdb10db92bec6e= 26ba32e53c781 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -199,6 +199,15 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,typhoon-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + ; + interrupt-affinity =3D <&cpu0 &cpu1 &cpu2>; + }; }; =20 #include "t7001-pmgr.dtsi" --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF38B2F60AD; Mon, 8 Sep 2025 10:01:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325720; cv=none; b=IFUkrqliLiaOyadxf7mdxI8sxumwY+vjV5gVHEW0la3HLv+a4IejrHKsblVANA/sMjQiRTEc1T0kARfzwEtxMd9fqOcFJ0Zf/dvS33q4aDfoZcsSF9CMVwTI/wI4tXrOccoOeC87AUSFyHlBlae1bCRLQkTzJ+4SRHaTQElDPD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325720; c=relaxed/simple; bh=KUmhbvVhE7a9qQQiOxTeh6fcRXxeiaIPFMb6Ibxmxag=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=b/M+kxSHcyfu4g2lbrX17HZUD+HVqv2URtKE9ACa/v/CH0coNVynl0xgZ8u+vMljtc4aMC3tMeObzD4Wpzyl/uDx6+dG7F7FrpYwP03QMxCe1Olxco7IUkcnnVr0TWHclSgc7uyU7+kETNNBlpB6gkvorM+C0uBX5erCxoiKAns= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=LJZAXzEk; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="LJZAXzEk" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-24b21006804so43480685ad.3; Mon, 08 Sep 2025 03:01:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325718; x=1757930518; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=fKXUCmU9jFowxknRpXATBfrh5U5iaqmYG7UiFDMEOEw=; b=LJZAXzEkIAGNsICXft5bQUzQLoW9uiBkiLlEacdNNqkwrOAPSdpQkJuM4X6e1srYL/ 58qgPp6UPuoVW1QQuPaXuVsxT1iy8mK3ImWCFGyeTe4Q4GELeAHkAyhSgOiRZln3M0iU y90fI49sfMGTvTww2jl9iDhWJgI1rF4laEXbeE8SHMrowihXjsOQ2+Z4R7lIQcGr7u7p q0xZfnjQ7CAaky+OR8Rpn7E47n0rTd1hLyx6qOLtd+UeXU4xXfTUbBLEXL+KRrNsTo5T nSA2H6DwH8/84Y4DquDZ4aFOuA6ZSAIqDgn/2RLJ3D2yIXNeSVFj1z9EDa1YwD6rfU9F 4Rrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325718; x=1757930518; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fKXUCmU9jFowxknRpXATBfrh5U5iaqmYG7UiFDMEOEw=; b=bTQSBC0rUfvbDeA/wrRW3g8gcm08crNxjWdTj74ut/qnHixt3aXW1Suz6c5yS9iOGN TL88+4kL4Hs2ntlm9hErdrEvGPInyZOzz0nTdQQgCPpkNq2cqvLcHGYPeDIl3u6jDEKF mD46B+fF1GMke80LO7YqoE5/lBL2idBsHqejCVAIIelHpuA1TrZ7HlG4LxeJ1Z+bhZig GbZx6XI/LJeUKkMknVx1/HD3KwzGEHvHp6PWVOTDDFvdsbhxKhM4rMmNtE6+as5hUYZi QYrAEA2oFS7vC2f/iMea/WPpAimdx0MbriRh92xqossGPMOSKjovh0wCg+KhSu3bRP0Q OuNA== X-Forwarded-Encrypted: i=1; AJvYcCVWWulhTpegcHpBGJUfzX7FdigFPyIq2pAY5p+xxNZhcatXSgCrThDt4Upqk24SA7IKit1Wy5ubGS+B@vger.kernel.org, AJvYcCW2WSASfTslrnNC9tqyUO33EdnpKZnv5cjDDsV1y/wyugZgbBnDIRgvxHZMfzl+4KqAl2R7TLvm7xHit3t0@vger.kernel.org, AJvYcCXpISbA7UF/Eqi4/74sc3i+KQHdMCIPb0oQ2w6R18DoOiR/URQ9a9UzWhyoFllvxITmMoW4Bq3/PHB5JYkSU6OjXA==@vger.kernel.org X-Gm-Message-State: AOJu0YyJnPb7y+v7vJD/G02LUCrSssB0A9MNdf56Pl6IXiwLpAAK5yiV +dlmyd493m58ARLuRN3KO31TgTs/z8MN5M8a5Vvmc01aLMNPguriab2i X-Gm-Gg: ASbGnctumPwmX9cQW7Hxy81O5edl067IObEdAcBKHWE/D60BVJs0bdAMXxOzAaz8Z+w KkIJcGCQWhIPa/96unNQJ3Pb536h/MYU96U63nLd1VVSUcvm3xDlvF9soFzZ2xONv0ElIJ7jib7 Z8kylY7W2vzt37SkveQbwj4l+ehJ6rv6SMEyCYEsKeRCPfUwTTJIS8oYaM4ZK5aaRjmDFXLKXrr 1Gf9iYMdmDYYVUH4bVPM1tf1drn82pL/szo9ZyYF3rN6Rk7u4zrVR/pCUNEwiCRCBGxzY2bj37J yn0svRORbORkavElqIeqvYSTVNGw8TXWPXgrsop2SH/dmWe/qffKTl8jSNScoK9s2FWUm5fAB9C u9zCux9k8lTdDEn+X1MK05S2iYB5YHzGcPqDcew== X-Google-Smtp-Source: AGHT+IEm2+gAoGZa0cwwAA0rX20QtV+5UuqaUU6OUNEfKaf4rVPNAoZSA3dqhcwbE9x5WjVSv6TpXA== X-Received: by 2002:a17:903:2a8e:b0:244:6a96:6912 with SMTP id d9443c01a7336-251701a644cmr93794865ad.20.1757325717942; Mon, 08 Sep 2025 03:01:57 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:01:57 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:40 +0800 Subject: [PATCH RESEND v8 16/21] arm64: dts: apple: s800-0-3: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-16-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=912; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=KUmhbvVhE7a9qQQiOxTeh6fcRXxeiaIPFMb6Ibxmxag=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlEC/KtUs5Hq0AV/39vKlCFghpi48YewdkJ6 gXzM4aJxfGJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pRAAKCRABygi3psUI JMKaEACmwYGs3rD8OMLjnTxxlkBn7vmh9k5AUksNc30NWUwChqVZ7NxW1ETKBoRn2MDPZntSVZG j0Dz2kXqhCTBd/E+9WVvyXc/fiattQEENQs7w+p/Z8OaY7iaUtP/3BcK0FgrqndtaPHh1pEFYKL EWEd0EWPLLApygXTuouliEthc/QiDUCSZ/xzT8w5lYWTaO0snntMglcPEr2oYLBskg92OfkGT9U piHI2YiFc1FIbbkb20ajSus589Dce4xbTeujD8COJ9RNOUo0tqJ9GW8HY/IjjvFQWGillETAnAn Ctdovt8ZeVV9Gh+ofL/XZm4rkN9e11zNHqtZdmk8o7kiAmQXoNRVFlsLmg9OPhfJyOKjnH05r0D nvQVMeN7oxBVCgD+8moOWVzaHFWZKzTbbO4t91ILeWMAaBWim8mTLVkfjBziSP3toGH01PwARya 3Fnq0lj+jZ3ARWTwJejMV9eQBJPMK9Tg0Wj63WiyOZyt7MuZD3J4DuNzc/Lu49pmn5HwdqIql11 q7BYDQWDwh+yG+J0f/hwpblU40AzNT3kPezF10Oi4gUXadmzS853w7ic1Ht52JCSzDEaLSiOQ8D r1KrcLXmAgFbVMk301HYHnr7mJT4ua1cWxfCjQ5h8y68yru2FWF4y7TV2zazaXmqUhvDmBnNG01 tY/GmJKgRZKwDTw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A9 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s800-0-3.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/= apple/s800-0-3.dtsi index 09db4ed64054aefe5b8f8298553d87fe5514e81a..bdb66f7e0de43a6a751af37c9ce= abba44ef907d6 100644 --- a/arch/arm64/boot/dts/apple/s800-0-3.dtsi +++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi @@ -180,6 +180,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,twister-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "s800-0-3-pmgr.dtsi" --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47C662F7468; Mon, 8 Sep 2025 10:02:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325726; cv=none; b=R5x/32/62b6/50qK7lnlNAoj0XEssyji+p/WLKoy69EIIoapLhPFwCIDo/XzEbbvKjFgJ9B48MmPO9snW3rFNy1/a4m+E3AoOWQJgEpicWtx+D7V85e05vcTEIt37FRRVO/fISVlEV4sZ6w2olY5qh4O3vRUITSLRem59f5HxTk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325726; c=relaxed/simple; bh=q41LAG04mQN+h/yjsDMGUnk4+iW5c6zrOTH+jcEbjrs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c92NwpNL3OezozDtWeO99/K4FH+PljKow2JsUde3iO3xBHLyavVyuhH33QfKxzIsDUiMYDAJ9YD3YVoVoZM/eB7PlQiQxLUWYY4LnuHS9poWnaK8vi/HSp4zanbKZ9lbFqoBdUscbn6B+QaYBnr+FwKSdobrYYBXAgdQB7VMG6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=lQP43vze; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lQP43vze" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-24c863e852aso37865535ad.1; Mon, 08 Sep 2025 03:02:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325723; x=1757930523; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=G1i7iqUxmgg/DXwXQpNr1KmCqr3Rj4mhCflPyxgc9Us=; b=lQP43vzeHA5WKq3decbaNM7Btdjerj9J4ZPNGWHhK5LjRYTiP5UXKaAozbSTHNRrOt R5K36xEi4Mtdo1xpQze9FEUHBfdLGL8fSVlqWw0csHVRZ2bQQwEuj1ut4lT+sCNoAppD O2NVVUiV1CMLRkyyKTb66rCZa4dZD3oRSDBK1uSpRkit8s5TxhXsGYEhpIvGM5PS7O55 Vvs71XL69xlgdD/V09EVLqwxTQna1vnoJw5FiYGVQ+2yKYyrdUu3nOKbNjcChv56gM7b 6urktp2H0HTTvaw+uUmwTKtlWp75kvgccXzgXDT2RCQYiDKtZy/iSsHBrpPrjyQiG5fd TvkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325723; x=1757930523; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G1i7iqUxmgg/DXwXQpNr1KmCqr3Rj4mhCflPyxgc9Us=; b=EWcD3gw7TMzJR4c0BfJYSBQUHBP2HtBWysMAZitbp8ZE23IZj9y7li13doyGlxuXXU KUGj5IaL2pTYClENNR/g/iRuVugEnKVjcB6KiuT96ke2qOU7eGS2Gb/IR+3Oy5RCN0eh qQS14WLGPCfKvW2ltUH2X1jlfBgP9b8+FYjR2QbhCYz6DWC2bhjGBKOOv4zFN4dGKPjD ONtCnUMGeMyNyQI6/U2u/3+qrJkhaG4kuF07xHdrtG58GcBpcL6d3OwY+vjeUCGLhWrC 5R6ws3PB0jvFnQdkDSyUvxoMeZTqfj+LcJ+CPf5Aas7n6spWGXrn5GLp7ZlP0GRdiwQw 4XuA== X-Forwarded-Encrypted: i=1; AJvYcCUUmDNqG5hBevcnLwYkeE1uezwrFaAYldwZ/ZrjAlej6Cv89+JUdxqAciSOmMJvRMH3yTjukMjuH84F@vger.kernel.org, AJvYcCUtuvvNhu9Qggx/b7/DRZKsP4ICwlkjf4VC1cJva+OWJskF3tduaEgSyLWsAvzftlOpkLRw8TdH2NVPygzD@vger.kernel.org, AJvYcCWQqzqV39TttEfNTyPZK5B1NaoVD/q1el52qL/MDJxXLp3aeZUL+mOjHJCOz/Ufk6CbVboWswCFqq88A32MgW0QvQ==@vger.kernel.org X-Gm-Message-State: AOJu0YwJJx7Fb/nCY2DvBsAXobgnfxLely8katlKINSl49nTDao5i3sA bMZSL2vhOeyP6HNPj3bZwlhrPxhWNquHdD3F6jz4mVqBf49IiHIp0sUI X-Gm-Gg: ASbGncuJio4yECJu2Bd8NVTDQwzF5qxH0YB1GcEHAO2RCe5CFu8VnS+Be8eYj+AHYDD 9yx8luDzhLSJVaMmUeGvJfINGyeTod2yPGXr3nGP/2lHZEetY3lCMO300cBa1Z40X3C4LcOx4EK 5alcEGKAMWceSvmXRVbR1qZHQswK5mQILFY2xVSe/yqLMEGrvgV2+sBHtLCgc7XyPXt4xSZRMtb jBfg3eFtCRLmUm2aMjAujqTn15yS5O69SQ64DplU0Cd3P2HcmbnFpyRSagxTs+JKgHJp4huZGD9 CTX61Mh7VouJ7myTrqOD/9sr7VWdGefgrSsFlxjLT1K0Ldu1yOtbFyBwlEstBVEe1ta8l1bYsbz EdRelpyKS7PNmSztpwtzVE9kJs54= X-Google-Smtp-Source: AGHT+IEephzG6wPv+SDfh/QNJZfyYYZEGiN9nvrRGlXcpvwgSrHUd5DTgv1ApG48nCxk+8qMKPMzuQ== X-Received: by 2002:a17:902:ea11:b0:246:e230:a99c with SMTP id d9443c01a7336-2516e97e544mr97305725ad.20.1757325722576; Mon, 08 Sep 2025 03:02:02 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.01.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:02:02 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:41 +0800 Subject: [PATCH RESEND v8 17/21] arm64: dts: apple: s8001: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-17-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=895; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=q41LAG04mQN+h/yjsDMGUnk4+iW5c6zrOTH+jcEbjrs=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlFdIPv4SPsQfS6q50PvS6+jpXMZuVxHeFTQ rKoKjDWLbiJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pRQAKCRABygi3psUI JD1XEACgJgkU1uz5AspTlaQ/vskTVHNVVJbTFwN29DKlUvF5uCFpzsIXD83ZajprFY2ZgAlL2Ds CZmwmM8JvwbHtT0IMBZYLkMj4V2j8k2fQYv+HoThtLD7q5t6xkkqIHkGQsth8Kp9bnTsbjwAy2N eXy8BKTMHlHMbBVNsFgws/1FSIeQgDTSquG7I21zxR8dZe0tIZQMy4q7b5QqLPEY7pKgGzBCORA /hfEtDf6TrAIHmSbfDL/aJXylc0IXCHZATjd6jj4OWhEVO2vSO7jBJ7niapmSoMPyDSN0ISzfd4 wtD7pmHaw/ojoSYcDzYQJQDtCraK5PX6C4DHS2cdGbAmJo/iSbGs/NfLfGA1VU6FVqJUzPHW8vF HGrDmpPQ3r7BlfFbYq+hvw1SaEAKFAKCUwoxd5qNXnw32G/uSwnNJ01tsAFvPrs47+mN7fX1Owy ai1rjW+8cJKEx5rscsq4BER7DcBLTUUffna70buak+VESiKYCrU1UgejvJob/E8BEN6oHkY9kHQ sNvmWfYy2wAQkEGYzDSpACkEW/32J28diUq7GoWhZk2ka3Wqo2xnKx/PnW62VNpIMaxHOwoR/52 yA5zRmSLUR6W9+oY3gNkgF2YS1F+5tcG4P4o/DUztQZPQR2SNHj4nu1HPzOX4LpvVWVWR3aYWiv lV/Nos227stGHUA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A9X SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s8001.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/app= le/s8001.dtsi index fee3507658948a9b4db6a185665fdff9f5acc446..ee2702fc807b678023915f72b52= 76cc5a31e1222 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -222,6 +222,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,twister-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "s8001-pmgr.dtsi" --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 058762F659A; Mon, 8 Sep 2025 10:02:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325729; cv=none; b=CyKPDyGnjhJlZaD7lzioekasCgQUSmKNynnbz1jXttZtEhv1EW3pCyqeCUjiGljJo3YVbFbPDCcXx4BrlPXpjynFkfXuJAl3nCJ28c+NBGcxqr3ognsOzl5VS4CyerdH/04N6BjNQuFmosohU4O98aQLfxJXAeTO7WypreNLd00= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325729; c=relaxed/simple; bh=I5bmZCvx8lSOgqzXisEWeIL6b++oNn2j9gQ7uou5JZQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HCuVw3R9FrguxCyzOnAFhmYcjvVbFTlXJ1SEdsP7O3b8ZipJIlT7GpXC+d79ymXy66bsnNlTW7W1eWkMLbmTkZOqqpXdLkcXpoW5i1YteVt4x1kSF+aUXz6M9IjxSAodq21e1erexMULmQ0jabxj1XVJ8nthrLn+RS0IGXUbrxM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=V8SNyRwc; arc=none smtp.client-ip=209.85.215.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="V8SNyRwc" Received: by mail-pg1-f182.google.com with SMTP id 41be03b00d2f7-b523af71683so239755a12.3; Mon, 08 Sep 2025 03:02:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325727; x=1757930527; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=c7UzRpURIuRgTvljraCf/vxpCIMLGtFavfo4dJ3/GB8=; b=V8SNyRwcVyrsIbCqIAy7IdUf4tGjyIn99iGnLEVhg6qK61RDbqC46Y76p8GW0ByHBi B1usy3QNm2OqMcIfFXr5MQzOzYMsXh4/273BonA8aDKKDx0hwPxLKWwWVhz6LEUbf7pb KJKnFmlAjfL1IYXUIZRFdWhaUgNvl705SxAU64enThY9RjIXE1ROMzS/ro5orcAjuVr+ GO+JXIan42OxcSDPzeD6c0y/dWk9wmVRl0Mb5A7hp+aAoSHj3DYfQTGbj6K9jHh5ZTFd 7aRCjGmG492qZPye0ynKWez7DhUPmr/92aqGQpQwjjKZddTWYOY5vRupICwZGt3x/bZf +fAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325727; x=1757930527; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c7UzRpURIuRgTvljraCf/vxpCIMLGtFavfo4dJ3/GB8=; b=urhJvDyWuB7RobCz/FDjq3se7ZEv7eLPEByzViL2g9o2ss9hdbAA6s4z3g2jK1E4Il +HZM4QFRJ5ttXrClHnLaj3+PAKE6G8HMr35ZgLOnx/RNKF86m561TycT/14QhQPZy0V9 1g0OVhREgIeX1T1XDtikg//qVYX+vVv2bECG1+2haUBDwY68mq8DZb8zYonL4c9xl5cz PaGXG65J+LmJsKSd93msA7pI7P5mrTqGtt44H1w9nLqLg+uXb59hif5qN6boYLuAISAZ u7dLgF8Gi1ID+gkxRvnxYPYurRe6Te8yM129nhAMElO28murKaaRnPK+DSbuXN0T2RLq 0UwA== X-Forwarded-Encrypted: i=1; AJvYcCUIV5CXRHwBnX3lj9hHzOGPYS1qvC3Geg42mwtzX6+SHqCADhIT7TsLav86s3iGmFG9mBYz/weuMtgi@vger.kernel.org, AJvYcCW3JOffxrjoxuVirAOEwO1CyWlQYGwkvE2QU+zFDXGoV1nNLO5iajxa9O4ByGs4+R4o3F7Z9in+nQd8fvf2@vger.kernel.org, AJvYcCXLQy7Z/GYflhqPgENhs93IzJXohm8kHRM4OJqAxY3FkM9WJtUhj2JBotncLP6rx0vPhr+JKLmOIw3mzX8pwRjORw==@vger.kernel.org X-Gm-Message-State: AOJu0Yy6sf1UhYvpXycJkhARCPRmGGNOp0vTMZJBLNb+D6Xtg74+SKwM 3NTo7U5HBSQxRGKCAys/Q/w53y+MVhV0qaPzrx6WUfm6+hh3rimRqHuH X-Gm-Gg: ASbGnctpylmUxhvq2EQhXs3vSTpwjCtuPyNFKB3/V+FXtYYJtkPoY8ElzgPsMzBRhAO eRUf5MFi30DgAiG1/4HemtJjj9qt7mK8tvLOa5TkFgjBX+xeboqYFA0f2f39eiYs4eArR6rW+BC 6DXtl1xz0ARV/KSV5SllOGdbUfeMfsQTzrMNTV+G5E3h5g8y0M2dMt9EtgN36vc7AgXWpq9EAcm 4r2KzAJM52GxToIfgQkryOua26IjRYccolC0Yf5MHaG256Se+tmg57CgmgB+/4zwSJLtggma1FT HMNO6RFBfrXuVNg2JhoHfTdvk6e54jhNK8H+uyTiSNwvjvl3globOrJSUaKjTgcXQjOL/6NaZnE y+pfWOOl9TH8LRJlNiZxfZBtiH3IX5ePxlV6nPA== X-Google-Smtp-Source: AGHT+IF8LpVXd+WGZEtF1C2T+vTa9TSDeVl3CnSVMFCq8UOb/1o28OdTA4U/neCjSXbyvg/fcm5TvQ== X-Received: by 2002:a17:903:90e:b0:24b:1785:6753 with SMTP id d9443c01a7336-251734f3e0cmr81802185ad.53.1757325727130; Mon, 08 Sep 2025 03:02:07 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:02:06 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:42 +0800 Subject: [PATCH RESEND v8 18/21] arm64: dts: apple: t8010: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-18-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=894; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=I5bmZCvx8lSOgqzXisEWeIL6b++oNn2j9gQ7uou5JZQ=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlFQ0cZrZzPeRGtCygbH95UuIjln1JvwKkJN 24hE/EOxKuJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pRQAKCRABygi3psUI JJaBD/oD5cXvCu2sBW1J09kC3JBBl28CAnlGWlecEz3qWOCDCR4tZ1cxWW3m2tnll3CaC7xlGu7 PFTC5tfA8pMiz/mJCb/XZcqIg4WEU7QCxjbRE5azyf2ruTRo84eQxpT/JULcO6OxcY59PmSA7HQ BzlzXWiIngPq5ex4K5CwtOZNREQDsqY27ECGJUmuiH1Fetnhf7unUNbE/o6bX0hg48FO1SnotwT +Idf0JNbMEDMHrAzWwrnhZwSmQJ9tk1ED+AQo+idFCmgESTsdjfi2UXO858CcCvwxkdfcf+t5Ot hpAHc9BVLzeCaGhbZdG56La/B3tTDcWJmF8atVIdQYKq9bsveCRrPVi9GxNQVEovMhrlRJi4jte IVnYVenLFmtKcVrDBD9xKwLszBmrM/pYHON27u5fOh22I0D+YYEmirFLX55eMQWupggKY69Ww9u fvSuxrIQW1u7lI99XVZMQzL9T1CuVYHyBVgthtKBSTigZc9kUkWefEvHjF33M5gkgjqp8nki9il 81mag0B5orFM3nSHKMtPkFv+Nn8RtQUxRtJEsk2ipOWtI7ckgSATmjLK1Gh1fwlTBV8NMhMRCNR CWBSJkIvuNSzwzpDZmCOGfhnPwdzrANKt1UgaZPuz8SecA/Fl+X6/JsAdk/83DLWwtEowYsw6gn x35Sp1wBumOXpyg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A10 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8010.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/app= le/t8010.dtsi index b961d4f65bc379da3b215ca76d5f68691df06f4d..d187fbf7e7a214cbbc1027034ef= d0724ef7f8b83 100644 --- a/arch/arm64/boot/dts/apple/t8010.dtsi +++ b/arch/arm64/boot/dts/apple/t8010.dtsi @@ -256,6 +256,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,fusion-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "t8010-pmgr.dtsi" --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B74DB302CAB; Mon, 8 Sep 2025 10:02:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325734; cv=none; b=pW8jGcQbIwctF6QpbbTvo46KLptap6zRKc7DEg0YjgHWUMaoKI7SuPxWDwnI4QP/rxVDpQvyddseJEIqPSMTCUkQ1OGid7lZLuXd/QQJHEn4Lo5RtXOt1lRlw1x4VA+Z8dJ5t1Dx8rmbJlH9N+EzMytRn3cVf0wEOaw8qmC9tOY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325734; c=relaxed/simple; bh=K4a8tKqeVL9BaqFzY33bqex26zqvwpxkE6HkJdl3Qlk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=j7rY/63wkHKeFtAuXUCCWmc+/J24+4PcXqweImXIrM+Nm60OydybumWXGuBdwZaUARGkkuDPhdiSJy5mqCZrrX6mXW/Z8E735Lu69SN059fvu+hO4Fl3fTYx1iv0GHjHTIHMCdqAPkCI1zIDEdlqSSzVkNAgeHa332Wx297dpdg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jYa821GS; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jYa821GS" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-244582738b5so34082535ad.3; Mon, 08 Sep 2025 03:02:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325732; x=1757930532; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7llkAP8rKH/Oo92VHhR1v/h5PxCOy9CRKJV3/2nzc+0=; b=jYa821GSUrVJzf3FCXS4HJawshuBsK0byXikDwN+CgnjSTTMPjPmaUXFa2dRUSOz9s 2K9x++hMeALAyFLwlW89EYRqo/tBxN7hUwm/WpE0eu+N9WZc+oC6xQrmcbjHDjzrrYJ9 knznYXVVpmy7s+Sb8zDq4aB1EiGkYqtyMCvRjXU9zrMe7zKLyMoDhOVPHmRxDj8XXx2L QkPGXAp9C2ZG70pSqy/pLpatfzJk4ofCmFFOYUcO6ucOB4/k/NUmOhovAl80U+I1HtHi XDkSuwyxVSEKmTMVNh7R0lT4Hp9F51i2Q1uWFsJKyVj8fXyzgvdjh5Pm7wRFe5Gtm72b hYBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325732; x=1757930532; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7llkAP8rKH/Oo92VHhR1v/h5PxCOy9CRKJV3/2nzc+0=; b=OJ1X2HLGgeSyoRxXDk9uIwmnTcifZdvTOLmeVNxVujF6Kp6pLJGK1UhLgRL8iZ1beN M6K+F+Pi0iu1zQq6MPBTWoQRT8rNrxbw2PtoaaszGeCbJQrRTpm2lPeu9VPRX9OXbaPp hRvdaq3ahrSwY4lsPgrCN8DpYAaOMsVJfNaESDnCD2z3ZCUaalhMmFZx8xcUh9avzgcO YPrEezkCr0kjYh0g0HYJDQAoYs7F+xgRcEyGo3YXocW5ADKP6ZqCZc8brkVmlH1a1mFc Wft6GYoJ1qwzvqZasjy8iO/KWx+0stCDOfo6+FFQRuSQ1I/Axsiz6wFCEiVN97FOG0x0 05rg== X-Forwarded-Encrypted: i=1; AJvYcCVxDtRVyk4idOT5gCCLgm7fx1lxUC5ZDPAzCjUSaSO6SWdZwVEbzXW1xBMZVTWobaBRQrh75fQj5X7Y@vger.kernel.org, AJvYcCW1tpyul1AQ6py2nBx5l58thDEWUvu+MLpGEuo81qsS0aS2zvej72lXj1Lp6Ig+qorJSQGXWqK0vH1zdUzHi3Wsvw==@vger.kernel.org, AJvYcCWHTkAdXZJTJCwiwWIOk4agqlPBeCSAqWS3xqBFoI4hlzNhOHTiQL0SgdtB+v7TkNIp+IEZgnQ/QTEc3jUH@vger.kernel.org X-Gm-Message-State: AOJu0Yzt5IYfn06bnKUZVtev5JVbt9scb9Sj3mB1yCuFKBlTX0UQLorT 5+7gDc/8sdtga+x0iLRUuE43Ly7gz4fRkj8kwjWdio3u+bg2MOiolJyV X-Gm-Gg: ASbGncvwGkIUZ6XU3D1O6W5726VfOLcdNYWu4N7KMRzGGWki0BcNyX5UECof8V1Zl1/ Q7c8x+vBmmpizOmZ4AlkaF9YDiJfqmCVTcVRz2pvgmQAMoNWDADmcgK/FR+macztrWKC6313uB9 YA1J+LadonQ+RLAnzUxpp2ZzGpo5PKIoJYrPDskDcXUmPf/V8LYUOIC/6HjfDqnpsTvW2MTAoDm 2vq3D+WbInjzGLULsuDFv63fBcbF2LtMEQHo1ExghJzHLzEw8MFgQ2sbCW5BtBxyeqaJbnHH7xj bp6IYFb/eqMK76bQZT6/Dio8V9JTrG9sJ5Kq6r3J4yOStVXAEix1awkSsL1cviIGT01P0QT5oTb MSe6SASxcE22rMpiDipCF+L6e9Mc= X-Google-Smtp-Source: AGHT+IEaOR8JabCaDSqwAtyIemGzOsc6AZgodUmn0wckrYMNjPfuK9mL35dB35gjVYmM5JcfKOQZtg== X-Received: by 2002:a17:902:ebd2:b0:248:fbc1:daf6 with SMTP id d9443c01a7336-25174c1a946mr104229935ad.43.1757325731677; Mon, 08 Sep 2025 03:02:11 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.02.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:02:11 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:43 +0800 Subject: [PATCH RESEND v8 19/21] arm64: dts: apple: t8011: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-19-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=946; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=K4a8tKqeVL9BaqFzY33bqex26zqvwpxkE6HkJdl3Qlk=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlFIgN7AzA3zsULl1lyuey9+Dz2gDXqJtM3h icR5/bhIDmJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pRQAKCRABygi3psUI JBapEACWJrARmkX9DGZE/hI8fBIDDVdvy5/7k0/9TyFg3XAvBnwIfD4gBCmipg1RtK2chXwzIYd YaTCB+YhIraduDc4zMHrItEUQrBaX33oRcsQDoHpIpl+8jFgMvZYejumwotCnhMhIyaGh9XWMth BoHK0bf5iUzW+nPz0CB21tD0NAJo79uOC7JFpW4fwteovhN3wvW3fglcBEIfI8jbBmIuuK2IGA3 5qVD20iehJRzt2M4du+V7HurBDPtyUX2KaFAEjRe1wogOD0xhM4/9VGyawrteSzOkox4xiO2sKF PoTkTaVQfpzdtElEXr1iGzHF/OtV0aPdX0fDk2fe8+HmjyFQOWp+0uRAatJZgITH1FzVgnFzh4p WylgpiQe1iQFUAK5mTk0C97CgyZPvwGMVMediKAgqMHe8X2p+G0ksahTxNQsObrXk7yAjRrH4o/ luaaOaUh8cdD+0eICfl46QSRNKDF8+t0sqodYZ5xflNgYde0ZQDYQTAdNqa5ZQKJF9vZmz7Hegz +FNTK20rIVVj7M1ry228bt13K/mJLu5scrNfRCxkxjUEUoQYodkQQwtTh9p4VN/+I/yEc8+BMVz xrJOcOQTAyDnPoU+Lu9BfP/B+3Zg+TjRBqSukK5GxA6VDVQp1t9ONrJWGHUjr+zI32iNzeIY0gM IP7d0vzBi+hNEvw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodse for Apple A10X SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8011.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/app= le/t8011.dtsi index 974f78cc77cfe28d3c26a52a292b643172d8f5bd..ac203ac4d6eca75655cd590deba= 5c361accf2375 100644 --- a/arch/arm64/boot/dts/apple/t8011.dtsi +++ b/arch/arm64/boot/dts/apple/t8011.dtsi @@ -253,6 +253,15 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,fusion-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + ; + interrupt-affinity =3D <&cpu0 &cpu1 &cpu2>; + }; }; =20 #include "t8011-pmgr.dtsi" --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1DAF303A05; Mon, 8 Sep 2025 10:02:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325739; cv=none; b=qy0BI10XjJ4BsTqusykL8/lMVpVSomk9XasVQf9nMsVOMlLaUgNF4umPxrFHBlEdnRS7yPvIj3C9K9M2kpCkwt4AKhtaPuQUA4LlkK/ASL8npdb+hj9x2LcUiDVRrCO3JWQtpL0rCYAyW9ysY5PXf9bTwEZ3exuIhDuM8tKgvbU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325739; c=relaxed/simple; bh=aC00DD3jiZSVPA6I5+G806JpCyFv8tDWkvwqkbp+yEU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZHCwDxRjA83Vw5b5BI5/eUk+YyvnXUPrSRIcGwyzoenz51ZEYs6vxjecotcFkU7qGTMDUEvN8QJub/7e44263Ca8OOcXDdBaW9/q9IcWUNe2Akg7HyI9h8zw+vhlwp8lW2aqQoGVM2nLRO028ewsVmI16GzwWySJlzGoVS9paFo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=AAcnoaSj; arc=none smtp.client-ip=209.85.210.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AAcnoaSj" Received: by mail-pf1-f173.google.com with SMTP id d2e1a72fcca58-7728a8862ccso3642481b3a.0; Mon, 08 Sep 2025 03:02:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325736; x=1757930536; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=L/G/Lg7srDy0beJ935wpO9N4JjYVVtt8v3yHlGagArU=; b=AAcnoaSjhUTi//Le+lcy1WbKfBBcVCQdaoKvAz048kLkr7EKclf352BCCShq0uUtHX 0yyhm4hl9dhXtgzLGBP5NJpuUzBMFFp1NXmqnUlCYgKtnzZv0vVIS0PJBX4ATSnbX1Z3 u777Rm19+7VoPFqn6efy86XND0EsM/vjlSkoUg0/uqZdEuckReTaq0OcILj+cJSkSOWO Hp2xZIGvuD4KvFrym9Rn76niwPamcEnJdTP0ItOjB5NscV3JEJsVMZ0p7A2ojeFmEI6z VRVLgqDFqFJ+k9PBAKZy6KLu5R2Oi2BTI0mQLfiBfUdIbCY9vik6pmoPE1B2L02gIcdD 4LYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325736; x=1757930536; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L/G/Lg7srDy0beJ935wpO9N4JjYVVtt8v3yHlGagArU=; b=QvxnBYvrHIl4vwsaXr4zfCSafg7mv3BRgGOZzrq1CYrUjuLlPPwFLslWEO3pb3vbk5 8OW02t+vAI4aNXVCvNBREWAaAsPxdRirBO4uchjTovQtAbJ6sZORlOqLFsqR2ufqs7bf AGvjFkCKbkwgryCIYfkmKqV+XTvAnB8gGmE1B61I6cJenlKRXo1swfVt/52kp/KhDvpU b0svX8knzt2J0Eowu1yqbUoG5AWbYGzCx8Rn0f0hkt08293N3llpfhivP8wHJTyRryT9 Vk/I+qeezK3VPBtyVccttzBzx24tvpBNN4UIli1aqI5iY0Ujoq5v6TWLkZAvntyBwOWg Ki5A== X-Forwarded-Encrypted: i=1; AJvYcCUCcx84zvuuUauOabu62UVfVBQ0A4wuI51DYHLbj10EIrliACNjGLqd+zinrtvFwEiX3CpB2/erEPsqGwwJjW5KpQ==@vger.kernel.org, AJvYcCUzQ+Mi2bTu/0xsgqxJcOPB4ifc+6OHRkQ2Zgb65kP7I1rHzLUL+vB4V7jzBCRDWaP5oNFVl2oULPxIUv8K@vger.kernel.org, AJvYcCX+ho3MnutKCi7H7HTiO4yvpquPe/M+q8GqLBDKOM6h9igOTAEgnLpZrcw7azBm9Q3YHHldglKmkr3V@vger.kernel.org X-Gm-Message-State: AOJu0YzwwnKIKs5up4N2VMnGx0KeeD/rrD3tSKTjRoIxSx7Jk4sraiil +9L/+l4uTTbhJ2SeGsgibmcg9BqOkyFazrLWGz7OGoxA3F97lBYAofbu X-Gm-Gg: ASbGncsRJbO5QWdspPC3x6W3F/Hb1bCsDWJcMOJr1RE10zPD22ZtVakgwZwjHOlxgEL C7+mXnoV96gx6O3/eswz6pzExXqKWA8+896SvAttTQ9jRMwKYJLRseTBJjY2wDOyIye04Z+BxlL SDvtU2QmMy+B5aLsAyPlka/1+6kLZYuhf/B13WWTCrIOiIhda3Zfr3xCucWsFzUaO83e01LFdJA uR4qTJb7KrVxhKHLymrDiYU7ghiRXiVcAjWj/1G1HTj0By1iQ/8Y6GCsfI/nn3vZHYBRWIiwa3C 6QspZR2ZFp1VG84VlE3NVa1hDPNiMsb6rO1TgD/E++ghdtG6FVcWYftd7oHsRdcbJ2Z5M+qwUGI eNfKtOhhJPJ91t05cm0SfoHMrXiV0RIDP7yN7/g== X-Google-Smtp-Source: AGHT+IEAIXwSOWBaq4aQTTAg+ktCQQ9sgDbFz59k1ZXwoZKqObK9N5fMVhMYXm01tFsE2HKdytctkw== X-Received: by 2002:a17:902:fc4f:b0:248:aa0d:bb22 with SMTP id d9443c01a7336-2516e1be7a9mr93271285ad.0.1757325736198; Mon, 08 Sep 2025 03:02:16 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.02.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:02:15 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:44 +0800 Subject: [PATCH RESEND v8 20/21] arm64: dts: apple: t8012: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-20-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=893; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=aC00DD3jiZSVPA6I5+G806JpCyFv8tDWkvwqkbp+yEU=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlFBgLFwy76RbumxIV4c/4RoBztS1KNxMhXp g+h0sH8bYOJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pRQAKCRABygi3psUI JPrBD/90RC79QUNeWxSVOP9mLx2PGE9DkCLNIvfuATE0hOmwCczenMR5rjgeBu3TcOy0TL5LiCm 8BhYt4aqJvKUmWNN3PgEud4sP8LUCDqGarjqZz1v+cyHDkRe0JYy4F+PyOstw3hUr1JxQLSxkQP HnQjZJS4N7v1TcAI7fLUs2tRdzbayKHs8LwptI+0FaQW/lPboIjhpvtacsFdaL7XvcqpDmiDgJj 09Z870pzP9lSW8QSO6XD6KDT42mGF0jk2EtrhOVGm8UnbQg6w/6L8KB226S8kJNo4kBAL9PriO7 k81he20AOwARbqedkQ/Cc+KDJk4v2wp/1det7F2t5LBd2b4xvvJsVfH4HJ2/7lQVrXcOzZIi7PC gZWCeBTiejrJmOTg8fr1ctNBQXvTg3psIMvzneDBAX9Eo3Xg6ogoSRLljCOHprQ1pMLxIl5xbp2 h5J5ai0+dBv+gtYuTyknryYVLJc8tizU1jqdpZFKaI8NbfzCBX6rEMQ54o+hs0m/1XkwnR0nV15 zj/G1Hl0YagMVy73AlwTdEBo6pI3tVZiPT9O1m2YNbxtkosB7cGUPHXC0YNDhjqVws4ozr7JLG6 mhg6FLxoU2del3YxiZxOojjgIxBxzlCHC+ujRgGfZe0BIfpfYtl//f4oYeRgYXBetbj6hQhn3WR 5DN/DitjKgshA/Q== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple T2 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8012.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/app= le/t8012.dtsi index a259e5735d938cfa5b29cee6c754c7a3c0aaae08..fc87ab818d975974dd811cedde2= 7292ec79f2c8b 100644 --- a/arch/arm64/boot/dts/apple/t8012.dtsi +++ b/arch/arm64/boot/dts/apple/t8012.dtsi @@ -289,6 +289,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,fusion-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "t8012-pmgr.dtsi" --=20 2.51.0 From nobody Fri Oct 3 01:55:13 2025 Received: from mail-pg1-f171.google.com (mail-pg1-f171.google.com [209.85.215.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81F77303A1F; Mon, 8 Sep 2025 10:02:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325743; cv=none; b=n12Npj1MkwXkNynXZfdojVke9dEBnNcoYameIoUjFQJ1AOlh6Rexsu/Y4XBiXtgZuP7zSnarAW2lCD0zgfFN1Kxt/it4cHxvm8UngLrDFXnCeLUvamTNGlggW0LF49ID7F/f4mfYG3VBtDIeQ92zGhUIQBxfZdSn1nxQqNmHLyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757325743; c=relaxed/simple; bh=NgiaadnBWzmQWHLVGXTkghr12q4e2Z2pGwu46CpKaLI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mfeddLp6cedU+eWyfyW/MOGsp055erqq0IPZxxZNVYkDXSgoqLMbK7nDpinrTVNBNziHIgR6NJI4rzqScr3EdqJ6Sl5AUAQ0/4so68V9A6hcwEGqKMuiujbjIu0Fy1B33QBdCtbYFQ1t4BQXf7z4aBbGT5yuur4UAn+rQVygWME= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HVjvDSrF; arc=none smtp.client-ip=209.85.215.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HVjvDSrF" Received: by mail-pg1-f171.google.com with SMTP id 41be03b00d2f7-b4f9d61e7deso2629591a12.2; Mon, 08 Sep 2025 03:02:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757325741; x=1757930541; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kj7fG7XAER68na8hgLjfPolxfyD9eQkGEiz9N4R6m0U=; b=HVjvDSrFdL/X+lxzvOqmuXGns3mSoQrH3PtVrxFWToE6QCh/gVKqOu8XHWkOuzWj1S f4DalBwZyjyLJZYwgFys+7B7qjvfoGFpxPDwnLSbFYx+LMEuKeZClyJrrYWGI2WGDrCe LzAIW75amZSacwRYNsrjLU9s6Bk+ec9v9dmTZkKaUWaLyw6IlAFqtx3Q311R2gUcQR17 Jou47pTiOP39kyUb2RWdPXoDYpeT20vmrFR9EFRxvXn9hmamjz+lc76oK0lppqtmRGn6 rt+HaEG+r3nWuGktv9BkoluIYy3PXKxeCavnqzWf6BYhf3mbCgahsKrCiQyxI+phatuB ZMPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757325741; x=1757930541; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kj7fG7XAER68na8hgLjfPolxfyD9eQkGEiz9N4R6m0U=; b=oUUz0lWxh4JWRYfbWZq8ZPRr5M169R40G0xW7VSQT58YagFJuyppuS8MbvDvAd+0wZ YgspIvNAmUANynkCgfx+mHMOMoHw8DkWZnlEGsJUUsWyItVJNqbWfRcYF9AHvMW7Krx9 qXp7xdDYIt4b1r1LqHuxY6hLKTztUFrC47KZ/XYsPx2c2VO4SHL2SKOIDpIxvcYxCc7h DuaYfkcZ0XsYi4Tl+9PV5fHu+lNsmzPNyORT4xK4RmvbVzhAdhxFe4EcqiiHyx/cqQIp VgqrVvNdAvDnc/xiLbSISkp7kyg8JMlBHkgneN0rtvswA/dShf7n6poSBF/qcfFZoNVy 1YUw== X-Forwarded-Encrypted: i=1; AJvYcCVyQMb9/0oxZLgym0aUyC4IBqxo/BcDqoJpeKM4EOAb+DrpCd8mKXpK+xKO2cdJcPbotMsIzUAbRp6oPlWpTKTaFQ==@vger.kernel.org, AJvYcCWYl+r7q6Rbn5oE0/chrFZcayhbGpjBhWml6N/tKUc3DFWhT5qr9W2pKZolZ6aifNr4y41gbL3DYpHF@vger.kernel.org, AJvYcCXN0b5ELcbrPdzb/RuD0jWZnkINnsAP+lX1B/Co1yZl6G0zVTYwmvwOd0CVB841N2quvtqAtJobrBGfxkGH@vger.kernel.org X-Gm-Message-State: AOJu0YyW3j1RQXzMCVbBCMJgSKm6qRBxoKzIiMs0U6NtPujet6uX8LdV dbll9/q2luT7TrWEOSzYsuZvnB8SoCbuAytE4ihz27/c8ufyt2oXEkvM X-Gm-Gg: ASbGncvWKe+hMZEbCpviaZ70OH16N3KnWG0ZpVVYtF3Xybd9/Wu05TsFn66VEXQtIf8 I/Ol7GpXEADHQsO07HLwZhaH6ASsSiJo3cNHLUfcd0aQjzQbk1qAS43WHNg/mPNG8VQ01UY/Q3v 4CTINqd6OW4ed9q1ElRbj2vQ2IfwyMG84wBoZHNlf2w+p8Z1rk7r2EmfbHqZ4oX6VbCI6PANClN 8dwvs8G6YyGCqqvWbgEZgYXM4/FHRG5MLQ+x0V3c/d3VlQXqYa1BlVVMQsSiMTlGByMvIhqwVbp LQPZEmhqqtIMxvd90dYnxVyXah5f4g14kyupY+PnmETsxGawbc+UW9PjSWUCD3I74Kro5U+IKYj Sp1sXqrjzHzPzXrA+cnhzV1LklD9bqXdYuZRrqd8EtYA3KO1v X-Google-Smtp-Source: AGHT+IFzBnyCeoSUT4/jKqak6Ru0Kvj/hbUWjk5gn0379Y2ihPn96fH4hCkaATJ2yH9Os2NuxascEQ== X-Received: by 2002:a17:903:1a26:b0:24d:4a96:7b30 with SMTP id d9443c01a7336-25170e41046mr103171265ad.35.1757325740700; Mon, 08 Sep 2025 03:02:20 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-24ccfc7f993sm107826545ad.63.2025.09.08.03.02.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Sep 2025 03:02:20 -0700 (PDT) From: Nick Chan Date: Mon, 08 Sep 2025 17:58:45 +0800 Subject: [PATCH RESEND v8 21/21] arm64: dts: apple: t8015: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250908-apple-cpmu-v8-21-d83b4544dc14@gmail.com> References: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> In-Reply-To: <20250908-apple-cpmu-v8-0-d83b4544dc14@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1462; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=NgiaadnBWzmQWHLVGXTkghr12q4e2Z2pGwu46CpKaLI=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBovqlFI+V4GoFFzmg6iekYjO3wUQsQ2NoToVu02 /eVS2sSy3OJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaL6pRQAKCRABygi3psUI JAaID/9rrnrkkgZNvzI0FIXkGSX4gBtvI+S+ZUhZpHoHLNx5mYa6SzSgxgGtFVh/RB3Ws6QCf2v QGDci6rsLtSmWAjeQ+uCoaMJcuSXbGTSiTxM2apn/N3Qa4oRhy96wHLRUCOq+zCdg9ST0POvKGD MU2QrOVTS/xAzulU2W6Veml9cV05aLbPnSgAdmlom+gXmZqWsicFUuun1bQzeP4YNj3tYfN85gL Kofv7w0kuwRAr6gePgu0je9RzyJZGzY8PhjJho1XYqKM2sboHNKtJOwjHQaOu9zKp1YysVomMA7 a7x3EwE1STEqEZK3KFwIHFQvYNzVPSSbZJX2thGtvHTmjmdfgEJN3RoO+6YFRclhBoR3YY5l+Ez 10S/GLNWdQ7MVEbO4C8mBHFrrc370ZfIoqyP3UgvZZFP5itHr/ByW8ENdblvZRvHL1WeCQKZGQE 3UdpaW3pj2RP417YZdpur7CQmv8YdTxdj0v6EXOxqE+e+IZMp3Jda2PHs2jWOpFfT2QCRfFeQ/7 RajECtYAJvCdQpNmkemfRYw+APevsJeyXEQhKifsPYISo2NkHZXg/lBZB7UQDBY5v2KPjf54Jk5 a6R8wk8dredST8Wb+UBF5e028+i6SkVwrsnKOjn/zcu/fu42nEfKXCQJ4bEBlHwf6eIcMY4iqzH DF9ti+Uugiot7DA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A11 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8015.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/app= le/t8015.dtsi index 12acf8fc8bc6bcde6b11773cadd97e9ee115f510..9bf5157f0e504b7394ef5354411= d3d37e8d5760a 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -284,6 +284,18 @@ aic: interrupt-controller@232100000 { #interrupt-cells =3D <3>; interrupt-controller; power-domains =3D <&ps_aic>; + + affinities { + e-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; + }; + + p-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_p0 &cpu_p1>; + }; + }; }; =20 pmgr: power-management@232000000 { @@ -412,6 +424,18 @@ timer { interrupts =3D , ; }; + + pmu-e { + compatible =3D "apple,mistral-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + pmu-p { + compatible =3D "apple,monsoon-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; }; =20 #include "t8015-pmgr.dtsi" --=20 2.51.0