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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5608ab939d5sm2936738e87.46.2025.09.07.07.52.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Sep 2025 07:52:18 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 07 Sep 2025 17:52:11 +0300 Subject: [PATCH 2/4] phy: qcom: qmp: extract common PIPE clock helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250907-qcom-dp-phy-v1-2-46634a6a980b@oss.qualcomm.com> References: <20250907-qcom-dp-phy-v1-0-46634a6a980b@oss.qualcomm.com> In-Reply-To: <20250907-qcom-dp-phy-v1-0-46634a6a980b@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=23326; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=Nf1s/PhEXHXo8aFyYDttuLdpXnvksenJa+qmRK/vJes=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBovZwfCkHF28rSlsLQ9CGbnty7aFu3iBXCT7agh 5GE3rqn3y2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaL2cHwAKCRCLPIo+Aiko 1S2YCACsds6BQnyNj7TiVUIHaLJTe9q9ddmYeb++/PKSAKx23+PgtgXweKl8wAmQFB4OO3GnWvq CTu/RTyKQ/+cc592NWgEGDff7a8GJItTr7XEwcRcT+0zFlT3R4pIB6ZRkQcb/ukqo0X3Rz++aOi Mo5R8h/OIJFD1j6k6lunEFmId5M9MUcXc8AKy9FktOHh+fUZYRTtA7awDcLG5M2ptqLfTMzD3+X 08YoUfYyoEGAE4U12Pwf3ehyomoIN1BCxA27hYUXmC6amd/bOnca+VLceqk4rG4xN7+EweAxInl QRTrsV6piFqWn2H80jWxszrjVvNYtWilYRRCanOU/39KYkeZ X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAyOSBTYWx0ZWRfXyN2xzacObh99 Yhdmgn7MwbguCRYyyZWve8VwzOVJr/X6b8gxyAPoTaSyq8eLrnS2D2+l2KVZ+bQHaRc6TBsgMbM TFTWnWRfspCCSM9LPbEP+gakBjiPIC6Hr+xKWwQjK8fH9g8LKV6O9WtTCYsqiWBSJDQuzBoRFVi MbnHKNk7uRupxeRaQoEXoUkwHN095UoLYWyJ4PgPR0Ysdac7KnulYsw6Li/PoQxR7alhdcFCqF8 N0lrKmmAysFSU2Px+B6LPiq2SZXygS5UsLSesLkoUPI8/GKB+kUJhUYooa0JW6KANIH7jqocfPf lNuzS3iGcSruA2zZQw2PkD4tjLnuLFffjkcz9ATemo66NOZ+pYhG6xbSBDRnPE309ZRqNlFunsh ma/kdCl2 X-Proofpoint-GUID: xGANbHd0UAXR4OgJ1PoESXB2e2iPiy6A X-Proofpoint-ORIG-GUID: xGANbHd0UAXR4OgJ1PoESXB2e2iPiy6A X-Authority-Analysis: v=2.4 cv=DYgXqutW c=1 sm=1 tr=0 ts=68bd9c27 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=o8b8T06iM2j7pLjo7BIA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-07_05,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 spamscore=0 impostorscore=0 malwarescore=0 bulkscore=0 suspectscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060029 Extract the code common to (almost) all QMP PHY drivers, which handles the 125 MHz PIPE clock. Drop unused pipe_clk_fixed fields from the QMP PHY structures, using pipe_clk_hw instead (where required). Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 56 +++----------------- drivers/phy/qualcomm/phy-qcom-qmp-common.h | 67 ++++++++++++++++++++= ++++ drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 62 +-------------------= -- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 67 +++-----------------= ---- drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c | 60 +-------------------- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 60 +-------------------- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 60 +-------------------- 7 files changed, 87 insertions(+), 345 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 7b5af30f1d028c592500e723ecd27b54ed554709..baf25ae442478ac01a5428fa426= 8470e6b5211e3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -1863,7 +1863,7 @@ struct qmp_combo { unsigned int dp_init_count; bool dp_powered_on; =20 - struct clk_fixed_rate pipe_clk_fixed; + struct clk_hw *pipe_clk_hw; struct clk_hw dp_link_hw; struct clk_hw dp_pixel_hw; =20 @@ -3512,46 +3512,6 @@ static int qmp_combo_clk_init(struct qmp_combo *qmp) return devm_clk_bulk_get_optional(dev, num, qmp->clks); } =20 -static void phy_clk_release_provider(void *res) -{ - of_clk_del_provider(res); -} - -/* - * Register a fixed rate pipe clock. - * - * The _pipe_clksrc generated by PHY goes to the GCC that gate - * controls it. The _pipe_clk coming out of the GCC is requested - * by the PHY driver for its operations. - * We register the _pipe_clksrc here. The gcc driver takes care - * of assigning this _pipe_clksrc as parent to _pipe_clk. - * Below picture shows this relationship. - * - * +---------------+ - * | PHY block |<<---------------------------------------+ - * | | | - * | +-------+ | +-----+ | - * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ - * clk | +-------+ | +-----+ - * +---------------+ - */ -static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node= *np) -{ - struct clk_fixed_rate *fixed =3D &qmp->pipe_clk_fixed; - struct clk_init_data init =3D { }; - char name[64]; - - snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); - init.name =3D name; - init.ops =3D &clk_fixed_rate_ops; - - /* controllers using QMP phys use 125MHz pipe clock interface */ - fixed->fixed_rate =3D 125000000; - fixed->hw.init =3D &init; - - return devm_clk_hw_register(qmp->dev, &fixed->hw); -} - /* * Display Port PLL driver block diagram for branch clocks * @@ -3724,7 +3684,7 @@ static struct clk_hw *qmp_combo_clk_hw_get(struct of_= phandle_args *clkspec, void =20 switch (clkspec->args[0]) { case QMP_USB43DP_USB3_PIPE_CLK: - return &qmp->pipe_clk_fixed.hw; + return qmp->pipe_clk_hw; case QMP_USB43DP_DP_LINK_CLK: return &qmp->dp_link_hw; case QMP_USB43DP_DP_VCO_DIV_CLK: @@ -3739,9 +3699,9 @@ static int qmp_combo_register_clocks(struct qmp_combo= *qmp, struct device_node * { int ret; =20 - ret =3D phy_pipe_clk_register(qmp, usb_np); - if (ret) - return ret; + qmp->pipe_clk_hw =3D devm_qmp_register_pipe_clock(qmp->dev, usb_np); + if (IS_ERR(qmp->pipe_clk_hw)) + return PTR_ERR(qmp->pipe_clk_hw); =20 ret =3D phy_dp_clks_register(qmp, dp_np); if (ret) @@ -3757,7 +3717,7 @@ static int qmp_combo_register_clocks(struct qmp_combo= *qmp, struct device_node * * Register multiple providers for legacy bindings with child nodes. */ ret =3D of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, - &qmp->pipe_clk_fixed.hw); + qmp->pipe_clk_hw); if (ret) return ret; =20 @@ -3765,7 +3725,7 @@ static int qmp_combo_register_clocks(struct qmp_combo= *qmp, struct device_node * * Roll a devm action because the clock provider is the child node, but * the child node is not actually a device. */ - ret =3D devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_= np); + ret =3D devm_add_action_or_reset(qmp->dev, qmp_clk_release_provider, usb_= np); if (ret) return ret; =20 @@ -3773,7 +3733,7 @@ static int qmp_combo_register_clocks(struct qmp_combo= *qmp, struct device_node * if (ret) return ret; =20 - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np= ); + return devm_add_action_or_reset(qmp->dev, qmp_clk_release_provider, dp_np= ); } =20 #if IS_ENABLED(CONFIG_TYPEC) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-common.h b/drivers/phy/qualc= omm/phy-qcom-qmp-common.h index b945fc14cecec4ef00143e144cea4e10225d5947..00041892d9ec7a45e21b0b15301= ab65ed996bd45 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-common.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-common.h @@ -6,6 +6,10 @@ #ifndef QCOM_PHY_QMP_COMMON_H_ #define QCOM_PHY_QMP_COMMON_H_ =20 +#include +#include +#include + struct qmp_phy_init_tbl { unsigned int offset; unsigned int val; @@ -59,4 +63,67 @@ static inline void qmp_configure(struct device *dev, voi= d __iomem *base, qmp_configure_lane(dev, base, tbl, num, 0xff); } =20 +/* + * Register a fixed rate pipe clock. + * + * The _pipe_clksrc generated by PHY goes to the GCC that gate + * controls it. The _pipe_clk coming out of the GCC is requested + * by the PHY driver for its operations. + * We register the _pipe_clksrc here. The gcc driver takes care + * of assigning this _pipe_clksrc as parent to _pipe_clk. + * Below picture shows this relationship. + * + * +---------------+ + * | PHY block |<<---------------------------------------+ + * | | | + * | +-------+ | +-----+ | + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ + * clk | +-------+ | +-----+ + * +---------------+ + */ +static inline struct clk_hw *devm_qmp_register_pipe_clock(struct device *d= ev, + struct device_node *np) +{ + const char *pname =3D NULL; + char name[64]; + + /* ignore if the property is not present */ + if (np) + of_property_read_string(np, "clock-output-names", &pname); + + if (!pname) { + snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(dev)); + pname =3D name; + } + + /* controllers using QMP phys use 125MHz pipe clock interface */ + return devm_clk_hw_register_fixed_rate(dev, pname, NULL, 0, 125000000); +} + +static inline void qmp_clk_release_provider(void *res) +{ + of_clk_del_provider(res); +} + +static inline int devm_qmp_register_pipe_clock_provider(struct device *dev, + struct device_node *np) +{ + struct clk_hw *fixed; + int ret; + + fixed =3D devm_qmp_register_pipe_clock(dev, np); + if (IS_ERR(fixed)) + return PTR_ERR(fixed); + + ret =3D of_clk_add_hw_provider(np, of_clk_hw_simple_get, fixed); + if (ret) + return ret; + + /* + * Roll a devm action because the clock provider is the child node, but + * the child node is not actually a device. + */ + return devm_add_action_or_reset(dev, qmp_clk_release_provider, np); +} + #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy= /qualcomm/phy-qcom-qmp-pcie-msm8996.c index a7c65cfe31dfb80d8b1058d3c519a324a309d1c2..226d893c198bdce0ecd3d7d31ed= 65199fc360ecf 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -579,66 +579,6 @@ static int qmp_pcie_msm8996_clk_init(struct device *de= v, const struct qmp_phy_cf return devm_clk_bulk_get(dev, num, qmp->clks); } =20 -static void phy_clk_release_provider(void *res) -{ - of_clk_del_provider(res); -} - -/* - * Register a fixed rate pipe clock. - * - * The _pipe_clksrc generated by PHY goes to the GCC that gate - * controls it. The _pipe_clk coming out of the GCC is requested - * by the PHY driver for its operations. - * We register the _pipe_clksrc here. The gcc driver takes care - * of assigning this _pipe_clksrc as parent to _pipe_clk. - * Below picture shows this relationship. - * - * +---------------+ - * | PHY block |<<---------------------------------------+ - * | | | - * | +-------+ | +-----+ | - * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ - * clk | +-------+ | +-----+ - * +---------------+ - */ -static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node = *np) -{ - struct clk_fixed_rate *fixed; - struct clk_init_data init =3D { }; - int ret; - - ret =3D of_property_read_string(np, "clock-output-names", &init.name); - if (ret) { - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); - return ret; - } - - fixed =3D devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); - if (!fixed) - return -ENOMEM; - - init.ops =3D &clk_fixed_rate_ops; - - /* controllers using QMP phys use 125MHz pipe clock interface */ - fixed->fixed_rate =3D 125000000; - fixed->hw.init =3D &init; - - ret =3D devm_clk_hw_register(qmp->dev, &fixed->hw); - if (ret) - return ret; - - ret =3D of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); - if (ret) - return ret; - - /* - * Roll a devm action because the clock provider is the child node, but - * the child node is not actually a device. - */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); -} - static const struct phy_ops qmp_pcie_msm8996_ops =3D { .power_on =3D qmp_pcie_msm8996_enable, .power_off =3D qmp_pcie_msm8996_disable, @@ -785,7 +725,7 @@ static int qmp_pcie_msm8996_probe(struct platform_devic= e *pdev) * Register the pipe clock provided by phy. * See function description to see details of this pipe clock. */ - ret =3D phy_pipe_clk_register(qmp, child); + ret =3D devm_qmp_register_pipe_clock_provider(dev, child); if (ret) { dev_err(qmp->dev, "failed to register pipe clock source\n"); diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 62b1c845b6275d924fa501ac64e69db5f58844aa..dad44cc0648355fc1533c9afd17= 6b7d37cfa9018 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3172,7 +3172,7 @@ struct qmp_pcie { struct phy *phy; int mode; =20 - struct clk_fixed_rate pipe_clk_fixed; + struct clk_hw *pipe_clk_hw; struct clk_fixed_rate aux_clk_fixed; }; =20 @@ -4789,57 +4789,6 @@ static int qmp_pcie_clk_init(struct qmp_pcie *qmp) return devm_clk_bulk_get_optional(dev, num, qmp->clks); } =20 -static void phy_clk_release_provider(void *res) -{ - of_clk_del_provider(res); -} - -/* - * Register a fixed rate pipe clock. - * - * The _pipe_clksrc generated by PHY goes to the GCC that gate - * controls it. The _pipe_clk coming out of the GCC is requested - * by the PHY driver for its operations. - * We register the _pipe_clksrc here. The gcc driver takes care - * of assigning this _pipe_clksrc as parent to _pipe_clk. - * Below picture shows this relationship. - * - * +---------------+ - * | PHY block |<<---------------------------------------+ - * | | | - * | +-------+ | +-----+ | - * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ - * clk | +-------+ | +-----+ - * +---------------+ - */ -static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node = *np) -{ - struct clk_fixed_rate *fixed =3D &qmp->pipe_clk_fixed; - struct clk_init_data init =3D { }; - int ret; - - ret =3D of_property_read_string_index(np, "clock-output-names", 0, &init.= name); - if (ret) { - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); - return ret; - } - - init.ops =3D &clk_fixed_rate_ops; - - /* - * Controllers using QMP PHY-s use 125MHz pipe clock interface - * unless other frequency is specified in the PHY config. - */ - if (qmp->cfg->pipe_clock_rate) - fixed->fixed_rate =3D qmp->cfg->pipe_clock_rate; - else - fixed->fixed_rate =3D 125000000; - - fixed->hw.init =3D &init; - - return devm_clk_hw_register(qmp->dev, &fixed->hw); -} - /* * Register a fixed rate PHY aux clock. * @@ -4881,11 +4830,11 @@ static struct clk_hw *qmp_pcie_clk_hw_get(struct of= _phandle_args *clkspec, void =20 /* Support legacy bindings */ if (!clkspec->args_count) - return &qmp->pipe_clk_fixed.hw; + return qmp->pipe_clk_hw; =20 switch (clkspec->args[0]) { case QMP_PCIE_PIPE_CLK: - return &qmp->pipe_clk_fixed.hw; + return qmp->pipe_clk_hw; case QMP_PCIE_PHY_AUX_CLK: return &qmp->aux_clk_fixed.hw; } @@ -4897,9 +4846,9 @@ static int qmp_pcie_register_clocks(struct qmp_pcie *= qmp, struct device_node *np { int ret; =20 - ret =3D phy_pipe_clk_register(qmp, np); - if (ret) - return ret; + qmp->pipe_clk_hw =3D devm_qmp_register_pipe_clock(qmp->dev, np); + if (IS_ERR(qmp->pipe_clk_hw)) + return PTR_ERR(qmp->pipe_clk_hw); =20 if (qmp->cfg->aux_clock_rate) { ret =3D phy_aux_clk_register(qmp, np); @@ -4910,7 +4859,7 @@ static int qmp_pcie_register_clocks(struct qmp_pcie *= qmp, struct device_node *np if (ret) return ret; } else { - ret =3D of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_= fixed.hw); + ret =3D of_clk_add_hw_provider(np, of_clk_hw_simple_get, qmp->pipe_clk_h= w); if (ret) return ret; } @@ -4919,7 +4868,7 @@ static int qmp_pcie_register_clocks(struct qmp_pcie *= qmp, struct device_node *np * Roll a devm action because the clock provider is the child node, but * the child node is not actually a device. */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); + return devm_add_action_or_reset(qmp->dev, qmp_clk_release_provider, np); } =20 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_no= de *np) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c b/drivers/phy/q= ualcomm/phy-qcom-qmp-usb-legacy.c index ddb52c1812dd02e15a840deee934c849405c2a98..0e775671054ed02024d01e3a11c= 6d3e2f973a097 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c @@ -521,8 +521,6 @@ struct qmp_usb { enum phy_mode mode; =20 struct phy *phy; - - struct clk_fixed_rate pipe_clk_fixed; }; =20 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -1043,62 +1041,6 @@ static int qmp_usb_legacy_clk_init(struct qmp_usb *q= mp) return devm_clk_bulk_get(dev, num, qmp->clks); } =20 -static void phy_clk_release_provider(void *res) -{ - of_clk_del_provider(res); -} - -/* - * Register a fixed rate pipe clock. - * - * The _pipe_clksrc generated by PHY goes to the GCC that gate - * controls it. The _pipe_clk coming out of the GCC is requested - * by the PHY driver for its operations. - * We register the _pipe_clksrc here. The gcc driver takes care - * of assigning this _pipe_clksrc as parent to _pipe_clk. - * Below picture shows this relationship. - * - * +---------------+ - * | PHY block |<<---------------------------------------+ - * | | | - * | +-------+ | +-----+ | - * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ - * clk | +-------+ | +-----+ - * +---------------+ - */ -static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *= np) -{ - struct clk_fixed_rate *fixed =3D &qmp->pipe_clk_fixed; - struct clk_init_data init =3D { }; - int ret; - - ret =3D of_property_read_string(np, "clock-output-names", &init.name); - if (ret) { - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); - return ret; - } - - init.ops =3D &clk_fixed_rate_ops; - - /* controllers using QMP phys use 125MHz pipe clock interface */ - fixed->fixed_rate =3D 125000000; - fixed->hw.init =3D &init; - - ret =3D devm_clk_hw_register(qmp->dev, &fixed->hw); - if (ret) - return ret; - - ret =3D of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); - if (ret) - return ret; - - /* - * Roll a devm action because the clock provider is the child node, but - * the child node is not actually a device. - */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); -} - static int qmp_usb_legacy_parse_dt_legacy(struct qmp_usb *qmp, struct devi= ce_node *np) { struct platform_device *pdev =3D to_platform_device(qmp->dev); @@ -1239,7 +1181,7 @@ static int qmp_usb_legacy_probe(struct platform_devic= e *pdev) */ pm_runtime_forbid(dev); =20 - ret =3D phy_pipe_clk_register(qmp, np); + ret =3D devm_qmp_register_pipe_clock_provider(dev, np); if (ret) goto err_node_put; =20 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm= /phy-qcom-qmp-usb.c index ed646a7e705ba3259708775ed5fedbbbada13735..7040b53e482d667f90eef09e3c4= a93cb6c01f934 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -1301,8 +1301,6 @@ struct qmp_usb { enum phy_mode mode; =20 struct phy *phy; - - struct clk_fixed_rate pipe_clk_fixed; }; =20 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -2046,62 +2044,6 @@ static int qmp_usb_clk_init(struct qmp_usb *qmp) return devm_clk_bulk_get_optional(dev, num, qmp->clks); } =20 -static void phy_clk_release_provider(void *res) -{ - of_clk_del_provider(res); -} - -/* - * Register a fixed rate pipe clock. - * - * The _pipe_clksrc generated by PHY goes to the GCC that gate - * controls it. The _pipe_clk coming out of the GCC is requested - * by the PHY driver for its operations. - * We register the _pipe_clksrc here. The gcc driver takes care - * of assigning this _pipe_clksrc as parent to _pipe_clk. - * Below picture shows this relationship. - * - * +---------------+ - * | PHY block |<<---------------------------------------+ - * | | | - * | +-------+ | +-----+ | - * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ - * clk | +-------+ | +-----+ - * +---------------+ - */ -static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *= np) -{ - struct clk_fixed_rate *fixed =3D &qmp->pipe_clk_fixed; - struct clk_init_data init =3D { }; - int ret; - - ret =3D of_property_read_string(np, "clock-output-names", &init.name); - if (ret) { - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); - return ret; - } - - init.ops =3D &clk_fixed_rate_ops; - - /* controllers using QMP phys use 125MHz pipe clock interface */ - fixed->fixed_rate =3D 125000000; - fixed->hw.init =3D &init; - - ret =3D devm_clk_hw_register(qmp->dev, &fixed->hw); - if (ret) - return ret; - - ret =3D of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); - if (ret) - return ret; - - /* - * Roll a devm action because the clock provider is the child node, but - * the child node is not actually a device. - */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); -} - static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node = *np, int index, bool exclusive) { @@ -2276,7 +2218,7 @@ static int qmp_usb_probe(struct platform_device *pdev) */ pm_runtime_forbid(dev); =20 - ret =3D phy_pipe_clk_register(qmp, np); + ret =3D devm_qmp_register_pipe_clock_provider(dev, np); if (ret) goto err_node_put; =20 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 5e7fcb26744a4401c3076960df9c0dcbec7fdef7..83f3011a93c0cd53f59a1a45406= bf4d9107e7ea9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -347,8 +347,6 @@ struct qmp_usbc { =20 struct phy *phy; =20 - struct clk_fixed_rate pipe_clk_fixed; - struct typec_switch_dev *sw; enum typec_orientation orientation; }; @@ -796,62 +794,6 @@ static int qmp_usbc_clk_init(struct qmp_usbc *qmp) return devm_clk_bulk_get_optional(dev, num, qmp->clks); } =20 -static void phy_clk_release_provider(void *res) -{ - of_clk_del_provider(res); -} - -/* - * Register a fixed rate pipe clock. - * - * The _pipe_clksrc generated by PHY goes to the GCC that gate - * controls it. The _pipe_clk coming out of the GCC is requested - * by the PHY driver for its operations. - * We register the _pipe_clksrc here. The gcc driver takes care - * of assigning this _pipe_clksrc as parent to _pipe_clk. - * Below picture shows this relationship. - * - * +---------------+ - * | PHY block |<<---------------------------------------+ - * | | | - * | +-------+ | +-----+ | - * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ - * clk | +-------+ | +-----+ - * +---------------+ - */ -static int phy_pipe_clk_register(struct qmp_usbc *qmp, struct device_node = *np) -{ - struct clk_fixed_rate *fixed =3D &qmp->pipe_clk_fixed; - struct clk_init_data init =3D { }; - int ret; - - ret =3D of_property_read_string(np, "clock-output-names", &init.name); - if (ret) { - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); - return ret; - } - - init.ops =3D &clk_fixed_rate_ops; - - /* controllers using QMP phys use 125MHz pipe clock interface */ - fixed->fixed_rate =3D 125000000; - fixed->hw.init =3D &init; - - ret =3D devm_clk_hw_register(qmp->dev, &fixed->hw); - if (ret) - return ret; - - ret =3D of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); - if (ret) - return ret; - - /* - * Roll a devm action because the clock provider is the child node, but - * the child node is not actually a device. - */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); -} - #if IS_ENABLED(CONFIG_TYPEC) static int qmp_usbc_typec_switch_set(struct typec_switch_dev *sw, enum typec_orientation orientation) @@ -1093,7 +1035,7 @@ static int qmp_usbc_probe(struct platform_device *pde= v) */ pm_runtime_forbid(dev); =20 - ret =3D phy_pipe_clk_register(qmp, np); + ret =3D devm_qmp_register_pipe_clock_provider(dev, np); if (ret) goto err_node_put; =20 --=20 2.47.3