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charset="utf-8" In particular, to pull in a SP_READ_SEL_LOCATION bitfield size fix to fix a7xx GPU snapshot. Sync from mesa commit 76fece61c6ff ("freedreno/registers: Add A7XX_CX_DBGC") Cc: Karmjit Mahil Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 10 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 19 +- drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 5 +- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 718 ++++++++++-------- .../msm/registers/adreno/a6xx_descriptors.xml | 40 - .../drm/msm/registers/adreno/a6xx_enums.xml | 50 +- .../drm/msm/registers/adreno/adreno_pm4.xml | 179 ++--- 7 files changed, 524 insertions(+), 497 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index d8d1ba379c9b..e54cdb9399f7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1345,11 +1345,11 @@ DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist); =20 /* Applicable for X185, A750 */ static const u32 a750_ifpc_reglist_regs[] =3D { - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, - REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), REG_A6XX_TPL1_NC_MODE_CNTL, REG_A6XX_SP_NC_MODE_CNTL, REG_A6XX_CP_DBG_ECO_CNTL, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 2e2090f52e26..3f5c4bcf32cc 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -247,8 +247,8 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gp= u, * Needed for preemption */ OUT_PKT7(ring, CP_MEM_WRITE, 5); - OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); - OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); + OUT_RING(ring, lower_32_bits(memptr)); + OUT_RING(ring, upper_32_bits(memptr)); OUT_RING(ring, lower_32_bits(ttbr)); OUT_RING(ring, upper_32_bits(ttbr)); OUT_RING(ring, ctx->seqno); @@ -278,9 +278,8 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gp= u, */ OUT_PKT7(ring, CP_WAIT_REG_MEM, 6); OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ)); - OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO( - REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS)); - OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0)); + OUT_RING(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS); + OUT_RING(ring, 0); OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); @@ -1320,14 +1319,14 @@ static int hw_init(struct msm_gpu *gpu) =20 /* Set weights for bicubic filtering */ if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 0); + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), 0x3fe05ff4); - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), 0x3fa0ebee); - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), 0x3f5193ed); - gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, + gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), 0x3f0243f0); } =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/ms= m/adreno/a6xx_preempt.c index 796be5cd5cc0..585fc1b772e1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c @@ -111,9 +111,8 @@ static void preempt_prepare_postamble(struct a6xx_gpu *= a6xx_gpu) =20 postamble[count++] =3D PKT7(CP_WAIT_REG_MEM, 6); postamble[count++] =3D CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ); - postamble[count++] =3D CP_WAIT_REG_MEM_1_POLL_ADDR_LO( - REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS); - postamble[count++] =3D CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0); + postamble[count++] =3D REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS; + postamble[count++] =3D 0; postamble[count++] =3D CP_WAIT_REG_MEM_3_REF(0x1); postamble[count++] =3D CP_WAIT_REG_MEM_4_MASK(0x1); postamble[count++] =3D CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0); diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/dr= m/msm/registers/adreno/a6xx.xml index 86fab2750ba7..9459b6038217 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -814,7 +814,7 @@ by a particular renderpass/blit. =20 - + @@ -826,18 +826,20 @@ by a particular renderpass/blit. - + + + =20 - - - - + + + + =20 - + @@ -848,26 +850,69 @@ by a particular renderpass/blit. - - + + + + + - + + + =20 =20 - + + + + + + + + + + + + + + + + + + + + + =20 - - - - + + + + + + + + + + + + + + + + + + + + + + =20 =20 - + @@ -875,12 +920,13 @@ by a particular renderpass/blit. - + + =20 - + @@ -890,39 +936,66 @@ by a particular renderpass/blit. - - - - - + + + + + + + - - + + + + + + + + + + + + + + + + + + + + + + + - + - - - - - - + + + + + + + - + =20 - + + + + @@ -932,7 +1005,10 @@ by a particular renderpass/blit. - + + + + @@ -942,10 +1018,13 @@ by a particular renderpass/blit. - - - - + + + + + + + =20 @@ -993,7 +1072,7 @@ by a particular renderpass/blit. =20 - + @@ -1003,7 +1082,9 @@ by a particular renderpass/blit. - + + + =20 @@ -1024,7 +1105,7 @@ by a particular renderpass/blit. =20 - + @@ -1037,18 +1118,25 @@ by a particular renderpass/blit. In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. - - + + + + =20 - + - - + + + + + - + + + =20 @@ -1066,30 +1154,35 @@ by a particular renderpass/blit. =20 - - - + + + =20 - + =20 - - + + + + + =20 - + + - + + =20 - - + + =20 @@ -1099,7 +1192,7 @@ by a particular renderpass/blit. =20 - + @@ -1107,20 +1200,32 @@ by a particular renderpass/blit. - - + + + + + - - + + + + + - - - + + + + + + + - + + + =20 @@ -1128,7 +1233,7 @@ by a particular renderpass/blit. =20 - + LRZ write also disabled for blend/etc. @@ -1155,26 +1260,36 @@ by a particular renderpass/blit. - + + + =20 =20 - + - + + + =20 - + - - - + + + + + + + - + + + =20 - @@ -1232,19 +1346,20 @@ by a particular renderpass/blit. =20 =20 - + =20 - + =20 - + - + + + =20 - - - + LUT used to convert quality buffer values to HW shading rate values.= An array of 4-bit values. + =20 =20 @@ -1269,28 +1384,29 @@ by a particular renderpass/blit. - + + + - + =20 - + - - - - - - + + + + + + - - - + + =20 @@ -1308,22 +1424,7 @@ by a particular renderpass/blit. --> =20 - - - - - - - - - - - - - - - - + =20 @@ -1347,9 +1448,6 @@ by a particular renderpass/blit. - - - =20 @@ -1516,9 +1614,7 @@ by a particular renderpass/blit. - - - + =20 @@ -1532,14 +1628,9 @@ by a particular renderpass/blit. - - - + - - - - + @@ -1575,9 +1666,7 @@ by a particular renderpass/blit. - - - + @@ -1616,8 +1705,9 @@ by a particular renderpass/blit. - - + + + @@ -1626,7 +1716,7 @@ by a particular renderpass/blit. - + @@ -1650,10 +1740,13 @@ by a particular renderpass/blit. - + + - - + + + + =20 @@ -1726,10 +1819,7 @@ by a particular renderpass/blit. - - - - + =20 @@ -1737,8 +1827,9 @@ by a particular renderpass/blit. - - + + + @@ -1747,12 +1838,10 @@ by a particular renderpass/blit. + - - - - + @@ -1815,7 +1904,7 @@ by a particular renderpass/blit. =20 - + @@ -1921,13 +2010,13 @@ by a particular renderpass/blit. - - - + + + =20 - - - + + + =20 @@ -1935,23 +2024,33 @@ by a particular renderpass/blit. =20 - - - + + + + =20 - - - + + + + + + + + + + + + + + =20 - - - =20 + @@ -1991,10 +2090,10 @@ by a particular renderpass/blit. =20 - - - - + + + + =20 @@ -2011,11 +2110,11 @@ by a particular renderpass/blit. =20 - + Packed array of a6xx_varying_interp_mode - + Packed array of a6xx_varying_ps_repl_mode @@ -2024,12 +2123,12 @@ by a particular renderpass/blit. =20 - + =20 - + - - - + + + + + - + + + + =20 - + =20 - + @@ -2077,12 +2181,13 @@ by a particular renderpass/blit. =20 - + - - - - + + + + + =20 @@ -2101,11 +2206,12 @@ by a particular renderpass/blit. - - - =20 - + + + + + @@ -2122,9 +2228,11 @@ by a particular renderpass/blit. ViewID through the VS. - + =20 - + + + @@ -2133,22 +2241,28 @@ by a particular renderpass/blit. - - + + + + + - - - - - - - - - - - - - + + + + + + + + + + + + + + + + =20 =20 @@ -2163,52 +2277,62 @@ by a particular renderpass/blit. =20 - + =20 - - + - + + + =20 - + - + + + + + =20 - - + =20 =20 - + - + =20 - - + + + - + + + + =20 - + - - + + + =20 - + - + =20 - - - + + =20 - + - + + + =20 =20 - - - - - - - - - - - - - - - - - - - - - - - - - - + + =20 - + - + =20 =20 - + =20 @@ -2270,18 +2370,18 @@ by a particular renderpass/blit. + =20 - - - - - + + + + =20 - + =20 @@ -2290,9 +2390,9 @@ by a particular renderpass/blit. =20 - + - + @@ -2303,34 +2403,39 @@ by a particular renderpass/blit. - - - + + + + - + =20 - + Possibly not really "initiating" the draw but the layout is similar to VGT_DRAW_INITIATOR on older gens - - + + =20 - + =20 @@ -3104,14 +3209,19 @@ by a particular renderpass/blit. instructions VS/HS/DS/GS/FS. See SP_CS_UAV_BASE_* for compute shaders. --> - + =20 - + + + + + + + =20 - - - + + @@ -3156,7 +3266,7 @@ by a particular renderpass/blit. - + @@ -3192,7 +3302,7 @@ by a particular renderpass/blit. =20 - + @@ -3232,12 +3342,12 @@ by a particular renderpass/blit. =20 - + - + @@ -3296,17 +3406,13 @@ by a particular renderpass/blit. diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml b/dr= ivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml index 307d43dda8a2..56cfaff614a4 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml @@ -9,38 +9,6 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/freed= reno/ rules-fd.xsd"> =20 Texture sampler dwords - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =20 @@ -79,14 +47,6 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fre= edreno/ rules-fd.xsd"> =20 Texture constant dwords - - - - - - - - diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml b/drivers/= gpu/drm/msm/registers/adreno/a6xx_enums.xml index 665539b098c6..4e42f055b85f 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml @@ -320,14 +320,14 @@ to upconvert to 32b float internally? 16b float: 3 --> - + - + =20 @@ -380,4 +380,50 @@ to upconvert to 32b float internally? =20 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml b/drivers/= gpu/drm/msm/registers/adreno/adreno_pm4.xml index 7abc08635495..0e10e1c6d263 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml @@ -120,12 +120,12 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> - + - - + + =20 @@ -523,7 +523,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> @@ -640,8 +640,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> Clears, adds to local, or adds to global timestamp - - + Write to a scratch memory that is read by CP_REG_TEST with SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers. @@ -918,12 +917,6 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) =20 - - - - - - @@ -1099,8 +1092,10 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + + + @@ -1166,26 +1161,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - - - - + - - - - - - + - - - - - - + @@ -1195,26 +1175,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - - - - + - - - - - - + - - - - - - + @@ -1300,7 +1265,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) =20 - + @@ -1308,12 +1273,12 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - - - - + + + + + + =20 @@ -1329,12 +1294,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - - - - + @@ -1354,18 +1314,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - - - - - - - - - - + + =20 @@ -1378,12 +1328,12 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - - - - + + + + + + =20 @@ -1403,6 +1353,10 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) + + + + =20 @@ -1518,24 +1472,14 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - - - - + - - - - - - + @@ -1550,12 +1494,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - - - - + @@ -1573,12 +1512,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - - - - + @@ -1712,12 +1646,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) TODO what is gpuaddr for, seems to be all 0's.. maybe needed for context switch? --> - - - - - - + @@ -1832,9 +1761,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - + @@ -1843,12 +1770,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - - - - + @@ -2161,12 +2083,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - - - - - + --=20 2.51.0