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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5608ace9c65sm2357467e87.85.2025.09.06.06.54.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Sep 2025 06:54:03 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , =?UTF-8?q?Jonas=20Schw=C3=B6bel?= , Charan Pedumuru Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v2 01/23] clk: tegra: set CSUS as vi_sensors gate for Tegra20, Tegra30 and Tegra114 Date: Sat, 6 Sep 2025 16:53:22 +0300 Message-ID: <20250906135345.241229-2-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250906135345.241229-1-clamor95@gmail.com> References: <20250906135345.241229-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" CSUS clock which is camera MCLK, is also a clock gate for vi_sensor so lets model it by creating CSUS grate with vi_sensor as a parent. Signed-off-by: Svyatoslav Ryhel --- drivers/clk/tegra/clk-tegra114.c | 7 ++++++- drivers/clk/tegra/clk-tegra20.c | 7 ++++++- drivers/clk/tegra/clk-tegra30.c | 7 ++++++- 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra= 114.c index 186b0b81c1ec..00282b0d3763 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -691,7 +691,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __= initdata =3D { [tegra_clk_tsec] =3D { .dt_id =3D TEGRA114_CLK_TSEC, .present =3D true }, [tegra_clk_xusb_host] =3D { .dt_id =3D TEGRA114_CLK_XUSB_HOST, .present = =3D true }, [tegra_clk_msenc] =3D { .dt_id =3D TEGRA114_CLK_MSENC, .present =3D true = }, - [tegra_clk_csus] =3D { .dt_id =3D TEGRA114_CLK_CSUS, .present =3D true }, [tegra_clk_mselect] =3D { .dt_id =3D TEGRA114_CLK_MSELECT, .present =3D t= rue }, [tegra_clk_tsensor] =3D { .dt_id =3D TEGRA114_CLK_TSENSOR, .present =3D t= rue }, [tegra_clk_i2s3] =3D { .dt_id =3D TEGRA114_CLK_I2S3, .present =3D true }, @@ -1047,6 +1046,12 @@ static __init void tegra114_periph_clk_init(void __i= omem *clk_base, 0, 82, periph_clk_enb_refcnt); clks[TEGRA114_CLK_DSIB] =3D clk; =20 + /* csus */ + clk =3D tegra_clk_register_periph_gate("csus", "vi_sensor", 0, + clk_base, 0, TEGRA114_CLK_CSUS, + periph_clk_enb_refcnt); + clks[TEGRA114_CLK_CSUS] =3D clk; + /* emc mux */ clk =3D clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, ARRAY_SIZE(mux_pllmcp_clkm), diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra2= 0.c index 2c58ce25af75..bf9a9f8ddf62 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -530,7 +530,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __i= nitdata =3D { [tegra_clk_rtc] =3D { .dt_id =3D TEGRA20_CLK_RTC, .present =3D true }, [tegra_clk_timer] =3D { .dt_id =3D TEGRA20_CLK_TIMER, .present =3D true }, [tegra_clk_kbc] =3D { .dt_id =3D TEGRA20_CLK_KBC, .present =3D true }, - [tegra_clk_csus] =3D { .dt_id =3D TEGRA20_CLK_CSUS, .present =3D true }, [tegra_clk_vcp] =3D { .dt_id =3D TEGRA20_CLK_VCP, .present =3D true }, [tegra_clk_bsea] =3D { .dt_id =3D TEGRA20_CLK_BSEA, .present =3D true }, [tegra_clk_bsev] =3D { .dt_id =3D TEGRA20_CLK_BSEV, .present =3D true }, @@ -807,6 +806,12 @@ static void __init tegra20_periph_clk_init(void) clk_register_clkdev(clk, NULL, "dsi"); clks[TEGRA20_CLK_DSI] =3D clk; =20 + /* csus */ + clk =3D tegra_clk_register_periph_gate("csus", "vi_sensor", 0, + clk_base, 0, TEGRA20_CLK_CSUS, + periph_clk_enb_refcnt); + clks[TEGRA20_CLK_CSUS] =3D clk; + /* pex */ clk =3D tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, periph_clk_enb_refcnt); diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra3= 0.c index 82a8cb9545eb..ca367184e185 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -779,7 +779,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __i= nitdata =3D { [tegra_clk_rtc] =3D { .dt_id =3D TEGRA30_CLK_RTC, .present =3D true }, [tegra_clk_timer] =3D { .dt_id =3D TEGRA30_CLK_TIMER, .present =3D true }, [tegra_clk_kbc] =3D { .dt_id =3D TEGRA30_CLK_KBC, .present =3D true }, - [tegra_clk_csus] =3D { .dt_id =3D TEGRA30_CLK_CSUS, .present =3D true }, [tegra_clk_vcp] =3D { .dt_id =3D TEGRA30_CLK_VCP, .present =3D true }, [tegra_clk_bsea] =3D { .dt_id =3D TEGRA30_CLK_BSEA, .present =3D true }, [tegra_clk_bsev] =3D { .dt_id =3D TEGRA30_CLK_BSEV, .present =3D true }, @@ -1008,6 +1007,12 @@ static void __init tegra30_periph_clk_init(void) 0, 48, periph_clk_enb_refcnt); clks[TEGRA30_CLK_DSIA] =3D clk; =20 + /* csus */ + clk =3D tegra_clk_register_periph_gate("csus", "vi_sensor", 0, + clk_base, 0, TEGRA30_CLK_CSUS, + periph_clk_enb_refcnt); + clks[TEGRA30_CLK_CSUS] =3D clk; + /* pcie */ clk =3D tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 70, periph_clk_enb_refcnt); --=20 2.48.1