From nobody Tue Sep 9 11:41:16 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E79F02F0689; Sat, 6 Sep 2025 13:53:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757166800; cv=none; b=ZtvLhzzanIoqiDhN8aRLNKrYsLKAjnLBvnIlMVqdL5xOiD/xDN2gNn6YUh67pdVD/ygWIT5bU7sEVcuBUPpTzP72JUt4RINn+epb8yVMjnldugijRbz4hpr+3zdbpQ9BUBzInNVaLKo9ZD+/79X19X0pQY7P+NDkwsCbV6g08o8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757166800; c=relaxed/simple; bh=HWREdHG3YnglsO1xpZ5cZDYeUf4qqnVsw5wTGJIyxYE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WttvQk4RlYaJW6a/Ra6pi2hLi8zWRiup4EsPgH0tuF/wK3Rnv2ynnLjFcoYj7y4m4We6mHUznErH0KsqkWDNdId14kRSR9Bt8pX4g/HdcIn/ZAAyNxX/dWBvMJjJjPxSs5ipqwtyIP0lCHlnRGRoScwqyAfmQqdsTFNKksP3SdY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=lPB73zZ5; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="lPB73zZ5" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 32B362072F; Sat, 6 Sep 2025 15:53:17 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 9acWT6tHLmOh; Sat, 6 Sep 2025 15:53:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1757166796; bh=HWREdHG3YnglsO1xpZ5cZDYeUf4qqnVsw5wTGJIyxYE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=lPB73zZ5HFQWeRVaZeab0F1DPNpkih931WxzhVIy40gnwElxXZQ524OtcdKGilkh9 uJna4epMkzb7jPnrX3yLAJHV30XxyolC31E8i+T5x1UgiVoFXzP4Tfx+yQSEmRyQaa aVGpkii+XkWLAIXoIbdULfL3HQCw0UW9fd6fOD3f3up36vTRVoof8rD5BohgeaBuEL SydcSii9yNOMhZNUfn5FuRVj5GGADMFI5D7I5L3Uxodijz911OlBfqN/i3yscj8B4V 7600XjmFUBN4m5NQeVMdb+KZILQzDmfPcQ+l1CiaKawEz0uLk5iXnLi0rZLxDLzxmI EG/lN8ueuKo1A== From: Yao Zi To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jonas Karlman , Chukun Pan , Yao Zi Subject: [PATCH 2/3] arm64: dts: rockchip: Add PCIe Gen2x1 controller for RK3528 Date: Sat, 6 Sep 2025 13:52:45 +0000 Message-ID: <20250906135246.19398-3-ziyao@disroot.org> In-Reply-To: <20250906135246.19398-1-ziyao@disroot.org> References: <20250906135246.19398-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describes the PCIe Gen2x1 controller integrated in RK3528 SoC. The SoC doesn't provide a separate MSI controller, thus the one integrated in designware PCIe IP must be used. Signed-off-by: Yao Zi --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 56 +++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts= /rockchip/rk3528.dtsi index db5dbcac7756..2d2af467e5ab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -239,7 +240,7 @@ gmac0_clk: clock-gmac50m { =20 soc { compatible =3D "simple-bus"; - ranges =3D <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; + ranges =3D <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44400000>; #address-cells =3D <2>; #size-cells =3D <2>; =20 @@ -1133,6 +1134,59 @@ combphy: phy@ffdc0000 { rockchip,pipe-phy-grf =3D <&pipe_phy_grf>; status =3D "disabled"; }; + + pcie: pcie@fe4f0000 { + compatible =3D "rockchip,rk3528-pcie", + "rockchip,rk3568-pcie"; + reg =3D <0x1 0x40000000 0x0 0x400000>, + <0x0 0xfe4f0000 0x0 0x10000>, + <0x0 0xfc000000 0x0 0x100000>; + reg-names =3D "dbi", "apb", "config"; + bus-range =3D <0x0 0xff>; + clocks =3D <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>, + <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>, + <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE_PHY>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err", + "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + linux,pci-domain =3D <0>; + max-link-speed =3D <2>; + num-lanes =3D <1>; + phys =3D <&combphy PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3528_PD_VPU>; + ranges =3D <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000>, + <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000>, + <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>; + resets =3D <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>; + reset-names =3D "pwr", "pipe"; + #address-cells =3D <3>; + #size-cells =3D <2>; + status =3D "disabled"; + + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + interrupt-parent =3D <&gic>; + interrupts =3D ; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; }; }; =20 --=20 2.50.1