From nobody Tue Sep 9 05:50:29 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BFAE2F0C79; Sat, 6 Sep 2025 13:53:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757166794; cv=none; b=kvNtbeVXp5VfgVQG9kQzDFYhNVr/FgHSjb2Td3i6EEl0e0tgH+2KLYAJljRvUpezFk4e0MYs5ENeDT88yr6GQTyf9ObrgjawrhEn1fR99Fc4VKeUEdq6duD4Prx9+6UNh+KaZumc+95D0m0M5lPDv8kmzE49wVUdLvmWyzynp+I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757166794; c=relaxed/simple; bh=QsGy+bBU+9Umuk9tcBxgAcdBm7R9LKoAcjgjg3FRuWQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ft8z9o2NDNr9EXiNZqi8uYVJPl2NbTVYy8B2lCyC1uyEi83NWlbuzZLpHG1l/N0Ze8+XPTjkFASosePzDwxBDiqAmW8aQ44y36KBdp6G3ApgvjAnjVreUTk6qLMT1HbrK2NxvQEyWBBRIBmnSfyHkk87ilhaYtnXcDIo0JbhGjk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=UzK5gLBW; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="UzK5gLBW" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 87B2622C21; Sat, 6 Sep 2025 15:53:10 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id LJOJ-S12NzCP; Sat, 6 Sep 2025 15:53:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1757166789; bh=QsGy+bBU+9Umuk9tcBxgAcdBm7R9LKoAcjgjg3FRuWQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=UzK5gLBWNBPdd9zctSe6HF0agow0S4Irkj2epjEJqsqRj4003Fmpudn2OlKRQnyi8 sXmXz7a93HDo5An8XFbr0TunmzNsDxqiXbPsvWzj9rJX+6C2RB6PQvoRyZdAvvjFHp 2HWOwFLeP6UboKGnpxAZLObUGhnByw+pW0X98DL38OdLFEvXz4lQfoy9bmIebYaUZI Peq65SYdeX/rUOAJG/gY3XfDxRQ/UbfqOxZWacohCuQosftoA41YgUkPmvy43NGHZq 6hXDdV9q4g5kFrVFgbB7/6+nEAGCFuBWwPIRYqQYTLihNBJhJANUNKv9o6KDs8zxRJ lvsEEoof/L6nw== From: Yao Zi To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jonas Karlman , Chukun Pan , Yao Zi Subject: [PATCH 1/3] dt-bindings: PCI: dwc: rockchip: Add RK3528 variant Date: Sat, 6 Sep 2025 13:52:44 +0000 Message-ID: <20250906135246.19398-2-ziyao@disroot.org> In-Reply-To: <20250906135246.19398-1-ziyao@disroot.org> References: <20250906135246.19398-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RK3528 ships a PCIe Gen2x1 controller that operates in RC mode only. Since the SoC has no separate MSI controller, the one integrated in the DWC PCIe IP must be used, and thus its interrupt scheme is similar to variants found in RK3562 and RK3576. Older BSP code claimed its integrated MSI controller supports only 8 MSIs[1], but this has been changed in newer BSP[2] and testing proves the controller works correctly with more than 8 MSIs allocated, suggesting the controller should be compatible with the RK3568 variant. Let's document its compatible string. Link: https://github.com/rockchip-linux/kernel/blob/792a7d4273a5/drivers/pc= i/controller/dwc/pcie-dw-rockchip.c#L1610-L1613 # [1] Link: https://github.com/rockchip-linux/kernel/blob/1ba51b059f25/drivers/pc= i/controller/dwc/pcie-dw-rockchip.c#L904-L906 # [2] Signed-off-by: Yao Zi Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/= Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 6c6d828ce964..67f1a5502048 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -22,6 +22,7 @@ properties: - const: rockchip,rk3568-pcie - items: - enum: + - rockchip,rk3528-pcie - rockchip,rk3562-pcie - rockchip,rk3576-pcie - rockchip,rk3588-pcie @@ -78,6 +79,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3528-pcie - rockchip,rk3562-pcie - rockchip,rk3576-pcie then: @@ -89,6 +91,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3528-pcie - rockchip,rk3562-pcie - rockchip,rk3576-pcie then: --=20 2.50.1 From nobody Tue Sep 9 05:50:29 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E79F02F0689; Sat, 6 Sep 2025 13:53:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757166800; cv=none; b=ZtvLhzzanIoqiDhN8aRLNKrYsLKAjnLBvnIlMVqdL5xOiD/xDN2gNn6YUh67pdVD/ygWIT5bU7sEVcuBUPpTzP72JUt4RINn+epb8yVMjnldugijRbz4hpr+3zdbpQ9BUBzInNVaLKo9ZD+/79X19X0pQY7P+NDkwsCbV6g08o8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757166800; c=relaxed/simple; bh=HWREdHG3YnglsO1xpZ5cZDYeUf4qqnVsw5wTGJIyxYE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WttvQk4RlYaJW6a/Ra6pi2hLi8zWRiup4EsPgH0tuF/wK3Rnv2ynnLjFcoYj7y4m4We6mHUznErH0KsqkWDNdId14kRSR9Bt8pX4g/HdcIn/ZAAyNxX/dWBvMJjJjPxSs5ipqwtyIP0lCHlnRGRoScwqyAfmQqdsTFNKksP3SdY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=lPB73zZ5; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="lPB73zZ5" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 32B362072F; Sat, 6 Sep 2025 15:53:17 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 9acWT6tHLmOh; Sat, 6 Sep 2025 15:53:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1757166796; bh=HWREdHG3YnglsO1xpZ5cZDYeUf4qqnVsw5wTGJIyxYE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=lPB73zZ5HFQWeRVaZeab0F1DPNpkih931WxzhVIy40gnwElxXZQ524OtcdKGilkh9 uJna4epMkzb7jPnrX3yLAJHV30XxyolC31E8i+T5x1UgiVoFXzP4Tfx+yQSEmRyQaa aVGpkii+XkWLAIXoIbdULfL3HQCw0UW9fd6fOD3f3up36vTRVoof8rD5BohgeaBuEL SydcSii9yNOMhZNUfn5FuRVj5GGADMFI5D7I5L3Uxodijz911OlBfqN/i3yscj8B4V 7600XjmFUBN4m5NQeVMdb+KZILQzDmfPcQ+l1CiaKawEz0uLk5iXnLi0rZLxDLzxmI EG/lN8ueuKo1A== From: Yao Zi To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jonas Karlman , Chukun Pan , Yao Zi Subject: [PATCH 2/3] arm64: dts: rockchip: Add PCIe Gen2x1 controller for RK3528 Date: Sat, 6 Sep 2025 13:52:45 +0000 Message-ID: <20250906135246.19398-3-ziyao@disroot.org> In-Reply-To: <20250906135246.19398-1-ziyao@disroot.org> References: <20250906135246.19398-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describes the PCIe Gen2x1 controller integrated in RK3528 SoC. The SoC doesn't provide a separate MSI controller, thus the one integrated in designware PCIe IP must be used. Signed-off-by: Yao Zi --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 56 +++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts= /rockchip/rk3528.dtsi index db5dbcac7756..2d2af467e5ab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -239,7 +240,7 @@ gmac0_clk: clock-gmac50m { =20 soc { compatible =3D "simple-bus"; - ranges =3D <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; + ranges =3D <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44400000>; #address-cells =3D <2>; #size-cells =3D <2>; =20 @@ -1133,6 +1134,59 @@ combphy: phy@ffdc0000 { rockchip,pipe-phy-grf =3D <&pipe_phy_grf>; status =3D "disabled"; }; + + pcie: pcie@fe4f0000 { + compatible =3D "rockchip,rk3528-pcie", + "rockchip,rk3568-pcie"; + reg =3D <0x1 0x40000000 0x0 0x400000>, + <0x0 0xfe4f0000 0x0 0x10000>, + <0x0 0xfc000000 0x0 0x100000>; + reg-names =3D "dbi", "apb", "config"; + bus-range =3D <0x0 0xff>; + clocks =3D <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>, + <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>, + <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE_PHY>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err", + "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + linux,pci-domain =3D <0>; + max-link-speed =3D <2>; + num-lanes =3D <1>; + phys =3D <&combphy PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3528_PD_VPU>; + ranges =3D <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000>, + <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000>, + <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>; + resets =3D <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>; + reset-names =3D "pwr", "pipe"; + #address-cells =3D <3>; + #size-cells =3D <2>; + status =3D "disabled"; + + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + interrupt-parent =3D <&gic>; + interrupts =3D ; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; }; }; =20 --=20 2.50.1 From nobody Tue Sep 9 05:50:29 2025 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 931172EE29F; Sat, 6 Sep 2025 13:54:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757166848; cv=none; b=Lhjr6Egn13X6eeNJiyqVOv0J6Kt0biupdBck8ub6kkqziQl/bfzcQFwNIARmbQjkGB2niYMtXb3mMOhEw7WzV0rK94JJhasWggtNBMnYVnx1HX4gOsyQo0fUwTvdm8aeDGcGCbI0vOqLA4x5n6gH5tvXa47y2z8kfUvvspdzMS0= ARC-Message-Signature: i=1; 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Sat, 6 Sep 2025 15:54:05 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 15xGSrIbygqB; Sat, 6 Sep 2025 15:54:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1757166844; bh=Dw5uo181Dm3Fr9E03p865uWj8jVKOwAN1D+SIhGoS3E=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=QnenhXeTVnAZ4hc1cPKPDtuClk2YEMAQ1CvdjE8PRoj4rTwwfuAekElrTBr7hQSgB N7IvFyxXZ34NEK28AsfeUGPCS0Oqsudvn3qk7kPn8TGAgNI+IJgPITbWXXnKXe3qso Zc35meOMW+qDjq4diZXyxFRBSk9bgCZyZ9It6mwk5G6qgvILI2F+58bJ70+sKAuUon dnIfrXCdRUVWoa3Kc7raD2OP716eQrQLe8uSes1OZIP9KDhq9b1QszVP4VmnEY9/nL yGstc9ZF08io+5dtjwoQr/FUt2mRNqNjW6CLLXu71fEkiltKNK7Umc7qK19o6bEvce PuVkMK5WfjdwQ== From: Yao Zi To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jonas Karlman , Chukun Pan , Yao Zi Subject: [PATCH 3/3] arm64: dts: rockchip: Enable PCIe controller on Radxa E20C Date: Sat, 6 Sep 2025 13:52:46 +0000 Message-ID: <20250906135246.19398-4-ziyao@disroot.org> In-Reply-To: <20250906135246.19398-1-ziyao@disroot.org> References: <20250906135246.19398-1-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Radxa E20C provides one of its GbE ports through RTL8111H connected to SoC's PCIe controller. Let's enable the controller and the PHY used by it to allow usage of the port. Signed-off-by: Yao Zi --- .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm6= 4/boot/dts/rockchip/rk3528-radxa-e20c.dts index 12eec2c1db22..e880c7a7e674 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts @@ -171,6 +171,10 @@ vdd_logic: regulator-vdd-logic { }; }; =20 +&combphy { + status =3D "okay"; +}; + &cpu0 { cpu-supply =3D <&vdd_arm>; }; @@ -229,6 +233,13 @@ rgmii_phy: ethernet-phy@1 { }; }; =20 +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pciem1_pins>, <&pcie_reset_g>; + reset-gpios =3D <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + &pinctrl { ethernet { gmac1_rstn_l: gmac1-rstn-l { @@ -256,6 +267,12 @@ wan_led_g: wan-led-g { }; }; =20 + pcie { + pcie_reset_g: pcie-reset-g { + rockchip,pins =3D <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { rockchip,pins =3D <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; --=20 2.50.1