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([188.163.112.70]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5608ad44f8fsm2312647e87.137.2025.09.06.06.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Sep 2025 06:17:17 -0700 (PDT) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mikko Perttunen , David Airlie , Simona Vetter , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH v2 3/4] gpu/drm: tegra: dsi: add support for Tegra20/Tegra30 Date: Sat, 6 Sep 2025 16:16:54 +0300 Message-ID: <20250906131655.239340-4-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250906131655.239340-1-clamor95@gmail.com> References: <20250906131655.239340-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra20 and Tegra30 are fully compatible with existing tegra DSI driver apart from clock configuration and PAD calibration which are addressed by this patch. Signed-off-by: Svyatoslav Ryhel --- drivers/gpu/drm/tegra/drm.c | 2 + drivers/gpu/drm/tegra/dsi.c | 88 ++++++++++++++++++++++++------------- drivers/gpu/drm/tegra/dsi.h | 15 +++++++ 3 files changed, 74 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 4596073fe28f..5d64cd57e764 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -1359,10 +1359,12 @@ static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_= drm_suspend, =20 static const struct of_device_id host1x_drm_subdevs[] =3D { { .compatible =3D "nvidia,tegra20-dc", }, + { .compatible =3D "nvidia,tegra20-dsi", }, { .compatible =3D "nvidia,tegra20-hdmi", }, { .compatible =3D "nvidia,tegra20-gr2d", }, { .compatible =3D "nvidia,tegra20-gr3d", }, { .compatible =3D "nvidia,tegra30-dc", }, + { .compatible =3D "nvidia,tegra30-dsi", }, { .compatible =3D "nvidia,tegra30-hdmi", }, { .compatible =3D "nvidia,tegra30-gr2d", }, { .compatible =3D "nvidia,tegra30-gr3d", }, diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index 8e80c7efe8b4..d079aa7d2a85 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -53,6 +53,10 @@ to_dsi_state(struct drm_connector_state *state) return container_of(state, struct tegra_dsi_state, base); } =20 +struct tegra_dsi_config { + u32 dsi_version; +}; + struct tegra_dsi { struct host1x_client client; struct tegra_output output; @@ -82,6 +86,8 @@ struct tegra_dsi { /* for ganged-mode support */ struct tegra_dsi *master; struct tegra_dsi *slave; + + const struct tegra_dsi_config *config; }; =20 static inline struct tegra_dsi * @@ -663,39 +669,46 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) { u32 value; =20 - value =3D DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); + if (dsi->config->dsi_version =3D=3D TEGRA_DSI_V1) { + /* + * XXX Is this still needed? The module reset is deasserted right + * before this function is called. + */ + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); + + value =3D DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); + + value =3D DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | + DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | + DSI_PAD_OUT_CLK(0x0); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); + + value =3D DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | + DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); + } else { + value =3D DSI_PAD_CONTROL_LPUPADJ(0x1) | DSI_PAD_CONTROL_LPDNADJ(0x1) | + DSI_PAD_CONTROL_PREEMP_EN(0x1) | DSI_PAD_CONTROL_SLEWDNADJ(0x6) | + DSI_PAD_CONTROL_SLEWUPADJ(0x6) | DSI_PAD_CONTROL_PDIO(0) | + DSI_PAD_CONTROL_PDIO_CLK(0) | DSI_PAD_CONTROL_PULLDN_ENAB(0); + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); + } =20 return 0; } =20 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) { - u32 value; int err; =20 - /* - * XXX Is this still needed? The module reset is deasserted right - * before this function is called. - */ - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); - /* start calibration */ tegra_dsi_pad_enable(dsi); =20 - value =3D DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | - DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | - DSI_PAD_OUT_CLK(0x0); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); - - value =3D DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | - DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); - err =3D tegra_mipi_start_calibration(dsi->mipi); if (err < 0) return err; @@ -1577,6 +1590,7 @@ static int tegra_dsi_probe(struct platform_device *pd= ev) if (!dsi) return -ENOMEM; =20 + dsi->config =3D of_device_get_match_data(&pdev->dev); dsi->output.dev =3D dsi->dev =3D &pdev->dev; dsi->video_fifo_depth =3D 1920; dsi->host_fifo_depth =3D 64; @@ -1615,7 +1629,7 @@ static int tegra_dsi_probe(struct platform_device *pd= ev) goto remove; } =20 - dsi->clk_lp =3D devm_clk_get(&pdev->dev, "lp"); + dsi->clk_lp =3D devm_clk_get_optional(&pdev->dev, "lp"); if (IS_ERR(dsi->clk_lp)) { err =3D dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp), "cannot get low-power clock\n"); @@ -1636,10 +1650,12 @@ static int tegra_dsi_probe(struct platform_device *= pdev) goto remove; } =20 - err =3D tegra_dsi_setup_clocks(dsi); - if (err < 0) { - dev_err(&pdev->dev, "cannot setup clocks\n"); - goto remove; + if (dsi->config->dsi_version =3D=3D TEGRA_DSI_V1) { + err =3D tegra_dsi_setup_clocks(dsi); + if (err < 0) { + dev_err(&pdev->dev, "cannot setup clocks\n"); + goto remove; + } } =20 dsi->regs =3D devm_platform_ioremap_resource(pdev, 0); @@ -1703,11 +1719,21 @@ static void tegra_dsi_remove(struct platform_device= *pdev) tegra_mipi_free(dsi->mipi); } =20 +static const struct tegra_dsi_config tegra20_dsi_config =3D { + .dsi_version =3D TEGRA_DSI_V0, +}; + +static const struct tegra_dsi_config tegra114_dsi_config =3D { + .dsi_version =3D TEGRA_DSI_V1, +}; + static const struct of_device_id tegra_dsi_of_match[] =3D { - { .compatible =3D "nvidia,tegra210-dsi", }, - { .compatible =3D "nvidia,tegra132-dsi", }, - { .compatible =3D "nvidia,tegra124-dsi", }, - { .compatible =3D "nvidia,tegra114-dsi", }, + { .compatible =3D "nvidia,tegra210-dsi", .data =3D &tegra114_dsi_config }, + { .compatible =3D "nvidia,tegra132-dsi", .data =3D &tegra114_dsi_config }, + { .compatible =3D "nvidia,tegra124-dsi", .data =3D &tegra114_dsi_config }, + { .compatible =3D "nvidia,tegra114-dsi", .data =3D &tegra114_dsi_config }, + { .compatible =3D "nvidia,tegra30-dsi", .data =3D &tegra20_dsi_config }, + { .compatible =3D "nvidia,tegra20-dsi", .data =3D &tegra20_dsi_config }, { }, }; MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); diff --git a/drivers/gpu/drm/tegra/dsi.h b/drivers/gpu/drm/tegra/dsi.h index f39594e65e97..5049ec7813c7 100644 --- a/drivers/gpu/drm/tegra/dsi.h +++ b/drivers/gpu/drm/tegra/dsi.h @@ -95,6 +95,16 @@ #define DSI_TALLY_LRX(x) (((x) & 0xff) << 8) #define DSI_TALLY_HTX(x) (((x) & 0xff) << 0) #define DSI_PAD_CONTROL_0 0x4b +/* DSI V0 */ +#define DSI_PAD_CONTROL_PULLDN_ENAB(x) (((x) & 0x1) << 28) +#define DSI_PAD_CONTROL_SLEWUPADJ(x) (((x) & 0x7) << 24) +#define DSI_PAD_CONTROL_SLEWDNADJ(x) (((x) & 0x7) << 20) +#define DSI_PAD_CONTROL_PREEMP_EN(x) (((x) & 0x1) << 19) +#define DSI_PAD_CONTROL_PDIO_CLK(x) (((x) & 0x1) << 18) +#define DSI_PAD_CONTROL_PDIO(x) (((x) & 0x3) << 16) +#define DSI_PAD_CONTROL_LPUPADJ(x) (((x) & 0x3) << 14) +#define DSI_PAD_CONTROL_LPDNADJ(x) (((x) & 0x3) << 12) +/* DSI V1 */ #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) #define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) @@ -140,4 +150,9 @@ enum tegra_dsi_format { TEGRA_DSI_FORMAT_24P, }; =20 +enum tegra_dsi_version { + TEGRA_DSI_V0, + TEGRA_DSI_V1, +}; + #endif --=20 2.48.1