From nobody Tue Sep 9 16:20:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A4FA25BEF8; Sat, 6 Sep 2025 04:13:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132022; cv=none; b=u3+mTz3yayrFlnC4blCwfIn+u5mcJsvtf5UOk4U7FSRdXSAqHq8SYFiDWAYBuGlCfC+JjwHtjaimkmgBeLAFr4HCobzUSDriJGAVrp5htMQFNDLbubyOD7KjPhpKsNxdPTAt+c99hvzA/3XP35Hb66niTfQKXagGHey5LNjIy/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132022; c=relaxed/simple; bh=cGn/A6pv5/QIRUIvcflPGOg7C3keUUcnpZ16rUvo3ZA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=U73+djXEhHQ4skuuerKwKkqtqZ+iyNDjjdQaWf50zO2epISKdMkq85FdkT99gMWiPQC3F4xlYxtRHZv8lUWjmYc1upuXPw4+Uwf+ea0UxYCvI3vr0/gGYoPN5AuzwH0scqyBwEdhsGm9yDZiUgsqqHvTuwU5y44/VlI8Ywe/StY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jMCqmG8X; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jMCqmG8X" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8831C4CEF9; Sat, 6 Sep 2025 04:13:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757132022; bh=cGn/A6pv5/QIRUIvcflPGOg7C3keUUcnpZ16rUvo3ZA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jMCqmG8XhfdDjFQNrGIYpHAZwpEOfwxAuRgcq+VvwROzExK7lxf2jGIYMpWJ9kolL dj3HKl8NrOGySD/8VYF0MeV/ym5LqniQZta7ErM9hJ+4CJ9+L58wlgKLmy+EcaTyUA 1SDV+kTWklP/zVYJJmNbiHohB3SG9nUV1lVvSA7JqQ3q5QE2lLLxTc2KH/B9zpvjZY iwbFnaexBWjXTSvk7B14sfD27IRCifWT2MzzWXY1dgtokWCyaZpdi99VOSmdWz/vng 3dbYNog0DhcRBRqbtFaoxknytNM2NTGDX9oVhTABUvzbIgIAFHs6mqXTUmSBk4hkC1 QFKijWspFTJBg== Received: by wens.tw (Postfix, from userid 1000) id 9F1A05FAC5; Sat, 06 Sep 2025 12:13:38 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v3 01/10] dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible Date: Sat, 6 Sep 2025 12:13:24 +0800 Message-Id: <20250906041333.642483-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250906041333.642483-1-wens@kernel.org> References: <20250906041333.642483-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a compatible string entry for it, and work in the requirements for a second clock and a power domain. Signed-off-by: Chen-Yu Tsai --- Changes since v2: - Added "select" to avoid matching against all dwmac entries Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../net/allwinner,sun8i-a83t-emac.yaml | 96 ++++++++++++++++++- 1 file changed, 94 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-ema= c.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.ya= ml index 2ac709a4c472..9d205c5d93ca 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -10,6 +10,21 @@ maintainers: - Chen-Yu Tsai - Maxime Ripard =20 +# We need a select here so we don't match all nodes with 'snps,dwmac' +select: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-emac + - allwinner,sun8i-h3-emac + - allwinner,sun8i-r40-gmac + - allwinner,sun8i-v3s-emac + - allwinner,sun50i-a64-emac + - allwinner,sun55i-a523-gmac200 + required: + - compatible + properties: compatible: oneOf: @@ -26,6 +41,9 @@ properties: - allwinner,sun50i-h616-emac0 - allwinner,sun55i-a523-gmac0 - const: allwinner,sun50i-a64-emac + - items: + - const: allwinner,sun55i-a523-gmac200 + - const: snps,dwmac-4.20a =20 reg: maxItems: 1 @@ -37,14 +55,19 @@ properties: const: macirq =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 clock-names: - const: stmmaceth + minItems: 1 + maxItems: 2 =20 phy-supply: description: PHY regulator =20 + power-domains: + maxItems: 1 + syscon: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -191,6 +214,45 @@ allOf: - mdio-parent-bus - mdio@1 =20 + - if: + properties: + compatible: + contains: + const: allwinner,sun55i-a523-gmac200 + then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: stmmaceth + - const: mbus + tx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 700 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + rx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 3100 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + required: + - power-domains + else: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: stmmaceth + power-domains: false + + unevaluatedProperties: false =20 examples: @@ -323,4 +385,34 @@ examples: }; }; =20 + - | + ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu 117>, <&ccu 79>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu 43>; + reset-names =3D "stmmaceth"; + interrupts =3D <0 47 4>; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 4>; + syscon =3D <&syscon>; + phy-handle =3D <&ext_rgmii_phy_1>; + phy-mode =3D "rgmii-id"; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ext_rgmii_phy_1: ethernet-phy@1 { + reg =3D <1>; + }; + }; + }; ... --=20 2.39.5 From nobody Tue Sep 9 16:20:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C83725BEE7; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RDnLlab7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BDF74C4CEF7; Sat, 6 Sep 2025 04:13:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757132021; bh=7ezgqWe8YoIYR8sACxy16DNlijdxVUU1e6mgg+928iI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RDnLlab7YBU8jClTxmQGNK2Es6Ckohx4WlyZuhAOnDiKQhODx9wU7IYq/pVnGHeaV 1NNBCVIRD2oDqe4cns9gOz9GjVpnAvm8YQT940222JiRlU6PHPz0z0nQtt4s06JJEK P+xGNmd+7PpvWRRfarAIxGFa4FT6wguzMFPeyMFsKqWw0BayyKEMrctgri2I9ONBlX ocmuxk0n+Aqftge5w+LSEnQb9g+9RbzDn+bEdpnM7t+dIB7IQbasRwJe/bS+slD7Cw /H+tuuQTflkJJjHY2tLpcOgMDG3teP6DQyHNslNwyjT+j180UVexxfVDNzR5h0xOWw gaRZnhcWGYSRw== Received: by wens.tw (Postfix, from userid 1000) id AB84B5FE30; Sat, 06 Sep 2025 12:13:38 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v3 02/10] net: stmmac: Add support for Allwinner A523 GMAC200 Date: Sat, 6 Sep 2025 12:13:25 +0800 Message-Id: <20250906041333.642483-3-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250906041333.642483-1-wens@kernel.org> References: <20250906041333.642483-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a new driver for this hardware supporting the integration layer. Signed-off-by: Chen-Yu Tsai --- Changes since v2 (all suggested by Russell King): - Include "ps" unit in "... must be multiple of ..." error message - Use FIELD_FIT to check if delay value is in range and FIELD_MAX to get the maximum value - Reword error message for delay value exceeding maximum - Drop MASK_TO_VAL Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Change dev_err() + return to dev_err_probe() - Check return value from syscon regmap write - Change driver name to match file name --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-sun55i.c | 159 ++++++++++++++++++ 3 files changed, 172 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 67fa879b1e52..38ce9a0cfb5b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -263,6 +263,18 @@ config DWMAC_SUN8I stmmac device driver. This driver is used for H3/A83T/A64 EMAC ethernet controller. =20 +config DWMAC_SUN55I + tristate "Allwinner sun55i GMAC200 support" + default ARCH_SUNXI + depends on OF && (ARCH_SUNXI || COMPILE_TEST) + select MDIO_BUS_MUX + help + Support for Allwinner A523/T527 GMAC200 ethernet controllers. + + This selects Allwinner SoC glue layer support for the + stmmac device driver. This driver is used for A523/T527 + GMAC200 ethernet controller. + config DWMAC_THEAD tristate "T-HEAD dwmac support" depends on OF && (ARCH_THEAD || COMPILE_TEST) diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index b591d93f8503..51e068e26ce4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_STI) +=3D dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) +=3D dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) +=3D dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUN8I) +=3D dwmac-sun8i.o +obj-$(CONFIG_DWMAC_SUN55I) +=3D dwmac-sun55i.o obj-$(CONFIG_DWMAC_THEAD) +=3D dwmac-thead.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) +=3D dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) +=3D dwmac-intel-plat.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c b/drivers/n= et/ethernet/stmicro/stmmac/dwmac-sun55i.c new file mode 100644 index 000000000000..fb127e7a297d --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dwmac-sun55i.c - Allwinner sun55i GMAC200 specific glue layer + * + * Copyright (C) 2025 Chen-Yu Tsai + * + * syscon parts taken from dwmac-sun8i.c, which is + * + * Copyright (C) 2017 Corentin Labbe + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac.h" +#include "stmmac_platform.h" + +#define SYSCON_REG 0x34 + +/* RMII specific bits */ +#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ +/* Generic system control EMAC_CLK bits */ +#define SYSCON_ETXDC_MASK GENMASK(12, 10) +#define SYSCON_ERXDC_MASK GENMASK(9, 5) +/* EMAC PHY Interface Type */ +#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ +#define SYSCON_ETCS_MASK GENMASK(1, 0) +#define SYSCON_ETCS_MII 0x0 +#define SYSCON_ETCS_EXT_GMII 0x1 +#define SYSCON_ETCS_INT_GMII 0x2 + +static int sun55i_gmac200_set_syscon(struct device *dev, + struct plat_stmmacenet_data *plat) +{ + struct device_node *node =3D dev->of_node; + struct regmap *regmap; + u32 val, reg =3D 0; + int ret; + + regmap =3D syscon_regmap_lookup_by_phandle(node, "syscon"); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Unable to map syscon\n"); + + if (!of_property_read_u32(node, "tx-internal-delay-ps", &val)) { + if (val % 100) + return dev_err_probe(dev, -EINVAL, + "tx-delay must be a multiple of 100ps\n"); + val /=3D 100; + dev_dbg(dev, "set tx-delay to %x\n", val); + if (!FIELD_FIT(SYSCON_ETXDC_MASK, val)) + return dev_err_probe(dev, -EINVAL, + "TX clock delay exceeds maximum (%d00ps > %d00ps)\n", + val, FIELD_MAX(SYSCON_ETXDC_MASK)); + + reg |=3D FIELD_PREP(SYSCON_ETXDC_MASK, val); + } + + if (!of_property_read_u32(node, "rx-internal-delay-ps", &val)) { + if (val % 100) + return dev_err_probe(dev, -EINVAL, + "rx-delay must be a multiple of 100ps\n"); + val /=3D 100; + dev_dbg(dev, "set rx-delay to %x\n", val); + if (!FIELD_FIT(SYSCON_ERXDC_MASK, val)) + return dev_err_probe(dev, -EINVAL, + "RX clock delay exceeds maximum (%d00ps > %d00ps)\n", + val, FIELD_MAX(SYSCON_ERXDC_MASK)); + + reg |=3D FIELD_PREP(SYSCON_ERXDC_MASK, val); + } + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + /* default */ + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + reg |=3D SYSCON_EPIT | SYSCON_ETCS_INT_GMII; + break; + case PHY_INTERFACE_MODE_RMII: + reg |=3D SYSCON_RMII_EN; + break; + default: + return dev_err_probe(dev, -EINVAL, "Unsupported interface mode: %s", + phy_modes(plat->mac_interface)); + } + + ret =3D regmap_write(regmap, SYSCON_REG, reg); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to write to syscon\n"); + + return 0; +} + +static int sun55i_gmac200_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct device *dev =3D &pdev->dev; + struct clk *clk; + int ret; + + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + /* BSP disables it */ + plat_dat->flags |=3D STMMAC_FLAG_SPH_DISABLE; + plat_dat->host_dma_width =3D 32; + + ret =3D sun55i_gmac200_set_syscon(dev, plat_dat); + if (ret) + return ret; + + clk =3D devm_clk_get_enabled(dev, "mbus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get or enable MBUS clock\n"); + + ret =3D devm_regulator_get_enable_optional(dev, "phy"); + if (ret) + return dev_err_probe(dev, ret, "Failed to get or enable PHY supply\n"); + + return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); +} + +static const struct of_device_id sun55i_gmac200_match[] =3D { + { .compatible =3D "allwinner,sun55i-a523-gmac200" }, + { } +}; +MODULE_DEVICE_TABLE(of, sun55i_gmac200_match); + +static struct platform_driver sun55i_gmac200_driver =3D { + .probe =3D sun55i_gmac200_probe, + .driver =3D { + .name =3D "dwmac-sun55i", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D sun55i_gmac200_match, + }, +}; +module_platform_driver(sun55i_gmac200_driver); + +MODULE_AUTHOR("Chen-Yu Tsai "); +MODULE_DESCRIPTION("Allwinner sun55i GMAC200 specific glue layer"); +MODULE_LICENSE("GPL"); --=20 2.39.5 From nobody Tue Sep 9 16:20:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A49A25BEF1; Sat, 6 Sep 2025 04:13:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132022; cv=none; b=MvUymzW6Cfp632MLmKoTdP0nMAZJIafY2sITOjZELd5Uyaw2b9u0K4MFlDOnEOJZMBfE/GDpjNaMCTY9BWG1QerBHIQ3tV6uuJe/iWTV2ZGjncIy9xpWf9onbFW7Oq0pyATZPh3xzt3hzhIzSnArwYnKOyJg05at1N8+VDbGQM0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132022; c=relaxed/simple; bh=e0tQSO9pJI2jVvlvL9W4OBbAj83puHTjG+o0KV+3bdg=; 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Sat, 06 Sep 2025 12:13:38 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v3 03/10] soc: sunxi: sram: add entry for a523 Date: Sat, 6 Sep 2025 12:13:26 +0800 Message-Id: <20250906041333.642483-4-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250906041333.642483-1-wens@kernel.org> References: <20250906041333.642483-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 has two Ethernet controllers. So in the system controller address space, there are two registers for Ethernet clock delays, one for each controller. Add a new entry for the A523 system controller that allows access to the second register. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- drivers/soc/sunxi/sunxi_sram.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 08e264ea0697..4f8d510b7e1e 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -320,6 +320,10 @@ static const struct sunxi_sramc_variant sun50i_h616_sr= amc_variant =3D { .has_ths_offset =3D true, }; =20 +static const struct sunxi_sramc_variant sun55i_a523_sramc_variant =3D { + .num_emac_clocks =3D 2, +}; + #define SUNXI_SRAM_THS_OFFSET_REG 0x0 #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30 #define SUNXI_SYS_LDO_CTRL_REG 0x150 @@ -440,6 +444,10 @@ static const struct of_device_id sunxi_sram_dt_match[]= =3D { .compatible =3D "allwinner,sun50i-h616-system-control", .data =3D &sun50i_h616_sramc_variant, }, + { + .compatible =3D "allwinner,sun55i-a523-system-control", + .data =3D &sun55i_a523_sramc_variant, + }, { }, }; MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match); --=20 2.39.5 From nobody Tue Sep 9 16:20:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C89825BEE8; Sat, 6 Sep 2025 04:13:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132022; cv=none; b=mNzxbijf4Zdb720vlJEVD1Ywv3Xa4n0MbLmKHqwuCuebfqlnur3z2q04jGF+OkdrsQkVHPvtmU5oP/EG4+6mWE2mgKsvzDVnizOkZV9nJo0iCHopZEsjqKbOSB+0cuNJ1kAUg61sbsYUccrhD3SHpnr3Wv3NiFlgYXx/fax4StE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132022; c=relaxed/simple; bh=lfdtXInB87tu2kO8lr4PclPJGDu1MGh0UniOZ5ZFUPg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Tkk94MQIzjJB+gthy5TUjJ7Jro9EN0w9NXmOU4fB2HIkUbFQG0oEezKzBZWqQ029ZV9WEmX8GmU6j4sf+GEetxwrIvQXku/ASBS3KYcsHEA0mXVQvmBmocIghWeSR/lsInkCU/io7LfXZOqcVKEolzn5+DDgEG4AnbyD0vDqcMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=imNNXESu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="imNNXESu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BC1FBC4CEE7; Sat, 6 Sep 2025 04:13:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757132021; bh=lfdtXInB87tu2kO8lr4PclPJGDu1MGh0UniOZ5ZFUPg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=imNNXESu02WE1qAyRlqDwx5gn4CSI1yvviY+YPNUpQ7ahq06PBnc0KUIFEHPzTt97 seBu+49//TFDQgIijITmxTikt8UX7UcIrmtQ2y6yyL2jsNtWf3k2FszhN10W9ksFLh /ODLgEk0QChgcK5zQwcMC3ALVVaIxS5e/GAINLMxOyKobRPoVUOCosyDLVCNiuPEII zjseB6Esd0jrO+s5yc/9WdnsnVQrqXMoJvzVFMTs3nemYa8nOTsVw7fSUpN+rPhWwk GaEdE5bvRm8iGQob2+WKph8JzN8xJC7ECVS7lkLndYaaf4TFyv3+YVxy6Kwfvc5Ve+ 8uJJp3qJ241gw== Received: by wens.tw (Postfix, from userid 1000) id BFAFC5FEB3; Sat, 06 Sep 2025 12:13:38 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v3 04/10] soc: sunxi: sram: register regmap as syscon Date: Sat, 6 Sep 2025 12:13:27 +0800 Message-Id: <20250906041333.642483-5-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250906041333.642483-1-wens@kernel.org> References: <20250906041333.642483-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai If the system controller had a ethernet controller glue layer control register, a limited access regmap would be registered and tied to the system controller struct device for the ethernet driver to use. Until now, for the ethernet driver to acquire this regmap, it had to do a of_parse_phandle() + find device + dev_get_regmap() sequence. Since the syscon framework allows a provider to register a custom regmap for its device node, and the ethernet driver already uses syscon for one platform, this provides a much more easier way to pass the regmap. Use of_syscon_register_regmap() to register our regmap with the syscon framework so that consumers can retrieve it that way. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Fix check on return value - Expand commit message --- drivers/soc/sunxi/sunxi_sram.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 4f8d510b7e1e..1837e1b5dce8 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -12,6 +12,7 @@ =20 #include #include +#include #include #include #include @@ -377,6 +378,7 @@ static int __init sunxi_sram_probe(struct platform_devi= ce *pdev) const struct sunxi_sramc_variant *variant; struct device *dev =3D &pdev->dev; struct regmap *regmap; + int ret; =20 sram_dev =3D &pdev->dev; =20 @@ -394,6 +396,10 @@ static int __init sunxi_sram_probe(struct platform_dev= ice *pdev) regmap =3D devm_regmap_init_mmio(dev, base, &sunxi_sram_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); + + ret =3D of_syscon_register_regmap(dev->of_node, regmap); + if (ret) + return ret; } =20 of_platform_populate(dev->of_node, NULL, NULL, dev); --=20 2.39.5 From nobody Tue Sep 9 16:20:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4456C26CE29; Sat, 6 Sep 2025 04:13:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132024; cv=none; b=IISdvfA+oYZqwvaApNWstLzcrwoOe1mGePoQxnkkSMrm6yscCmaMx6uwelkC07/qBXFxCKW3cSrQIQ54etGlB+J8Tq5fY9TzKUeQw7bRQF3qeHni1ignEye1vtHDPbxaGqTQyVmKUR5ZEcXOUKVKiyRifhyXhAIi7cnMnfqK+jU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132024; c=relaxed/simple; bh=k8chtkdd/C7iCwiNiHHjJu/kaYcxaJejVp0B1FUTyf8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Cc+O9PAaqkcxKUI94WfcLhFEn+gowk3WGav6zvQPKcbLegwKDfA1N7EsvJlyhBJmoIZ3GiYG2odlnE3msezIvI4dC3VmU6O8zTNXfXEq96xej9trVF1fuBmZtTMNoCCrPU3QoNS8hN6InwW+xVo6GXD9i8UEAhNgIq3wAFuN2e4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kU7nmGmr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kU7nmGmr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EFCF3C4CEFB; Sat, 6 Sep 2025 04:13:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757132024; bh=k8chtkdd/C7iCwiNiHHjJu/kaYcxaJejVp0B1FUTyf8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kU7nmGmr9GrP4fcgHMZu/lxXC++AHKUEE8K4NSMilL6KWWJHUJ9wuxuCFSj9jvhnH dOytLE1oxMFdarHdgiDBcLuZm9bLBNLfdi4zpFcPyGUfPi2NJD4ilLbrOO2aN4Poeh /7nrVE5RldkgxTaQSjXJpwt46djfnLx2kaOrIEZVCT+TvnOwqka3Ww/X2pVv3Z44uE FvLB0YppLtE29Yjubq6mGkpo4aPCiRyK4CEonGSrW79MYbKhogDkttLylFZl65zrXD PNaXajXRZORwYHKmuVb6btnZhB72mt5G/uvT+ni2bt9ND+KTa1OrnG19UJLXsFHWYB 47eSJPfIPhDRA== Received: by wens.tw (Postfix, from userid 1000) id CBFBC5FEEF; Sat, 06 Sep 2025 12:13:38 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v3 05/10] arm64: dts: allwinner: a523: Add GMAC200 ethernet controller Date: Sat, 6 Sep 2025 12:13:28 +0800 Message-Id: <20250906041333.642483-6-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250906041333.642483-1-wens@kernel.org> References: <20250906041333.642483-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 SoC family has a second ethernet controller, called the GMAC200. It is not exposed on all the SoCs in the family. Add a device node for it. All the hardware specific settings are from the vendor BSP. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Fixed typo in tx-queues-config --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 6b6f2296bdff..449bcafbddcd 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -180,6 +180,16 @@ rgmii0_pins: rgmii0-pins { bias-disable; }; =20 + rgmii1_pins: rgmii1-pins { + pins =3D "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", + "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", + "PJ11", "PJ12", "PJ13", "PJ14", "PJ15"; + allwinner,pinmux =3D <5>; + function =3D "gmac1"; + drive-strength =3D <40>; + bias-disable; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; @@ -601,6 +611,51 @@ mdio0: mdio { }; }; =20 + gmac1: ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu RST_BUS_EMAC1>; + reset-names =3D "stmmaceth"; + interrupts =3D ; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 PD_VO1>; + syscon =3D <&syscon>; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config =3D <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac1_mtl_tx_setup>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + + queue0 {}; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0xf>; + snps,rd_osr_lmt =3D <0xf>; + snps,blen =3D <256 128 64 32 16 8 4>; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + + queue0 {}; + }; + }; + ppu: power-controller@7001400 { compatible =3D "allwinner,sun55i-a523-ppu"; reg =3D <0x07001400 0x400>; --=20 2.39.5 From nobody Tue Sep 9 16:20:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4872F26CE2C; Sat, 6 Sep 2025 04:13:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132024; cv=none; b=uT6/pm18PqLQwCUuFTdvyoAMgdMDnRyXRcCV0rxSfmgn+bYlY+iVNABRy7smJ3vPw10ZaxPsPnI0zbejOkW0eDxlT/PDiK/ndJ5XmO3rcoCEKM8KC9DqHi03FFEeBo/apIhDDEQJeZGC66ouPQnVDNQpxxVowr/UOkZTE5otljM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132024; c=relaxed/simple; bh=tDfUpZExKmJMXStQh2fTARqlHOrlMBEVmIQj8qTNpp8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DMHY519qOg+06vY7Nx4HxmoW0Je7Xa+YdoGc3VdpmGbM/xx706qpbsiEuLl3pXivJzk8Dq06M3Mssy6KjwQu5KyYF+cpyp0enRGxsE0PDUB+xnT0jBsfXxJ7FUtQOhwVWXKiGfXjMpe1dFRPAG1NJ0uBL1l9HvnotSgM8TEK8aI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qxcX3hDd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qxcX3hDd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 04BB9C4CEF7; Sat, 6 Sep 2025 04:13:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757132024; bh=tDfUpZExKmJMXStQh2fTARqlHOrlMBEVmIQj8qTNpp8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qxcX3hDdhIcHU3lc6DId6MV315Sk7yYxVfYARSA80aE259q6UGqWfhpcdvQ0sSDMW vw1uu7EhOf86FWBcj70eUuJ9tjOsPY6MCZNGXZRQUxX85V0Q0y4d+/lujPNMTEhnNt 0LZLQY8AuPtKB/8N3aoy/aEzMmwa6iQ6EQfJ07B0Uyxx9tzWn6CJZYsrzpkLhglHqK sLJoe7ZZuMUA4hpYoh0MsrEFY8XOkCSc6pMjCrkFNoKnPKoi+tm1U1V3r/+LTuHmEo XGnTuepdldm36U+VNpLSWxlkPOre2hll8LTqd30iQligkWtmm/w16k591RYns7Xenv RuVsh29ymcmcQ== Received: by wens.tw (Postfix, from userid 1000) id D59155FEF5; Sat, 06 Sep 2025 12:13:38 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v3 06/10] arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting Date: Sat, 6 Sep 2025 12:13:29 +0800 Message-Id: <20250906041333.642483-7-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250906041333.642483-1-wens@kernel.org> References: <20250906041333.642483-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: acca163f3f51 ("arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E b= oard") Signed-off-by: Chen-Yu Tsai Acked-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 70d439bc845c..d4cee2222104 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -94,6 +94,9 @@ &mdio0 { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; }; }; =20 --=20 2.39.5 From nobody Tue Sep 9 16:20:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DB2A26F281; Sat, 6 Sep 2025 04:13:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132024; cv=none; b=sZysJAG24v0JHeBF8gq2e3jSFfP5m19UrylembYiQ4ny9n/Ne8+/fcqeZ78/G8Hj+C0JDgJUERL+xo4AGUA2s8FuUk0rUA0g0HeiSlJ73ZMM3zNaREx1kGUAyVv1xwxgH7bUvD/Y6YX/nKgt30p2Zxh2J63FPYpcIz4LVBrA8FU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132024; c=relaxed/simple; bh=1u87rs46+m5wL1Xw7aZOQ0O0nwgjPdStsou5RO+mPyc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KOGa4tSQWtJDZRfAdWzYx/kKC+kkmom6Ar0Yug/Or3UZH+p4Mye8AZ2maf/u9OddAzpCktbB6NvRo07BYb5ZOY+FVz7M9sGd1lZU526+yA1RiuB17Jnvyvx864QbERi1htOPu7Pc+zGLz4F2B+taGb9Z7STp4A5g0JUax4R4iGA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dKv/t1mI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dKv/t1mI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 02421C4CEFE; Sat, 6 Sep 2025 04:13:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757132024; bh=1u87rs46+m5wL1Xw7aZOQ0O0nwgjPdStsou5RO+mPyc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dKv/t1mIARtg/Pk7uvV2k04TohqX82g0g1CslFnScuHvlRnMJ0oAbw897cb/4iJ7T FlzO+I6g9dae4s3Agz5cwFapOF0P4pFUtmID6z7reQsxIAQx48sg1bW9NdNYkImeMz RioQBYpZtJV2/fr4YjNtKMwpJbTaAJNFml3NN+cSd5sL9QsqhK/Mxt82hsuKdfgAzf z2aqlq2likSRvMlOcw/x0bTOJX93qJPKLqNegi6AuyAdvhGb4xKV88NS+LKQswXKHA VuHidAOAyqlICR+Dl4iJ83cK781fdVYYQvcaOPfyOtcHnkz58y3o6OcixE8hxaXO0t KfZvMdV/wpzYg== Received: by wens.tw (Postfix, from userid 1000) id E91555FF44; Sat, 06 Sep 2025 12:13:38 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v3 07/10] arm64: dts: allwinner: a527: cubie-a5e: Enable second Ethernet port Date: Sat, 6 Sep 2025 12:13:30 +0800 Message-Id: <20250906041333.642483-8-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250906041333.642483-1-wens@kernel.org> References: <20250906041333.642483-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Radxa Cubie A5E board, the second Ethernet controller, aka the GMAC200, is connected to a second external Maxio MAE0621A PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. An enable delay for the PHY supply regulator is added to make sure the PHY's internal regulators are fully powered and the PHY is operational. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Add PHY regulator delay --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index d4cee2222104..e96a419faf21 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -14,6 +14,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -76,7 +77,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_cldo3>; =20 allwinner,tx-delay-ps =3D <300>; @@ -85,13 +86,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <300>; + rx-internal-delay-ps =3D <400>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -100,6 +112,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ @@ -240,6 +262,8 @@ reg_cldo4: cldo4 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-name =3D "vcc-pj-phy"; + /* enough time for the PHY to fully power on */ + regulator-enable-ramp-delay =3D <150000>; }; =20 reg_cpusldo: cpusldo { --=20 2.39.5 From nobody Tue Sep 9 16:20:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DA4826E70C; Sat, 6 Sep 2025 04:13:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132024; cv=none; b=l8cPLyo8P1A59D5yNku2JDs1FZbgFLQrhNMvRGKj+fZRcKe+XVNXKaWvMRT/y64prDgGh9K4WlEtB/LnwuOfuRzUrVwqyPb2ohkg9XLVeIazOn/Nppz07nKXlgn669gttsO8fPP1i4/Mcq+EXTYoKI1I03j4RMtWvsoulNgZYzg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132024; c=relaxed/simple; bh=coKgeanaUZ3X4I0jziHLWfdNIN3UjLw9i/nP+qWcjHY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jgmz7OMMMVU7ILnyyiU02wBlVrdjvG1Lcfx8aJMrg5dQpIIXoSihZI/c6P9b0S8ameAHmyJT1c64m3KYYMlNbyvdXyDVOZX5mk0cd3Clsp3QM5+7eFiTzAhnHWz73tf4cQVg95mrUgsh0tF5QcAAxSxZe0Mjml+vFdZy9L3fwfg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=coau5L4V; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="coau5L4V" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 09206C4CEF8; Sat, 6 Sep 2025 04:13:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757132024; bh=coKgeanaUZ3X4I0jziHLWfdNIN3UjLw9i/nP+qWcjHY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=coau5L4VcUBh0pb7ft7mpwoSZY/nZgwM8Umvnx01Nwbm1ZUwnwRH77dcw2XJN3rZD RD7USlnj4bsrb+YF1AFycelE5v12xACcnlkDYSSJTAP4Iq/mglQZ7B9X70KTjaHAFv ThofGXaZJH+gM6tDAliipZa1Y94iXBjLed94C2aNVyXwRSjnYV2ZPlcNBEfmdrVNP5 phiBVWBhO4wAJtlIZsNnvPbanxBywMqbUeaWhCERI+eJETInsXiDE5n+fWs2k9a6wg IfngRvqzL0glUpW6RJmab9E727RyXFywaJLBvFb9jmyEcidrVdlkJ2k8vZxO+bSGb/ E84OJY7fVm2fg== Received: by wens.tw (Postfix, from userid 1000) id F1BF75FF75; Sat, 06 Sep 2025 12:13:38 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v3 08/10] arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting Date: Sat, 6 Sep 2025 12:13:31 +0800 Message-Id: <20250906041333.642483-9-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250906041333.642483-1-wens@kernel.org> References: <20250906041333.642483-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: c6800f15998b ("arm64: dts: allwinner: t527: add EMAC0 to Avaota-A1 b= oard") Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index b9eeb6753e9e..e7713678208d 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -85,6 +85,9 @@ &mdio0 { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; }; }; =20 --=20 2.39.5 From nobody Tue Sep 9 16:20:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB80A27057C; Sat, 6 Sep 2025 04:13:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132024; cv=none; b=a/GhPlIMUEnilacIBf0NpVTe7xmDGHQLMYWbRHZAf6/vrTMIHxmIyjJrd17BxE192lriFbCtNGS2uXbsldGFnqmA+tuMjMFdanhJE0tA60B7lcCSmSPYIfp1u+brHyYFbJL8qYY5EXrG1TgtMD9c2wllkKPoM37fifKofWSAa38= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132024; c=relaxed/simple; bh=KwQ33/Me6CtoPqF903pwWNvdntE/FNahw7BHgwIWeoE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NaQ5AD8tkBJBAVC5Yd6znhJUGGPx1c+t7LNLtg0bYFW0/kl30NZ157LibbXTk7ckqgmtJY10CFyGon5QJSFicQXX4J04yCAcmALuG8xCrGKbQwSM9QJvqq/1argGliZ7snqz/IcxB+zUNmgHCxtmUpElpwYpK3q3XeXVa3aUgso= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NXfuaFnG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NXfuaFnG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5B92FC4CEF9; Sat, 6 Sep 2025 04:13:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757132024; bh=KwQ33/Me6CtoPqF903pwWNvdntE/FNahw7BHgwIWeoE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NXfuaFnGH4VZDCWcXHddtfnJp4yQD3T3SAbvOEczeEuvfFcbi5xLco1Yax1zkJKDY nnE2nMb7HGtfVV+VVDvmF8/2WKe0yZxmYCozVUg2TSZYmmQIlsbU8fmYPUJxieLCfZ InAQDS7FmYnd4u9AAXR2AuJxxPypsHMwr1KW7gRPecQIX3Ip7xWoxyrTz4b9nZkQA3 zeoTqSves77CJwPfUqrP86azQP+/j5MkVPAefvu1wtAg9VTava5J4JHXW0xeENWmjb bbIcfSN6NY/Jqs6ygGaNLchYKcS8qqOlPbqzfKyn0xMfQLap7DAGDVEDFD6J4XIwJD m87JsDBoBYfVg== Received: by wens.tw (Postfix, from userid 1000) id 0E7ED5FF9B; Sat, 06 Sep 2025 12:13:39 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v3 09/10] arm64: dts: allwinner: t527: avaota-a1: enable second Ethernet port Date: Sat, 6 Sep 2025 12:13:32 +0800 Message-Id: <20250906041333.642483-10-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250906041333.642483-1-wens@kernel.org> References: <20250906041333.642483-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Avaota A1 board, the second Ethernet controller, aka the GMAC200, is connected to a second external RTL8211F-CG PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-avaota-a1.dts | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index e7713678208d..f540965ffaa4 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -13,6 +13,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -67,7 +68,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_dcdc4>; =20 allwinner,tx-delay-ps =3D <100>; @@ -76,13 +77,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_dcdc4>; + + tx-internal-delay-ps =3D <100>; + rx-internal-delay-ps =3D <100>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -91,6 +103,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5 From nobody Tue Sep 9 16:20:05 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBB1B270EC5; Sat, 6 Sep 2025 04:13:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132024; cv=none; b=FP1901ioQyUUoITlJYImfXCrGn9MyIFKa6bGf18a1U/H6p50rRMJrMxNfgiLs8lQdc737fbxj0UM2yG66wJ3Jf4Xg95ImrmLdpFLOwzh1XRRGHO7ivlHTgCAwuCMs5Af1CNIylMXaZCHd/wxL4fr5lLEPBjxoPVlwivTs+dY1d0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757132024; c=relaxed/simple; bh=zJ4rq1A7rDmdHeQfB8ynFE9503F7ovKFxfivFN/5hPw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=V7r1VIeXS0+AIACkIWadDw7e/1ooES/8ycyr1LF6exOkEk+EAY8pmk4Ob3fVkSwKsepk4nh52FfJLim/sDYJkpYEbT4TfnH2f8hNvPFeN4yN3frA6F8kutweE3BmkNIWL8cK6QAtbb8Ev0R0hWMOkwBXHDjMrqVcGmvkhhBL5Ko= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VbR0ETCU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VbR0ETCU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BD2BC4CEFA; Sat, 6 Sep 2025 04:13:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757132024; bh=zJ4rq1A7rDmdHeQfB8ynFE9503F7ovKFxfivFN/5hPw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VbR0ETCUU5YXKOI/JSjxXA7DY30F2AY9PMf4cVATlrMDMmtUoZ/WgIbnTeXMrUcOc okbhJLTOmdIYaPITRU/ngiebOfcGVH4OoqAFihK+Aqa7dVwIysDt4q2nqkVSfjHq0s DXz5OzghxZ/Ry/xpjFhdiKnBG85PAfrIYSfTn8Gz1ES651wN4lgaqIrTphPpgfBzNU oRw/guM/hoSO8VS5sUC2WqAm0qAkikRLryt5pkLIB/4bCM6aAJHS2P417HK08LbZu1 Jd2MdUQ4XVgNRy5fpRY09ighAACxqCV/2Ue4vfAtUWJzOfbLArRWiHJxV8JI9Vg6X+ u+YT88w5EntvQ== Received: by wens.tw (Postfix, from userid 1000) id 1B6A55FF0D; Sat, 06 Sep 2025 12:13:39 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v3 10/10] arm64: dts: allwinner: t527: orangepi-4a: Enable Ethernet port Date: Sat, 6 Sep 2025 12:13:33 +0800 Message-Id: <20250906041333.642483-11-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250906041333.642483-1-wens@kernel.org> References: <20250906041333.642483-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Orangepi 4A board, the second Ethernet controller, aka the GMAC200, is connected to an external Motorcomm YT8531 PHY. The PHY uses an external 25MHz crystal, has the SoC's PI15 pin connected to its reset pin, and the PI16 pin for its interrupt pin. Enable it. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 38cd8c7e92da..7afd6e57fe86 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -15,6 +15,7 @@ / { compatible =3D "xunlong,orangepi-4a", "allwinner,sun55i-t527"; =20 aliases { + ethernet0 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -95,11 +96,33 @@ &ehci1 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <0>; + rx-internal-delay-ps =3D <300>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 +&mdio1 { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupts-extended =3D <&pio 8 16 IRQ_TYPE_LEVEL_LOW>; /* PI16 */ + reset-gpios =3D <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5