From nobody Tue Sep 9 16:21:04 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C03E7186E40; Sat, 6 Sep 2025 01:48:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757123339; cv=none; b=mFYJFNXvIwZagxVumGppEz9DwYIuM/m8Y05u6pYx08SFwk7pk17C7dNFcD3PWC+XtkH880Uj0TX68pI0lnYkYXiTabwg1mgo+lOmMQk9kJPiGz82h2FKSgyNxB1MVS5yXlu5xlEvW0rop59b2iZHjfHGEooLUG50S/ZyhYlQ8yk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757123339; c=relaxed/simple; bh=ZeZewhLsyLKNrLXp27L523l5O6hHKBkFOtMhLVkcFfE=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uHSfxWMmqjJAZDA3a2wTRiYIxXcm+/x8dNAcmdoNOiGsqFDXVIUn0PExgRdwpi4OS5QJ9kX66TOlMCSyw+kvInHURQgykjYz/umDXlinML6KsjSSfMol8M/bVd7vSoBW6cXfUmvl1uLtK8baMZgM8rzoVa886tbt4Uny0KVQShE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sat, 6 Sep 2025 09:48:46 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sat, 6 Sep 2025 09:48:46 +0800 From: Ryan Chen To: ryan_chen , Eddie James , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Lee Jones , , , , Subject: [PATCH v3 1/4] irqchip/aspeed-scu-ic: Refactor driver to support variant-based initialization Date: Sat, 6 Sep 2025 09:48:43 +0800 Message-ID: <20250906014846.861368-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250906014846.861368-1-ryan_chen@aspeedtech.com> References: <20250906014846.861368-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The original SCU IC driver handled each AST2600 instance with separate initialization functions and hardcoded register definitions. This patch consolidates the implementation by introducing a variant-based structure, selected via compatible string. The driver now uses a unified init path and MMIO access via of_iomap(). This simplifies the code and prepares for upcoming SoCs like AST2700, which require split register handling. Signed-off-by: Ryan Chen --- drivers/irqchip/irq-aspeed-scu-ic.c | 143 ++++++++++++---------------- 1 file changed, 59 insertions(+), 84 deletions(-) diff --git a/drivers/irqchip/irq-aspeed-scu-ic.c b/drivers/irqchip/irq-aspe= ed-scu-ic.c index 1c7045467c48..24d3d3fa5c4b 100644 --- a/drivers/irqchip/irq-aspeed-scu-ic.c +++ b/drivers/irqchip/irq-aspeed-scu-ic.c @@ -7,52 +7,52 @@ */ =20 #include +#include #include #include #include #include -#include +#include #include -#include =20 -#define ASPEED_SCU_IC_REG 0x018 -#define ASPEED_SCU_IC_SHIFT 0 -#define ASPEED_SCU_IC_ENABLE GENMASK(15, ASPEED_SCU_IC_SHIFT) -#define ASPEED_SCU_IC_NUM_IRQS 7 #define ASPEED_SCU_IC_STATUS GENMASK(28, 16) #define ASPEED_SCU_IC_STATUS_SHIFT 16 =20 -#define ASPEED_AST2600_SCU_IC0_REG 0x560 -#define ASPEED_AST2600_SCU_IC0_SHIFT 0 -#define ASPEED_AST2600_SCU_IC0_ENABLE \ - GENMASK(5, ASPEED_AST2600_SCU_IC0_SHIFT) -#define ASPEED_AST2600_SCU_IC0_NUM_IRQS 6 +struct aspeed_scu_ic_variant { + const char *compatible; + unsigned long irq_enable; + unsigned long irq_shift; + unsigned int num_irqs; +}; + +#define SCU_VARIANT(_compat, _shift, _enable, _num) { \ + .compatible =3D _compat, \ + .irq_shift =3D _shift, \ + .irq_enable =3D _enable, \ + .num_irqs =3D _num, \ +} =20 -#define ASPEED_AST2600_SCU_IC1_REG 0x570 -#define ASPEED_AST2600_SCU_IC1_SHIFT 4 -#define ASPEED_AST2600_SCU_IC1_ENABLE \ - GENMASK(5, ASPEED_AST2600_SCU_IC1_SHIFT) -#define ASPEED_AST2600_SCU_IC1_NUM_IRQS 2 +static const struct aspeed_scu_ic_variant scu_ic_variants[] __initconst = =3D { + SCU_VARIANT("aspeed,ast2400-scu-ic", 0, GENMASK(15, 0), 7), + SCU_VARIANT("aspeed,ast2500-scu-ic", 0, GENMASK(15, 0), 7), + SCU_VARIANT("aspeed,ast2600-scu-ic0", 0, GENMASK(5, 0), 6), + SCU_VARIANT("aspeed,ast2600-scu-ic1", 4, GENMASK(5, 4), 2), +}; =20 struct aspeed_scu_ic { - unsigned long irq_enable; - unsigned long irq_shift; - unsigned int num_irqs; - unsigned int reg; - struct regmap *scu; - struct irq_domain *irq_domain; + unsigned long irq_enable; + unsigned long irq_shift; + unsigned int num_irqs; + void __iomem *base; + struct irq_domain *irq_domain; }; =20 static void aspeed_scu_ic_irq_handler(struct irq_desc *desc) { - unsigned int sts; - unsigned long bit; - unsigned long enabled; - unsigned long max; - unsigned long status; struct aspeed_scu_ic *scu_ic =3D irq_desc_get_handler_data(desc); struct irq_chip *chip =3D irq_desc_get_chip(desc); - unsigned int mask =3D scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT; + unsigned long bit, enabled, max, status; + unsigned int sts, mask; =20 chained_irq_enter(chip, desc); =20 @@ -66,7 +66,7 @@ static void aspeed_scu_ic_irq_handler(struct irq_desc *de= sc) * shifting the status down to get the mapping and then back up to * clear the bit. */ - regmap_read(scu_ic->scu, scu_ic->reg, &sts); + sts =3D readl(scu_ic->base); enabled =3D sts & scu_ic->irq_enable; status =3D (sts >> ASPEED_SCU_IC_STATUS_SHIFT) & enabled; =20 @@ -76,9 +76,9 @@ static void aspeed_scu_ic_irq_handler(struct irq_desc *de= sc) for_each_set_bit_from(bit, &status, max) { generic_handle_domain_irq(scu_ic->irq_domain, bit - scu_ic->irq_shift); - - regmap_write_bits(scu_ic->scu, scu_ic->reg, mask, - BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT)); + writel((readl(scu_ic->base) & ~mask) | + BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT), + scu_ic->base); } =20 chained_irq_exit(chip, desc); @@ -95,7 +95,7 @@ static void aspeed_scu_ic_irq_mask(struct irq_data *data) * operation from clearing the status bits, they should be under the * mask and written with 0. */ - regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, 0); + writel(readl(scu_ic->base) & ~mask, scu_ic->base); } =20 static void aspeed_scu_ic_irq_unmask(struct irq_data *data) @@ -110,7 +110,7 @@ static void aspeed_scu_ic_irq_unmask(struct irq_data *d= ata) * operation from clearing the status bits, they should be under the * mask and written with 0. */ - regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, bit); + writel((readl(scu_ic->base) & ~mask) | bit, scu_ic->base); } =20 static int aspeed_scu_ic_irq_set_affinity(struct irq_data *data, @@ -146,18 +146,13 @@ static int aspeed_scu_ic_of_init_common(struct aspeed= _scu_ic *scu_ic, int irq; int rc =3D 0; =20 - if (!node->parent) { - rc =3D -ENODEV; + scu_ic->base =3D of_iomap(node, 0); + if (IS_ERR(scu_ic->base)) { + rc =3D PTR_ERR(scu_ic->base); goto err; } - - scu_ic->scu =3D syscon_node_to_regmap(node->parent); - if (IS_ERR(scu_ic->scu)) { - rc =3D PTR_ERR(scu_ic->scu); - goto err; - } - regmap_write_bits(scu_ic->scu, scu_ic->reg, ASPEED_SCU_IC_STATUS, ASPEED_= SCU_IC_STATUS); - regmap_write_bits(scu_ic->scu, scu_ic->reg, ASPEED_SCU_IC_ENABLE, 0); + writel(ASPEED_SCU_IC_STATUS, scu_ic->base); + writel(0, scu_ic->base); =20 irq =3D irq_of_parse_and_map(node, 0); if (!irq) { @@ -166,8 +161,7 @@ static int aspeed_scu_ic_of_init_common(struct aspeed_s= cu_ic *scu_ic, } =20 scu_ic->irq_domain =3D irq_domain_create_linear(of_fwnode_handle(node), s= cu_ic->num_irqs, - &aspeed_scu_ic_domain_ops, - scu_ic); + &aspeed_scu_ic_domain_ops, scu_ic); if (!scu_ic->irq_domain) { rc =3D -ENOMEM; goto err; @@ -184,57 +178,38 @@ static int aspeed_scu_ic_of_init_common(struct aspeed= _scu_ic *scu_ic, return rc; } =20 -static int __init aspeed_scu_ic_of_init(struct device_node *node, - struct device_node *parent) +static const struct aspeed_scu_ic_variant * +aspeed_scu_ic_find_variant(struct device_node *np) { - struct aspeed_scu_ic *scu_ic =3D kzalloc(sizeof(*scu_ic), GFP_KERNEL); - - if (!scu_ic) - return -ENOMEM; - - scu_ic->irq_enable =3D ASPEED_SCU_IC_ENABLE; - scu_ic->irq_shift =3D ASPEED_SCU_IC_SHIFT; - scu_ic->num_irqs =3D ASPEED_SCU_IC_NUM_IRQS; - scu_ic->reg =3D ASPEED_SCU_IC_REG; + for (int i =3D 0; i < ARRAY_SIZE(scu_ic_variants); i++) { + if (of_device_is_compatible(np, scu_ic_variants[i].compatible)) + return &scu_ic_variants[i]; + } =20 - return aspeed_scu_ic_of_init_common(scu_ic, node); + return NULL; } =20 -static int __init aspeed_ast2600_scu_ic0_of_init(struct device_node *node, - struct device_node *parent) +static int __init aspeed_scu_ic_of_init(struct device_node *node, struct d= evice_node *parent) { - struct aspeed_scu_ic *scu_ic =3D kzalloc(sizeof(*scu_ic), GFP_KERNEL); - - if (!scu_ic) - return -ENOMEM; + const struct aspeed_scu_ic_variant *variant; + struct aspeed_scu_ic *scu_ic; =20 - scu_ic->irq_enable =3D ASPEED_AST2600_SCU_IC0_ENABLE; - scu_ic->irq_shift =3D ASPEED_AST2600_SCU_IC0_SHIFT; - scu_ic->num_irqs =3D ASPEED_AST2600_SCU_IC0_NUM_IRQS; - scu_ic->reg =3D ASPEED_AST2600_SCU_IC0_REG; - - return aspeed_scu_ic_of_init_common(scu_ic, node); -} - -static int __init aspeed_ast2600_scu_ic1_of_init(struct device_node *node, - struct device_node *parent) -{ - struct aspeed_scu_ic *scu_ic =3D kzalloc(sizeof(*scu_ic), GFP_KERNEL); + variant =3D aspeed_scu_ic_find_variant(node); + if (!variant) + return -ENODEV; =20 + scu_ic =3D kzalloc(sizeof(*scu_ic), GFP_KERNEL); if (!scu_ic) return -ENOMEM; =20 - scu_ic->irq_enable =3D ASPEED_AST2600_SCU_IC1_ENABLE; - scu_ic->irq_shift =3D ASPEED_AST2600_SCU_IC1_SHIFT; - scu_ic->num_irqs =3D ASPEED_AST2600_SCU_IC1_NUM_IRQS; - scu_ic->reg =3D ASPEED_AST2600_SCU_IC1_REG; + scu_ic->irq_enable =3D variant->irq_enable; + scu_ic->irq_shift =3D variant->irq_shift; + scu_ic->num_irqs =3D variant->num_irqs; =20 return aspeed_scu_ic_of_init_common(scu_ic, node); } =20 IRQCHIP_DECLARE(ast2400_scu_ic, "aspeed,ast2400-scu-ic", aspeed_scu_ic_of_= init); IRQCHIP_DECLARE(ast2500_scu_ic, "aspeed,ast2500-scu-ic", aspeed_scu_ic_of_= init); -IRQCHIP_DECLARE(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0", - aspeed_ast2600_scu_ic0_of_init); -IRQCHIP_DECLARE(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1", - aspeed_ast2600_scu_ic1_of_init); +IRQCHIP_DECLARE(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0", aspeed_scu_ic_o= f_init); +IRQCHIP_DECLARE(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1", aspeed_scu_ic_o= f_init); --=20 2.34.1 From nobody Tue Sep 9 16:21:04 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28DA01C4A13; Sat, 6 Sep 2025 01:49:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sat, 6 Sep 2025 09:48:46 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sat, 6 Sep 2025 09:48:46 +0800 From: Ryan Chen To: ryan_chen , Eddie James , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Lee Jones , , , , Subject: [PATCH v3 2/4] dt-bindings: mfd: aspeed: Add AST2700 SCU compatibles Date: Sat, 6 Sep 2025 09:48:44 +0800 Message-ID: <20250906014846.861368-3-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250906014846.861368-1-ryan_chen@aspeedtech.com> References: <20250906014846.861368-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SCU interrupt controller compatible strings for the AST2700 SoC: scu-ic0 to 3. This extends the MFD binding to support AST2700-based platforms. Signed-off-by: Ryan Chen Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml = b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index 5eccd10d95ce..67be6d095fe4 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -75,6 +75,10 @@ patternProperties: - aspeed,ast2500-scu-ic - aspeed,ast2600-scu-ic0 - aspeed,ast2600-scu-ic1 + - aspeed,ast2700-scu-ic0 + - aspeed,ast2700-scu-ic1 + - aspeed,ast2700-scu-ic2 + - aspeed,ast2700-scu-ic3 =20 '^silicon-id@[0-9a-f]+$': description: Unique hardware silicon identifiers within the SoC --=20 2.34.1 From nobody Tue Sep 9 16:21:04 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32AEE1D31B9; Sat, 6 Sep 2025 01:49:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757123343; cv=none; b=DTH4QQrN8aPkt45+CF082KFGZYwRPseakjSKC5USuIQO6hBTjFVor1uZ6MYj8nx7OrbZwGSofbjESk3tE3ZKrwxcc5sLudnTJTNOFJgtkl7PvvVEMT552XMK/V+KKX1HAawQt//lWuuwbInFHgIuxnQwAchRY7lXji70mvHqP0c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757123343; c=relaxed/simple; bh=3ZeABG7RXzgMupXNgC3IgUTXs2QEJW0g6ibXeuKOE2s=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jnEmBu3aIxrAr789plucFAmlERkuaIBWPGq5zi9kW+X2cz87bVOHLMa/nbvgBm4MDB5VMrUW+78Ui3xUTYqQ2aF/pd1goL4RR9z9EdonrZ93eD4XzI27bPurWVZBAPYKhE4OZ9p66jE+bItH2DUJJY8vl/+JM2/QMoYnWLs9jAo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sat, 6 Sep 2025 09:48:46 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sat, 6 Sep 2025 09:48:46 +0800 From: Ryan Chen To: ryan_chen , Eddie James , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Lee Jones , , , , Subject: [PATCH v3 3/4] dt-bindings: interrupt-controller: aspeed: Add AST2700 SCU IC compatibles Date: Sat, 6 Sep 2025 09:48:45 +0800 Message-ID: <20250906014846.861368-4-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250906014846.861368-1-ryan_chen@aspeedtech.com> References: <20250906014846.861368-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible strings for the four SCU interrupt controller instances on the AST2700 SoC (scu-ic0 to 3), following the multi-instance model used on AST2600. Also define interrupt indices in the binding header. Signed-off-by: Ryan Chen Acked-by: Rob Herring (Arm) --- .../aspeed,ast2500-scu-ic.yaml | 6 +++++- .../interrupt-controller/aspeed-scu-ic.h | 14 ++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2500-scu-ic.yaml b/Documentation/devicetree/bindings/interrupt-controlle= r/aspeed,ast2500-scu-ic.yaml index d5287a2bf866..d998a9d69b91 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500= -scu-ic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500= -scu-ic.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2500-scu= -ic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Aspeed AST25XX and AST26XX SCU Interrupt Controller +title: Aspeed AST25XX, AST26XX, AST27XX SCU Interrupt Controller =20 maintainers: - Eddie James @@ -16,6 +16,10 @@ properties: - aspeed,ast2500-scu-ic - aspeed,ast2600-scu-ic0 - aspeed,ast2600-scu-ic1 + - aspeed,ast2700-scu-ic0 + - aspeed,ast2700-scu-ic1 + - aspeed,ast2700-scu-ic2 + - aspeed,ast2700-scu-ic3 =20 reg: maxItems: 1 diff --git a/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h b/inc= lude/dt-bindings/interrupt-controller/aspeed-scu-ic.h index f315d5a7f5ee..7dd04424afcc 100644 --- a/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h +++ b/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h @@ -20,4 +20,18 @@ #define ASPEED_AST2600_SCU_IC1_LPC_RESET_LO_TO_HI 0 #define ASPEED_AST2600_SCU_IC1_LPC_RESET_HI_TO_LO 1 =20 +#define ASPEED_AST2700_SCU_IC0_PCIE_PERST_LO_TO_HI 3 +#define ASPEED_AST2700_SCU_IC0_PCIE_PERST_HI_TO_LO 2 + +#define ASPEED_AST2700_SCU_IC1_PCIE_RCRST_LO_TO_HI 3 +#define ASPEED_AST2700_SCU_IC1_PCIE_RCRST_HI_TO_LO 2 + +#define ASPEED_AST2700_SCU_IC2_PCIE_PERST_LO_TO_HI 3 +#define ASPEED_AST2700_SCU_IC2_PCIE_PERST_HI_TO_LO 2 +#define ASPEED_AST2700_SCU_IC2_LPC_RESET_LO_TO_HI 1 +#define ASPEED_AST2700_SCU_IC2_LPC_RESET_HI_TO_LO 0 + +#define ASPEED_AST2700_SCU_IC3_LPC_RESET_LO_TO_HI 1 +#define ASPEED_AST2700_SCU_IC3_LPC_RESET_HI_TO_LO 0 + #endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ */ --=20 2.34.1 From nobody Tue Sep 9 16:21:04 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CBD31DE8BF; Sat, 6 Sep 2025 01:49:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757123346; cv=none; b=Oj7zu/7FvJQZl+RgITUVnKaW0+HgT9PrcqK8H0V0HmBCFBioEK1OKalrXsB/MvgPcg3mxxxO6ozmFxXwjV7aM7p6LsRTmBFyIlDIgBa1ylf/3mCnodx9Qh/LQ3HtrMTSwJuhGA0ECaYoTyU1vVwJWm68hqGmW3kdPeHrEQ9N7SA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757123346; c=relaxed/simple; bh=Dv8RWtAGXVai4jLnn5kg93giQ+Fw7LvlkApU1McGVMs=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ipov6LjFEa4dVrvnjsB4Zlp9VLkhDGZecl1gswBKC64B5nVyKB3NGGK4cZuViHC5RVQ3cXOYZub9oOC7N1GCH9f8tnsChH44Liv1OkP93tzjhuZNw9Z6JvZSs2aeTbze9MFz4JXEOLx5bF7+GMZRB92I7/Umwwjh96lpbL4+VlA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sat, 6 Sep 2025 09:48:46 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sat, 6 Sep 2025 09:48:46 +0800 From: Ryan Chen To: ryan_chen , Eddie James , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Lee Jones , , , , Subject: [PATCH v3 4/4] irqchip/aspeed-scu-ic: Add support AST2700 SCU interrupt controllers Date: Sat, 6 Sep 2025 09:48:46 +0800 Message-ID: <20250906014846.861368-5-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250906014846.861368-1-ryan_chen@aspeedtech.com> References: <20250906014846.861368-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AST2700 continues the multi-instance SCU interrupt controller model introduced in the AST2600, with four independent interrupt domains (scu-ic0 to 3). Unlike earlier generations that combine interrupt enable and status bits into a single register, the AST2700 separates these into distinct IER and ISR registers. Support for this layout is implemented by using register offsets and separate chained IRQ handlers. The variant table is extended to cover AST2700 IC instances, enabling shared initialization logic while preserving support for previous SoCs. Signed-off-by: Ryan Chen --- drivers/irqchip/irq-aspeed-scu-ic.c | 119 +++++++++++++++++++++++----- 1 file changed, 101 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-aspeed-scu-ic.c b/drivers/irqchip/irq-aspe= ed-scu-ic.c index 24d3d3fa5c4b..8c2df72353be 100644 --- a/drivers/irqchip/irq-aspeed-scu-ic.c +++ b/drivers/irqchip/irq-aspeed-scu-ic.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Aspeed AST24XX, AST25XX, and AST26XX SCU Interrupt Controller + * Aspeed AST24XX, AST25XX, AST26XX, and AST27XX SCU Interrupt Controller * Copyright 2019 IBM Corporation * * Eddie James @@ -17,26 +17,37 @@ =20 #define ASPEED_SCU_IC_STATUS GENMASK(28, 16) #define ASPEED_SCU_IC_STATUS_SHIFT 16 +#define AST2700_SCU_IC_STATUS GENMASK(15, 0) =20 struct aspeed_scu_ic_variant { const char *compatible; unsigned long irq_enable; unsigned long irq_shift; unsigned int num_irqs; + bool split_ier_isr; + unsigned long ier; + unsigned long isr; }; =20 -#define SCU_VARIANT(_compat, _shift, _enable, _num) { \ +#define SCU_VARIANT(_compat, _shift, _enable, _num, _split, _ier, _isr) { \ .compatible =3D _compat, \ .irq_shift =3D _shift, \ .irq_enable =3D _enable, \ .num_irqs =3D _num, \ + .split_ier_isr =3D _split, \ + .ier =3D _ier, \ + .isr =3D _isr, \ } =20 static const struct aspeed_scu_ic_variant scu_ic_variants[] __initconst = =3D { - SCU_VARIANT("aspeed,ast2400-scu-ic", 0, GENMASK(15, 0), 7), - SCU_VARIANT("aspeed,ast2500-scu-ic", 0, GENMASK(15, 0), 7), - SCU_VARIANT("aspeed,ast2600-scu-ic0", 0, GENMASK(5, 0), 6), - SCU_VARIANT("aspeed,ast2600-scu-ic1", 4, GENMASK(5, 4), 2), + SCU_VARIANT("aspeed,ast2400-scu-ic", 0, GENMASK(15, 0), 7, false, 0, 0), + SCU_VARIANT("aspeed,ast2500-scu-ic", 0, GENMASK(15, 0), 7, false, 0, 0), + SCU_VARIANT("aspeed,ast2600-scu-ic0", 0, GENMASK(5, 0), 6, false, 0, 0), + SCU_VARIANT("aspeed,ast2600-scu-ic1", 4, GENMASK(5, 4), 2, false, 0, 0), + SCU_VARIANT("aspeed,ast2700-scu-ic0", 0, GENMASK(3, 0), 4, true, 0x00, 0x= 04), + SCU_VARIANT("aspeed,ast2700-scu-ic1", 0, GENMASK(3, 0), 4, true, 0x00, 0x= 04), + SCU_VARIANT("aspeed,ast2700-scu-ic2", 0, GENMASK(3, 0), 4, true, 0x04, 0x= 00), + SCU_VARIANT("aspeed,ast2700-scu-ic3", 0, GENMASK(1, 0), 2, true, 0x04, 0x= 00), }; =20 struct aspeed_scu_ic { @@ -45,9 +56,12 @@ struct aspeed_scu_ic { unsigned int num_irqs; void __iomem *base; struct irq_domain *irq_domain; + bool split_ier_isr; + unsigned long ier; + unsigned long isr; }; =20 -static void aspeed_scu_ic_irq_handler(struct irq_desc *desc) +static void aspeed_scu_ic_irq_handler_combined(struct irq_desc *desc) { struct aspeed_scu_ic *scu_ic =3D irq_desc_get_handler_data(desc); struct irq_chip *chip =3D irq_desc_get_chip(desc); @@ -84,7 +98,33 @@ static void aspeed_scu_ic_irq_handler(struct irq_desc *d= esc) chained_irq_exit(chip, desc); } =20 -static void aspeed_scu_ic_irq_mask(struct irq_data *data) +static void aspeed_scu_ic_irq_handler_split(struct irq_desc *desc) +{ + struct aspeed_scu_ic *scu_ic =3D irq_desc_get_handler_data(desc); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + unsigned long bit, enabled, max, status; + unsigned int sts, mask; + + chained_irq_enter(chip, desc); + + mask =3D scu_ic->irq_enable; + sts =3D readl(scu_ic->base + scu_ic->isr); + enabled =3D sts & scu_ic->irq_enable; + sts =3D readl(scu_ic->base + scu_ic->isr); + status =3D sts & enabled; + + bit =3D scu_ic->irq_shift; + max =3D scu_ic->num_irqs + bit; + + for_each_set_bit_from(bit, &status, max) { + generic_handle_domain_irq(scu_ic->irq_domain, bit - scu_ic->irq_shift); + writel(BIT(bit), scu_ic->base + scu_ic->isr); // clear interrupt + } + + chained_irq_exit(chip, desc); +} + +static void aspeed_scu_ic_irq_mask_combined(struct irq_data *data) { struct aspeed_scu_ic *scu_ic =3D irq_data_get_irq_chip_data(data); unsigned int mask =3D BIT(data->hwirq + scu_ic->irq_shift) | @@ -98,7 +138,7 @@ static void aspeed_scu_ic_irq_mask(struct irq_data *data) writel(readl(scu_ic->base) & ~mask, scu_ic->base); } =20 -static void aspeed_scu_ic_irq_unmask(struct irq_data *data) +static void aspeed_scu_ic_irq_unmask_combined(struct irq_data *data) { struct aspeed_scu_ic *scu_ic =3D irq_data_get_irq_chip_data(data); unsigned int bit =3D BIT(data->hwirq + scu_ic->irq_shift); @@ -113,6 +153,22 @@ static void aspeed_scu_ic_irq_unmask(struct irq_data *= data) writel((readl(scu_ic->base) & ~mask) | bit, scu_ic->base); } =20 +static void aspeed_scu_ic_irq_mask_split(struct irq_data *data) +{ + struct aspeed_scu_ic *scu_ic =3D irq_data_get_irq_chip_data(data); + + writel(readl(scu_ic->base) & ~BIT(data->hwirq + scu_ic->irq_shift), + scu_ic->base + scu_ic->ier); +} + +static void aspeed_scu_ic_irq_unmask_split(struct irq_data *data) +{ + struct aspeed_scu_ic *scu_ic =3D irq_data_get_irq_chip_data(data); + unsigned int bit =3D BIT(data->hwirq + scu_ic->irq_shift); + + writel(readl(scu_ic->base) | bit, scu_ic->base + scu_ic->ier); +} + static int aspeed_scu_ic_irq_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force) @@ -120,17 +176,29 @@ static int aspeed_scu_ic_irq_set_affinity(struct irq_= data *data, return -EINVAL; } =20 -static struct irq_chip aspeed_scu_ic_chip =3D { - .name =3D "aspeed-scu-ic", - .irq_mask =3D aspeed_scu_ic_irq_mask, - .irq_unmask =3D aspeed_scu_ic_irq_unmask, - .irq_set_affinity =3D aspeed_scu_ic_irq_set_affinity, +static struct irq_chip aspeed_scu_ic_chip_combined =3D { + .name =3D "aspeed-scu-ic", + .irq_mask =3D aspeed_scu_ic_irq_mask_combined, + .irq_unmask =3D aspeed_scu_ic_irq_unmask_combined, + .irq_set_affinity =3D aspeed_scu_ic_irq_set_affinity, +}; + +static struct irq_chip aspeed_scu_ic_chip_split =3D { + .name =3D "ast2700-scu-ic", + .irq_mask =3D aspeed_scu_ic_irq_mask_split, + .irq_unmask =3D aspeed_scu_ic_irq_unmask_split, + .irq_set_affinity =3D aspeed_scu_ic_irq_set_affinity, }; =20 static int aspeed_scu_ic_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) { - irq_set_chip_and_handler(irq, &aspeed_scu_ic_chip, handle_level_irq); + struct aspeed_scu_ic *scu_ic =3D domain->host_data; + + if (scu_ic->split_ier_isr) + irq_set_chip_and_handler(irq, &aspeed_scu_ic_chip_split, handle_level_ir= q); + else + irq_set_chip_and_handler(irq, &aspeed_scu_ic_chip_combined, handle_level= _irq); irq_set_chip_data(irq, domain->host_data); =20 return 0; @@ -151,8 +219,14 @@ static int aspeed_scu_ic_of_init_common(struct aspeed_= scu_ic *scu_ic, rc =3D PTR_ERR(scu_ic->base); goto err; } - writel(ASPEED_SCU_IC_STATUS, scu_ic->base); - writel(0, scu_ic->base); + + if (scu_ic->split_ier_isr) { + writel(AST2700_SCU_IC_STATUS, scu_ic->base + scu_ic->isr); + writel(0, scu_ic->base + scu_ic->ier); + } else { + writel(ASPEED_SCU_IC_STATUS, scu_ic->base); + writel(0, scu_ic->base); + } =20 irq =3D irq_of_parse_and_map(node, 0); if (!irq) { @@ -167,7 +241,9 @@ static int aspeed_scu_ic_of_init_common(struct aspeed_s= cu_ic *scu_ic, goto err; } =20 - irq_set_chained_handler_and_data(irq, aspeed_scu_ic_irq_handler, + irq_set_chained_handler_and_data(irq, scu_ic->split_ier_isr ? + aspeed_scu_ic_irq_handler_split : + aspeed_scu_ic_irq_handler_combined, scu_ic); =20 return 0; @@ -205,6 +281,9 @@ static int __init aspeed_scu_ic_of_init(struct device_n= ode *node, struct device_ scu_ic->irq_enable =3D variant->irq_enable; scu_ic->irq_shift =3D variant->irq_shift; scu_ic->num_irqs =3D variant->num_irqs; + scu_ic->split_ier_isr =3D variant->split_ier_isr; + scu_ic->ier =3D variant->ier; + scu_ic->isr =3D variant->isr; =20 return aspeed_scu_ic_of_init_common(scu_ic, node); } @@ -213,3 +292,7 @@ IRQCHIP_DECLARE(ast2400_scu_ic, "aspeed,ast2400-scu-ic"= , aspeed_scu_ic_of_init); IRQCHIP_DECLARE(ast2500_scu_ic, "aspeed,ast2500-scu-ic", aspeed_scu_ic_of_= init); IRQCHIP_DECLARE(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0", aspeed_scu_ic_o= f_init); IRQCHIP_DECLARE(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1", aspeed_scu_ic_o= f_init); +IRQCHIP_DECLARE(ast2700_scu_ic0, "aspeed,ast2700-scu-ic0", aspeed_scu_ic_o= f_init); +IRQCHIP_DECLARE(ast2700_scu_ic1, "aspeed,ast2700-scu-ic1", aspeed_scu_ic_o= f_init); +IRQCHIP_DECLARE(ast2700_scu_ic2, "aspeed,ast2700-scu-ic2", aspeed_scu_ic_o= f_init); +IRQCHIP_DECLARE(ast2700_scu_ic3, "aspeed,ast2700-scu-ic3", aspeed_scu_ic_o= f_init); --=20 2.34.1