From nobody Tue Sep 9 21:30:30 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 419EB29CB32; Sat, 6 Sep 2025 20:17:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757189856; cv=none; b=XkxdMFaIONpwYRybJ9Yf4Xr9NpXMwTFSRQsxJdFnooZfTnj2Ymkjvb7w3JS6BBmY1Q1RjKRw5WjXCW4Hm6x9Vwr6Cld5trHOxScZIxF859nk9H3hE8VPop6NAzf3xOJHD5tYWC+CGn8iY0pyTlBOoIfl+FCe8augxqqh6Zk/4/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757189856; c=relaxed/simple; bh=J0Hl5jXSkgUDOuUrz4cdXPv31p4OJPbVVWkHvszXf+0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L68aEvuVnGAX0q8UTFsqaF4atAz/spg48im1y19OymsMrFXfzSWmVve88yTnfjGKZ5THNj+lmdvZYDbFhcptznamxNiJYXU9ZUMVVSroq2kMmop7EPCF0vYb8Q52oAP/G42XZruBKjJ3RufcBq2i+FK6ndHHX0cn5QESiQ6wrTg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=f2sbplfJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="f2sbplfJ" Received: by smtp.kernel.org (Postfix) with ESMTPS id A9914C116B1; Sat, 6 Sep 2025 20:17:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757189855; bh=J0Hl5jXSkgUDOuUrz4cdXPv31p4OJPbVVWkHvszXf+0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=f2sbplfJXzSlgKCh5bTwUmw2JWeL79KA5TuFMoZsFMcaAgQcoV7KLpW+XZmRRouG4 JzjqOWbKoh88VaCUlianfXLz4WYEGvpXydursgH3C6iCsGbvIt6WyIITX/i6M7cDQG ca4UI/t3iyvPkv+KWr/vs+62+mxabQdUhNHAYtAjuY6p3JMXG8pnYcUr7VF0vxC1TZ E2ITCmUABgbS4fkyIresNOq+kDzLYAJ3Er2a6T14rL+F9H2MbY7L27itrt0kwgo0Kh 7Spe8h+QM3MyvdHkm6WWh6DAimB8oGB6rFBtu2QQPHI9HnDpvtV6VdxJjtKz7VeWj2 Cxv0OPSFOXb0g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F92ACA0FED; Sat, 6 Sep 2025 20:17:35 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Sat, 06 Sep 2025 15:16:55 -0500 Subject: [PATCH v3 5/9] memory: tegra210: Support interconnect framework Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250906-t210-actmon-v3-5-1403365d571e@gmail.com> References: <20250906-t210-actmon-v3-0-1403365d571e@gmail.com> In-Reply-To: <20250906-t210-actmon-v3-0-1403365d571e@gmail.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Thierry Reding , Jonathan Hunter , Krzysztof Kozlowski , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757189854; l=14757; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=m5ZhfVIuvuh1I0mQ/EHdvDIqAYGB5EuPbVWBtkxLV64=; b=+961k4846RzewO4/gG2nQAmvms4a5mVlJoZaFuzlbK7ZZpMd2gOlu7csm8Vb98wbMKjWfyC2Z 0KKItvfhSMhDaWTdYA51e/Buq3xGXqsRZO9nWgoTWDZxDSL4Kn3nn/g X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling This makes mc and emc interconnect providers and allows for dynamic memory clock scaling. Signed-off-by: Aaron Kling --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/tegra210-emc-core.c | 272 +++++++++++++++++++++++++++= +++- drivers/memory/tegra/tegra210-emc.h | 23 +++ drivers/memory/tegra/tegra210.c | 81 +++++++++ 4 files changed, 375 insertions(+), 2 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index fc5a277918267ee8240f9fb9efeb80275db4790b..2d0be29afe2b9ebf9a0630ef7fb= 6fb43ff359499 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -55,6 +55,7 @@ config TEGRA210_EMC tristate "NVIDIA Tegra210 External Memory Controller driver" depends on ARCH_TEGRA_210_SOC || COMPILE_TEST select TEGRA210_EMC_TABLE + select PM_OPP help This driver is for the External Memory Controller (EMC) found on Tegra210 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegr= a/tegra210-emc-core.c index e96ca4157d48182574310f8caf72687bed7cc16a..8991592794c888f75b9e7d2e59d= 911e364ffba92 100644 --- a/drivers/memory/tegra/tegra210-emc-core.c +++ b/drivers/memory/tegra/tegra210-emc-core.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -87,6 +88,13 @@ =20 #define LPDDR2_MR4_SRR GENMASK(2, 0) =20 +/* + * Tegra210 memory layout can be 1 channel at 64-bit or 2 channels at 32-b= it + * each. Either way, the total bus width will always be 64-bit. + */ +#define DRAM_DATA_BUS_WIDTH_BYTES (64 / 8) +#define DDR 2 + static const struct tegra210_emc_sequence *tegra210_emc_sequences[] =3D { &tegra210_emc_r21021, }; @@ -1569,6 +1577,79 @@ static int tegra210_emc_set_rate(struct device *dev, return 0; } =20 +static void tegra_emc_rate_requests_init(struct tegra210_emc *emc) +{ + unsigned int i; + + for (i =3D 0; i < EMC_RATE_TYPE_MAX; i++) { + emc->requested_rate[i].min_rate =3D 0; + emc->requested_rate[i].max_rate =3D ULONG_MAX; + } +} + +static int emc_request_rate(struct tegra210_emc *emc, + unsigned long new_min_rate, + unsigned long new_max_rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req =3D emc->requested_rate; + unsigned long min_rate =3D 0, max_rate =3D ULONG_MAX; + unsigned int i; + int err; + + /* select minimum and maximum rates among the requested rates */ + for (i =3D 0; i < EMC_RATE_TYPE_MAX; i++, req++) { + if (i =3D=3D type) { + min_rate =3D max(new_min_rate, min_rate); + max_rate =3D min(new_max_rate, max_rate); + } else { + min_rate =3D max(req->min_rate, min_rate); + max_rate =3D min(req->max_rate, max_rate); + } + } + + if (min_rate > max_rate) { + dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", + __func__, type, min_rate, max_rate); + return -ERANGE; + } + + err =3D clk_set_rate(emc->clk, min_rate); + if (err) + return err; + + emc->requested_rate[type].min_rate =3D new_min_rate; + emc->requested_rate[type].max_rate =3D new_max_rate; + + return 0; +} + +static int emc_set_min_rate(struct tegra210_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req =3D &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret =3D emc_request_rate(emc, rate, req->max_rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + +static int emc_set_max_rate(struct tegra210_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req =3D &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret =3D emc_request_rate(emc, req->min_rate, rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + /* * debugfs interface * @@ -1641,7 +1722,7 @@ static int tegra210_emc_debug_min_rate_set(void *data= , u64 rate) if (!tegra210_emc_validate_rate(emc, rate)) return -EINVAL; =20 - err =3D clk_set_min_rate(emc->clk, rate); + err =3D emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; =20 @@ -1671,7 +1752,7 @@ static int tegra210_emc_debug_max_rate_set(void *data= , u64 rate) if (!tegra210_emc_validate_rate(emc, rate)) return -EINVAL; =20 - err =3D clk_set_max_rate(emc->clk, rate); + err =3D emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; =20 @@ -1758,6 +1839,185 @@ static void tegra210_emc_debugfs_init(struct tegra2= 10_emc *emc) &tegra210_emc_debug_temperature_fops); } =20 +static inline struct tegra210_emc * +to_tegra210_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra210_emc, icc_provider); +} + +static struct icc_node_data * +emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider =3D data; + struct icc_node_data *ndata; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id !=3D TEGRA_ICC_EMEM) + continue; + + ndata =3D kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + /* + * SRC and DST nodes should have matching TAG in order to have + * it set by default for a requested path. + */ + ndata->tag =3D TEGRA_MC_ICC_TAG_ISO; + ndata->node =3D node; + + return ndata; + } + + return ERR_PTR(-EPROBE_DEFER); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra210_emc *emc =3D to_tegra210_emc_provider(dst->provider); + unsigned long long peak_bw =3D icc_units_to_bps(dst->peak_bw); + unsigned long long avg_bw =3D icc_units_to_bps(dst->avg_bw); + unsigned long long rate =3D max(avg_bw, peak_bw); + int err; + + /* + * Tegra210 EMC runs on a clock rate of SDRAM bus. This means that + * EMC clock rate is twice smaller than the peak data rate because + * data is sampled on both EMC clock edges. + */ + do_div(rate, DDR * DRAM_DATA_BUS_WIDTH_BYTES); + rate =3D min_t(u64, rate, U32_MAX); + + err =3D emc_set_min_rate(emc, rate, EMC_RATE_ICC); + if (err) + return err; + + return 0; +} + +static int tegra_emc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 = *peak) +{ + *avg =3D 0; + *peak =3D 0; + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra210_emc *emc) +{ + const struct tegra_mc_soc *soc =3D emc->mc->soc; + struct icc_node *node; + int err; + + emc->icc_provider.dev =3D emc->dev; + emc->icc_provider.set =3D emc_icc_set; + emc->icc_provider.data =3D &emc->icc_provider; + emc->icc_provider.aggregate =3D soc->icc_ops->aggregate; + emc->icc_provider.xlate_extended =3D emc_of_icc_xlate_extended; + emc->icc_provider.get_bw =3D tegra_emc_icc_get_init_bw; + + icc_provider_init(&emc->icc_provider); + + /* create External Memory Controller node */ + node =3D icc_node_create(TEGRA_ICC_EMC); + if (IS_ERR(node)) { + err =3D PTR_ERR(node); + goto err_msg; + } + + node->name =3D "External Memory Controller"; + icc_node_add(node, &emc->icc_provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err =3D icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node =3D icc_node_create(TEGRA_ICC_EMEM); + if (IS_ERR(node)) { + err =3D PTR_ERR(node); + goto remove_nodes; + } + + node->name =3D "External Memory (DRAM)"; + icc_node_add(node, &emc->icc_provider); + + err =3D icc_provider_register(&emc->icc_provider); + if (err) + goto remove_nodes; + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->icc_provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + +static int tegra_emc_opp_table_init(struct tegra210_emc *emc) +{ + u32 hw_version =3D BIT(tegra_sku_info.soc_speedo_id); + struct dev_pm_opp *opp; + unsigned long rate; + int opp_token, err, max_opps, i; + + err =3D dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); + if (err < 0) { + dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err); + return err; + } + opp_token =3D err; + + err =3D dev_pm_opp_of_add_table(emc->dev); + if (err) { + if (err =3D=3D -ENODEV) + dev_warn(emc->dev, "OPP table not found, please update your device tree= \n"); + else + dev_err(emc->dev, "failed to add OPP table: %d\n", err); + + goto put_hw_table; + } + + max_opps =3D dev_pm_opp_get_opp_count(emc->dev); + if (max_opps <=3D 0) { + dev_err(emc->dev, "Failed to add OPPs\n"); + goto remove_table; + } + + if (emc->num_timings !=3D max_opps) { + dev_err(emc->dev, "OPP table does not match emc table\n"); + goto remove_table; + } + + for (i =3D 0; i < emc->num_timings; i++) { + rate =3D emc->timings[i].rate * 1000; + opp =3D dev_pm_opp_find_freq_exact(emc->dev, rate, true); + if (IS_ERR(opp)) { + dev_err(emc->dev, "Rate %lu not found in OPP table\n", rate); + goto remove_table; + } + + dev_pm_opp_put(opp); + } + + dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", + hw_version, clk_get_rate(emc->clk) / 1000000); + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(emc->dev); +put_hw_table: + dev_pm_opp_put_supported_hw(opp_token); + + return err; +} + static void tegra210_emc_detect(struct tegra210_emc *emc) { u32 value; @@ -1966,6 +2226,13 @@ static int tegra210_emc_probe(struct platform_device= *pdev) =20 tegra210_emc_debugfs_init(emc); =20 + err =3D tegra_emc_opp_table_init(emc); + if (!err) { + tegra_emc_rate_requests_init(emc); + tegra_emc_interconnect_init(emc); + } else if (err !=3D -ENODEV) + return err; + cd =3D devm_thermal_of_cooling_device_register(emc->dev, np, "emc", emc, &tegra210_emc_cd_ops); if (IS_ERR(cd)) { @@ -2050,6 +2317,7 @@ static struct platform_driver tegra210_emc_driver =3D= { .name =3D "tegra210-emc", .of_match_table =3D tegra210_emc_of_match, .pm =3D &tegra210_emc_pm_ops, + .sync_state =3D icc_sync_state, }, .probe =3D tegra210_emc_probe, .remove =3D tegra210_emc_remove, diff --git a/drivers/memory/tegra/tegra210-emc.h b/drivers/memory/tegra/teg= ra210-emc.h index 8988bcf1529072a7bdc93b185ebe0d51d82c1763..3c9142bfd5ae5c57bbc139e69e6= 2c893b50ce40c 100644 --- a/drivers/memory/tegra/tegra210-emc.h +++ b/drivers/memory/tegra/tegra210-emc.h @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include =20 @@ -784,6 +785,17 @@ enum { #define TRIM_REGS_SIZE 138 #define BURST_REGS_SIZE 221 =20 +enum emc_rate_request_type { + EMC_RATE_DEBUG, + EMC_RATE_ICC, + EMC_RATE_TYPE_MAX, +}; + +struct emc_rate_request { + unsigned long min_rate; + unsigned long max_rate; +}; + struct tegra210_emc_per_channel_regs { u16 bank; u16 offset; @@ -932,6 +944,17 @@ struct tegra210_emc { } debugfs; =20 struct tegra210_clk_emc_provider provider; + + struct icc_provider icc_provider; + + /* + * There are multiple sources in the EMC driver which could request + * a min/max clock rate, these rates are contained in this array. + */ + struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX]; + + /* protect shared rate-change code path */ + struct mutex rate_lock; }; =20 struct tegra210_emc_sequence { diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra21= 0.c index cfa61dd885577a8fbd79c396a1316101197ca1f2..20828a07d2d0cafa739b534c20c= 12f065b276669 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -3,6 +3,9 @@ * Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved. */ =20 +#include +#include + #include =20 #include "mc.h" @@ -1273,6 +1276,83 @@ static const struct tegra_mc_reset tegra210_mc_reset= s[] =3D { TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13), }; =20 +static int tegra210_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + /* TODO: program PTSA */ + return 0; +} + +static int tegra210_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 a= vg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + /* + * ISO clients need to reserve extra bandwidth up-front because + * there could be high bandwidth pressure during initial filling + * of the client's FIFO buffers. Secondly, we need to take into + * account impurities of the memory subsystem. + */ + if (tag & TEGRA_MC_ICC_TAG_ISO) + peak_bw =3D tegra_mc_scale_percents(peak_bw, 400); + + *agg_avg +=3D avg_bw; + *agg_peak =3D max(*agg_peak, peak_bw); + + return 0; +} + +static struct icc_node_data * +tegra210_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void= *data) +{ + struct tegra_mc *mc =3D icc_provider_to_tegra_mc(data); + const struct tegra_mc_client *client; + unsigned int i, idx =3D spec->args[0]; + struct icc_node_data *ndata; + struct icc_node *node; + + list_for_each_entry(node, &mc->provider.nodes, node_list) { + if (node->id !=3D idx) + continue; + + ndata =3D kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + client =3D &mc->soc->clients[idx]; + ndata->node =3D node; + + switch (client->swgroup) { + case TEGRA_SWGROUP_DC: + case TEGRA_SWGROUP_DCB: + case TEGRA_SWGROUP_PTC: + case TEGRA_SWGROUP_VI: + /* these clients are isochronous by default */ + ndata->tag =3D TEGRA_MC_ICC_TAG_ISO; + break; + + default: + ndata->tag =3D TEGRA_MC_ICC_TAG_DEFAULT; + break; + } + + return ndata; + } + + for (i =3D 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id =3D=3D idx) + return ERR_PTR(-EPROBE_DEFER); + } + + dev_err(mc->dev, "invalid ICC client ID %u\n", idx); + + return ERR_PTR(-EINVAL); +} + +static const struct tegra_mc_icc_ops tegra210_mc_icc_ops =3D { + .xlate_extended =3D tegra210_mc_of_icc_xlate_extended, + .aggregate =3D tegra210_mc_icc_aggregate, + .set =3D tegra210_mc_icc_set, +}; + const struct tegra_mc_soc tegra210_mc_soc =3D { .clients =3D tegra210_mc_clients, .num_clients =3D ARRAY_SIZE(tegra210_mc_clients), @@ -1286,5 +1366,6 @@ const struct tegra_mc_soc tegra210_mc_soc =3D { .reset_ops =3D &tegra_mc_reset_ops_common, .resets =3D tegra210_mc_resets, .num_resets =3D ARRAY_SIZE(tegra210_mc_resets), + .icc_ops =3D &tegra210_mc_icc_ops, .ops =3D &tegra30_mc_ops, }; --=20 2.50.1